CN112310063A - 半导体装置封装及其制造方法 - Google Patents

半导体装置封装及其制造方法 Download PDF

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Publication number
CN112310063A
CN112310063A CN201910927114.3A CN201910927114A CN112310063A CN 112310063 A CN112310063 A CN 112310063A CN 201910927114 A CN201910927114 A CN 201910927114A CN 112310063 A CN112310063 A CN 112310063A
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China
Prior art keywords
semiconductor die
substrate
device package
semiconductor device
cavity
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CN201910927114.3A
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Inventor
颜尤龙
博恩·卡尔·艾皮特
凯·史提芬·艾斯格
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Publication of CN112310063A publication Critical patent/CN112310063A/zh
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Abstract

本公开涉及一种半导体装置封装及其制造方法。一种半导体装置封装包含衬底、堆叠结构和包封层。所述衬底包含电路层、第一表面和与所述第一表面相对的第二表面。所述衬底限定穿过所述衬底的至少一个空腔。所述堆叠结构包含安置于所述第一表面上并电性连接于所述电路层上的第一半导体裸片，以及堆叠于所述第一半导体裸片上并电性连接到所述第一半导体裸片的至少一个第二半导体裸片。所述第二半导体裸片至少部分插入所述空腔中。所述包封层安置在所述空腔中且至少完全地包封所述第二半导体裸片。

Description

半导体装置封装及其制造方法
技术领域
本公开涉及一种半导体装置封装及其制造方法，且涉及一种包含部分嵌入衬底的空腔中并由包封层包封的堆叠结构的半导体装置封装及其制造方法。
背景技术
堆叠裸片结构具有较厚的厚度，其限制半导体装置封装的小型化。已尝试通过在衬底中嵌入半导体裸片来减小半导体装置封装的厚度，然而，所嵌入的半导体裸片无法很好地成型且模制化合物可能污染衬底的接合垫。另外，需要插入件来使半导体裸片互连，这增加了半导体装置封装的成本及厚度。
发明内容
在一些实施例中，一种半导体装置封装包含衬底、堆叠结构及包封层。衬底包含电路层、第一表面和与第一表面相对的第二表面。衬底限定穿过所述衬底的至少一个空腔，及从第二表面凹入并部分暴露电路层的至少一个凹部。堆叠结构包含安置于第一表面上并电性连接于电路层上的第一半导体裸片，及堆叠在第一半导体裸片上并电性连接到第一半导体裸片的至少一个第二半导体裸片。第二半导体裸片至少部分插入空腔中。包封层安置在空腔中且至少包封第二半导体裸片。包封层进一步包含突出空腔并部分地覆盖衬底的第二表面的突出部分。
在一些实施例中，一种半导体装置封装包含衬底、堆叠结构及包封层。衬底包含电路层、第一表面和与第一表面相对的第二表面。衬底限定穿过所述衬底的至少一个空腔。堆叠结构包含安置于第一表面上并电性连接于电路层上的第一半导体裸片，及堆叠于第一半导体裸片上并电性连接到第一半导体裸片的至少一个第二半导体裸片。第二半导体裸片至少部分插入空腔中。包封层安置在空腔中且至少完全地包封第二半导体裸片。
在一些实施例中，一种用于制造半导体装置封装的方法包含以下步骤。接收限定空腔的衬底。接收包含第一半导体裸片和堆叠于第一半导体裸片上的至少一个第二半导体裸片的堆叠结构。利用至少部分插入空腔中的第二半导体裸片将第一半导体裸片接合到衬底的第一表面。将模制材料填充于空腔中以在空腔中形成包封层，从而至少完全地包封第二半导体裸片。
附图说明
结合附图阅读以下详细描述易于理解本公开的一些实施例的各方面。各种结构可能未按比例绘制，且各种结构的尺寸可出于论述的清楚起见而任意增大或减小。
图1是根据本公开的一些实施例的半导体装置封装的横截面视图。
图1A是根据本公开的一些实施例的图1的半导体装置封装的仰视图。
图2A是根据本公开的一些实施例的半导体装置封装的横截面视图。
图2B是根据本公开的一些实施例的半导体装置封装的横截面视图。
图2C是根据本公开的一些实施例的半导体装置封装的横截面视图。
图2D是根据本公开的一些实施例的半导体装置封装的横截面视图。
图2E是根据本公开的一些实施例的半导体装置封装的横截面视图。
图2F是根据本公开的一些实施例的半导体装置封装的横截面视图。
图2G是根据本公开的一些实施例的半导体装置封装的横截面视图。
图2H是根据本公开的一些实施例的半导体装置封装的横截面视图。
图2I是根据本公开的一些实施例的半导体装置封装的横截面视图。
图3是根据本公开的一些实施例的半导体装置封装的横截面视图。
图3A是根据本公开的一些实施例的图3的半导体装置封装的仰视图。
图4是根据本公开的一些实施例的半导体装置封装的横截面视图。
图5A、图5B、图5C、图5D和图5E说明根据本公开的一些实施例的制造半导体装置封装的操作。
图6是根据本公开的一些实施例的半导体装置封装的横截面视图。
图7是根据本公开的一些实施例的半导体装置封装的横截面视图。
图8A、图8B、图8C、图8D和图8E说明根据本公开的一些实施例的制造半导体装置封装的操作。
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同实施例或实例。下文描述组件和布置的具体实例来阐释本公开的某些方面。当然，这些只是实例且并不意图为限制性的。举例来说，在以下描述中，第一特征形成于第二特征上方或上可包含其中第一特征和第二特征直接地形成或安置的实施例，且还可包含其中额外特征形成或安置在第一特征与第二特征之间使得第一特征和第二特征并不直接接触的实施例。另外，本公开可以在各种实例中重复附图标号及/或字母。此重复是出于简化和清楚的目的，且本身并不规定所论述的各种实施例和/或配置之间的关系。
如本文中所使用，为易于描述，可在本文中使用如“在…下面”、“在…下方”、“下部”、“在…上方”、“上部”、“左侧”、“右侧”和其类似物的空间相对术语来描述如图中所说明的一个元件或特征与另一元件或特征的关系。除图中所描绘的定向之外，空间相对术语意图涵盖装置在使用或操作中的不同定向。装置可以其它方式定向(旋转90度或处于其它定向)，且本文中所使用的空间相关描述词也可相应地进行解释。应理解，当元件被称为“连接到”或“耦接到”另一元件时，其可直接连接或耦接到所述另一元件，或可存在介入元件。
如本文中所使用，术语“与...齐平”可用于描述一个元件或特征的表面与另一元件或特征的表面基本上共面。如本文中所使用，术语“与...对准”可用于描述一个元件或特征的表面与另一元件或特征的表面基本上共面。
图1是根据本公开的一些实施例的半导体装置封装1的横截面视图，且图1A是根据本公开的一些实施例的图1的半导体装置封装1的仰视图。如图1、图1A中所展示，半导体装置封装1包含衬底10、堆叠结构20和包封层50。衬底10包含第一表面101(例如上表面)和第二表面102(例如与第一表面101相对的底表面)。衬底10包含电路层12。在一些实施例中，衬底10的基底材料可包含介电材料、绝缘材料或半导体材料。举例来说，衬底10可包含有机衬底，例如核心衬底、无核心衬底或其它合适的衬底。在一些实施例中，电路层12可包含堆叠于其上且彼此电性连接的一或多个导电层12C。电路层12可进一步包含安置在第二表面102上、与所述第二表面邻近安置或嵌入所述第二表面中且通过所述第二表面暴露的接合垫(其也可称为接触垫、凸块下金属(UBM)或其组合)12P1，以及安置在第一表面101上、与所述第一表面邻近安置或嵌入所述第一表面中且通过所述第一表面暴露的接合垫(其也可称为接触垫、凸块下金属(UBM)或其组合)12P2。接合垫12P1和接合垫12P2可电性连接到导电层12C。衬底10可限定穿过所述衬底10的至少一个空腔10C。空腔10C可包含如图1A所示的多边形形状例如矩形形状、圆形形状或其它形状。衬底10可进一步限定从第二表面102凹入且部分暴露电路层12的至少一个凹部10R。举例来说，凹部10R可部分暴露电路层12的接合垫12P1。凹部10R可包含如图1A所示的圆形形状、多边形形状(例如矩形形状)或其它形状。在一些实施例中，接合垫12P1的周边区域可由衬底10覆盖，且接合垫12P1的中心区域可通过衬底10暴露。在一些实施例中，接合垫12P1可通过凹部10R从衬底10的第二表面102凹入。在一些实施例中，接合垫12P2可基本上与衬底10的第一表面101齐平。凹部10R可包含靠近空腔10C的第一侧向边缘10R1和远离空腔10C的第二侧向边缘10R2。
堆叠结构20包含至少一个第一半导体裸片30和至少一个第二半导体裸片40。第一半导体裸片安置于衬底10的第一表面101上并且在电路层12上电性连接。第二半导体裸片40堆叠于第一半导体裸片30上并电性连接到第一半导体裸片30。第二半导体裸片40至少部分插入空腔10C中。举例来说，第二半导体裸片40可部分或完全插入空腔10C中，以使得可减小半导体装置封装1的厚度.在一些实施例中，第一半导体裸片30和第二半导体裸片40可包含不同类型的半导体裸片。举例来说，第一半导体裸片30可包含片上系统(SOC)裸片，且至少一个第二半导体裸片40可包含存储器裸片，例如高带宽存储器(HBM)裸片。然而，第一半导体裸片30和第二半导体裸片40各自可包含主动裸片或被动裸片。
半导体装置1可进一步包含多个互连结构32，所述多个互连结构安置于衬底10的第一表面101与第一半导体裸片30之间并将第一半导体裸片30电性连接到电路层12。在一些实施例中，互连结构32可例如但不限于包含导电凸块321和焊料322。导电凸块321(例如微凸块、导电柱、导电螺柱或类似物)可安置在第一半导体裸片30上并电性连接到所述第一半导体裸片30。焊料322(例如焊料凸块、焊膏或类似物)可安置于导电凸块321与接合垫12P2之间并将导电凸块321电性连接到接合垫12P2。在一些实施例中，导电凸块321和焊料322的方位可互换，且互连结构32可另外包含其它导电结构，例如UBM或类似物。
堆叠结构20可包含袋鼠裸片(kangaroo die)结构，其中第一半导体裸片30和第二半导体裸片40在插入空腔10C中之前事先接合且彼此电性连接。在一些实施例中，第一半导体裸片30可配置为母裸片，且第二半导体裸片40可配置为子裸片。第一半导体裸片30和第二半导体裸片40各自可包含集成电路(IC)。第一半导体裸片30和第二半导体裸片40各自可包含具有可兼容的线宽/线距(L/S)和间距的重布层(RDL)，且因此第一半导体裸片30和第二半导体裸片40可直接地彼此连通。第一半导体裸片30和第二半导体裸片40可通过半导体制作和设备形成，且第一半导体裸片30和第二半导体裸片40的L/S可减小到例如小于约10μm/约102μm或甚至约2μm/约2μm。第一半导体裸片30与第二半导体裸片40之间的电性连接可以是其中可省略额外的插入件或互连衬底的无衬底连接。因此，可减小电气传输路径以及堆叠结构20的厚度，且可增加I/O连接。在一些实施例中，第一半导体裸片30的主动表面(即前表面)30A面向第二半导体裸片40的主动表面40A。半导体装置1可进一步包含多个导电结构34，所述多个导电结构安置于第二半导体裸片40的主动表面40A与第一半导体裸片30的主动表面30A之间并将第二半导体裸片40电性连接到第一半导体裸片30。
在一些实施例中，导电结构34可例如但不限于包含导电凸块341和焊料342。导电凸块341(例如微凸块、导电柱、导电螺柱或类似物)可安置于第二半导体裸片40的主动表面40A上并且电性连接到第二半导体裸片40的主动表面40A。焊料342(例如焊料凸块、焊膏或类似物)可安置于导电凸块341与第一半导体裸片30的主动表面30A之间并将导电凸块342电性连接到第一半导体裸片30。在一些实施例中，导电凸块341和焊料342的方位可互换，且导电结构34可另外包含其它导电结构，例如凸块下金属(UBM)或类似物。因为可减小第一半导体裸片30和第二半导体裸片40的L/S，所有导电结构34可包含微导电结构。因此,可提高导电结构34的产量和密度。
在一些实施例中，导电结构34的熔点与互连结构32的熔点不同。举例来说，导电结构34的熔点比互连结构32的熔点更高，使得导电结构34在互连结构32的回流工艺期间并未软化或熔化。在一些实施例中，导电结构34的焊料342的熔点比互连结构32的焊料322的熔点更高。举例来说，导电结构34的焊料342的熔点高于约280℃或高于300℃，且互连结构32的焊料322的熔点低于约280℃或低于260℃。焊料342的材料的实例可包含金(Au)和锡(Sn)的掺杂物，且焊料322的材料的实例可包含锡(Sn)和铅(Pb)的掺杂物或锡(Sn)、银(Ag)和铜(Cu)的掺杂物。
包封层50安置在空腔10C中，且至少包封第二半导体裸片40。包封层50可完全地包封第二半导体裸片40。举例来说，包封层50可包封第二半导体裸片40的主动表面40A、被动表面(即背面)40B和侧壁40C。包封层50可配置为模制底填充物(MUF)，并安置于半导体裸片30与第二半导体裸片40之间以包封导电结构34。包封层50可进一步包封第一半导体裸片30的侧壁30C。包封层50还可包封第一半导体裸片30的被动表面30B。包封层50的材料可包含模制材料，例如环氧树脂或类似物。在一些实施例中，包封层50可进一步包含填充剂，例如氧化硅填充剂或类似物。
包封层50进一步包含突出空腔10C且至少部分覆盖衬底102的第二表面102的突出部分50P。接合垫12P1可在竖直突出方向P上与包封层50的突出部分50P部分交叠。在一些实施例中，包封层50的突出部分50P的第一边缘50P1基本上与凹部10R的第一侧向边缘10R1对准。如图1A中所展示，不同凹部10R的第一侧向边缘50P1的长度和形状可不同。举例来说，凹部10R(例如对应于空腔10C的拐角10C1的凹部10R)的第一侧向边缘10R1可以是凹部10R周长的四分之一，而凹部10R(例如对应于空腔10C的一侧10C2的凹部10R)的第一侧向边缘10R1可以是凹部10R的周长的一半。在一些实施例中，包封层50的突出部分50P可包含非平面表面50S。举例来说，非平面表面50S可包含凸面。在一些其它实施例中，非平面表面50S可包含凹面、粗糙表面或其它规则或不规则形状。在一些其它实施例中，包封层50的突出部分50P可包含平面表面或平面表面和非平面表面的组合。
在本公开的一些实施例中，半导体装置封装1包含堆叠结构20，所述堆叠结构部分插入衬底10的空腔10C中以使得可减小半导体装置封装1的厚度。堆叠结构20通过包封层50包封和保护，且因此可提高半导体装置封装1的可靠性。堆叠结构20包含彼此堆叠且彼此电性连接的第一半导体裸片30和第二半导体裸片40。第一半导体裸片30与第二半导体裸片40之间的电性连接可以是其中可省略额外的插入件或互连衬底的无衬底连接。因此，可缩短堆叠结构20的电传输路径，可进一步减小半导体装置封装1的厚度，且可增加I/O连接。
本公开的半导体装置封装和制造方法不限于上述实施例，且可根据其它实施例来实施。为了简化描述且出于方便在本公开的各种实施例之间进行比较，以下实施例中的类似组件标记有相同标号，且可能并不过多地加以描述。
图2A为根据本公开的一些实施例的半导体装置封装2A的横截面视图。相比于图1中的半导体装置封装1，半导体装置封装2A可进一步包含至少一个电导体14，所述电导体安置于衬底10的第二表面102上且通过凹部10R电性连接到电路层12。在一些实施例中，电导体14可包含焊球或类似物。
图2B为根据本公开的一些实施例的半导体装置封装2B的横截面视图。相比于图2A中的半导体装置封装2A，半导体装置封装2B可进一步包含封装衬底60，例如印刷电路板(PCB)或类似物。衬底10可通过电导体14接合到封装衬底60。突出部分50P可与封装衬底60接触或与封装衬底60隔开。
图2C为根据本公开的一些实施例的半导体装置封装2C的横截面视图。相比于图1中的半导体装置封装1，包封层50可暴露第一半导体裸片30的被动表面30B。半导体装置封装2C可进一步包含散热层62，所述散热层安置于第一半导体裸片30的被动表面30B上以提高散热效果。在一些实施例中，可选择散热层62的热膨胀系数(CTE)、弹性模量和/或厚度以减轻压力和弯曲。散热层62的材料可包含例如金属的导电材料、绝缘材料或其它合适的材料。
图2D为根据本公开的一些实施例的半导体装置封装2D的横截面视图。相比于图1中的半导体装置封装1，半导体装置封装2D可包含底填充物层33，所述底填充物层安置于第二半导体裸片40的主动表面40A与第一半导体裸片30的主动表面30A之间且包围导电结构34。在一些实施例中，互连结构32的熔点可与导电结构34的熔点相同或不同。举例来说，互连结构32的焊料322的熔点可与导电结构34的焊料342的熔点相同或不同。包围导电结构34的底填充物层33可防止导电结构34在互连结构32的回流工艺期间变形。
图2E为根据本公开的一些实施例的半导体装置封装2E的横截面视图。相比于图1中的半导体装置封装1，堆叠结构20可包含堆叠于第一半导体裸片30上的两个或更多个第二半导体裸片40。在一些实施例中，第二半导体裸片40可安置在相同空腔10C中。在一些实施例中，半导体裸片40可在基本上相同水平处并列布置，且第二半导体裸片40中的每一个可通过第一半导体裸片30彼此连通。
图2F为根据本公开的一些实施例的半导体装置封装2F的横截面视图。相比于图2E中的半导体装置封装2E，多个第二半导体裸片40可安置在不同空腔10C中且电性连接到相同的第一半导体裸片30。
图2G为根据本公开的一些实施例的半导体装置封装2G的横截面视图。相比于图1中的半导体装置封装1，第一半导体裸片30的主动表面30A面向第二半导体裸片40的被动表面40B。例如，第二半导体裸片40的被动表面40B可通过裸片附接膜(DAF)35附接到第一半导体裸片30的主动表面30A。半导体装置封装2G可包含接线36代替导电结构34，以将第二半导体裸片40电性连接到第一半导体裸片30。
图2H为根据本公开的一些实施例的半导体装置封装2H的横截面视图。相比于图2G中的半导体装置封装2G，堆叠结构20可包含堆叠于第一半导体裸片30上的两个或更多个第二半导体裸片40。在一些实施例中，第二半导体裸片40可安置在相同空腔10C中。在一些实施例中，半导体裸片40可在基本上相同的水平处并列布置，且第二半导体裸片40中的每一个可通过接线36的部分电性连接到第一半导体裸片30。第二半导体裸片40还可通过接线36的另一部分彼此连通。
图2I为根据本公开的一些实施例的半导体装置封装2I的横截面视图。相比于图2H中的半导体装置封装2H，堆叠结构20可包含彼此堆叠的两个或更多个第二半导体裸片40。第二半导体裸片40的第一组401通过导电结构34电性连接到第一半导体裸片30，且第二半导体裸片40的第一组401的主动表面40A面向第一半导体裸片30的主动表面30A。第二半导体裸片40的第二组402可堆叠于第二半导体裸片40的第一组401上，且第二半导体裸片40的第二组402的被动表面40B面向第二半导体裸片40的第一组401的被动表面40B。第二半导体裸片40的第二组402可电性连接到第二半导体裸片40的第一组401和/或通过接线36电性连接到第一半导体裸片30。
图3是根据本公开的一些实施例的半导体装置封装3的横截面视图，且图3A是根据本公开的一些实施例的图3的半导体装置封装5的仰视图。相比于图1中的半导体装置封装1，包封层50的突出部分50P可向外延伸以便进一步安置于凹部10R的第二侧向边缘10R2与衬底10的边界10E之间。突出部分50P可包含邻近凹部10R的第一侧向边缘10R1的第一边缘50P1，及邻近凹部10R的第二侧向边缘10R2的第二边缘50P2。在一些实施例中，突出部分50P的第一边缘50P1基本上与凹部10R的第一侧向边缘10R1对准，且突出部分50P的第二边缘50P2基本上与凹部10R的第二侧向边缘10R2对准。突出部分50P的外边缘50PE可基本上与衬底10的边界10E对准，或可从衬底10的边界10E凹入。半导体装置封装3可经修改以进一步包含散热层62和/或底填充物层33，从而改变第一半导体裸片30与第二半导体裸片40之间的连接，以及以类似于如图2A-2I中所示的实施例的方式改变第二半导体裸片40相对于空腔10C的方位。
图4是根据本公开的一些实施例的半导体装置封装4的横截面视图。相比于图3中的半导体装置封装3，半导体装置封装4可进一步包含至少一个电导体14，所述电导体安置于衬底10的第二表面102上且通过凹部10R电性连接到电路层12。在一些实施例中，电导体14可包含焊球或类似物。在一些实施例中，半导体装置封装4可进一步包含封装衬底60，例如印刷电路板或类似物。半导体装置封装4可经修改以进一步包含散热层62和/或底填充物层33，从而改变第一半导体裸片30与第二半导体裸片40之间的连接，以及以类似于如图2A-2I中所示的实施例的方式改变第二半导体裸片40相对于空腔10C的方位。
图5A、图5B、图5C、图5D和图5E说明根据本公开的一些实施例的制造半导体装置封装的操作。如图5A中所展示，接收衬底10。衬底10可包含预先形成的电路层12。衬底10限定穿过所述衬底10的至少一个空腔10C。衬底10可进一步包含电路层12。电路层12可包含邻近衬底10的第二表面102的接合垫12P1和邻近衬底10的第一表面101的接合垫12P2。在一些实施例中，接合垫12P1嵌入衬底10中且未从第二表面102暴露。在一些其它实施例中，接合垫12P1可从衬底10的第二表面102暴露但覆盖有暂时性钝化层。接合垫12P2可从衬底10的第一表面101暴露。在一些实施例中，支撑件70附接到衬底10的第二表面102以密封空腔10C的底部。在一些实施例中，支撑件70可包含但不限于柔性支撑件。举例来说，柔性支撑件可包含条带，例如味之素堆积膜(Ajinomoto Build-up Film，ABF)或类似物。
如图5B中所展示，接收堆叠结构20。堆叠结构20可包含第一半导体裸片30和堆叠于第一半导体裸片40上并电性连接第一半导体裸片40的至少一个第二半导体裸片40。第一半导体裸片30和第二半导体裸片40可通过导电结构34接合。在一些实施例中，底填充物层33可形成于第一半导体裸片30与第一半导体裸片40之间并包围导电结构34。在一些实施例中，例如当导电结构34的焊料342的熔点高于互连结构32的焊料322的熔点时，可省略底填充物层33。第一半导体裸片30和第一半导体裸片40可通过导电结构34通过直接接合(例如共熔接合)进行接合。举例来说，导电凸块341可通过例如电镀在第二半导体裸片40上形成，且焊料342可通过例如电镀在导电凸块341上形成。第一半导体裸片30和第一半导体裸片40可随后通过回流工艺接合。
如图5C中所展示，第一半导体裸片30利用至少部分插入空腔10C中的第二半导体裸片40接合到衬底10的第一表面101。在一些实施例中，第一半导体裸片30通过互连结构32接合到衬底10并电性连接到从衬底10的第一表面101暴露的接合垫12P2。第一半导体裸片30和衬底10可通过互连结构32通过直接接合(例如共熔接合)进行接合。举例来说，导电凸块321可通过例如电镀在第一半导体裸片30上形成，且焊料322可通过例如电镀在导电凸块321上形成。第一半导体裸片30和衬底10可随后通过回流工艺接合。包围导电结构34的底填充物层33可防止导电结构34(例如导电结构34的焊料342)在互连结构32的回流工艺期间变形。或者或另外，导电结构34的焊料342的熔点高于互连结构32的焊料322的熔点，使得导电结构34(例如导电结构34的焊料342)并不在互连结构32的回流工艺期间熔化。
如图5D中所展示，在空腔10C中填充模制材料(例如环氧树脂)以在空腔10C形成包封层50，从而包封第二半导体裸片40。举例来说，包封层50至少包封第二半导体裸片40的被动表面40B和侧壁40C。在一些实施例中，包封层50可基本上与衬底10的第二表面102齐平。在一些实施例中，模制材料可进一步形成于衬底10的第二表面102与支撑件70之间，使得包封层50可具有至少部分覆盖衬底10的第二表面102的突出部分50P。在一些实施例中，模制材料能进一步侧向展开，使得突出部分50P可完全覆盖衬底10的第二表面102。在一些实施例中，具有高压的模制材料可推压支撑件70，并在支撑件70与衬底10的第二表面102之间形成突出部分50P，以及在空腔10C中形成包封层50。由于电路层12的接合垫12P1由衬底10覆盖，因此可防止接合垫12P1被模制材料污染。
如图5E中所展示，在形成包封层50之后，从衬底10的第二表面102去除支撑件70。突出部分50P和衬底10随后部分地从第二表面102中去除以形成至少部分暴露电路层12(例如接合垫12P1)的凹部10R，形成如图2D所示的半导体装置封装2D。在一些实施例中，突出部分50P和衬底10可通过激光钻孔部分地去除。在一些其它实施例中，突出部分50P和衬底10可通过机械钻孔、蚀刻或其它合适的工艺部分地去除。
图6是根据本公开的一些实施例的半导体装置封装5的横截面视图。相比于图1中的半导体装置封装1，半导体装置封装5的包封层50可安置在空腔10C中以在不突出空腔10C的情况下包封第二半导体裸片40。在一些实施例中，包封层50可至少完全地包封第二半导体裸片40。举例来说，包封层50可基本上与衬底10的第二表面102齐平。接合垫12P1可从衬底10的第二表面102暴露。在一些实施例中，接合垫12P1可基本上与衬底10的第二表面102齐平。在一些实施例中，电导体14可安置于接合垫12P1上。在一些实施例中，衬底10可通过电导体14进一步接合到封装衬底60。
图7是根据本公开的一些实施例的半导体装置封装6的横截面视图。相比于图6中的半导体装置封装5，接合垫12P1可通过凹部10R从衬底10的第二表面102暴露。
图8A、图8B、图8C、图8D和图8E说明根据本公开的一些实施例的制造半导体装置封装的操作。如图8A中所展示，接收衬底10。衬底10可包含预先形成的电路层12。衬底10限定穿过所述衬底10的至少一个空腔10C。衬底10可进一步包含嵌入电路层12。电路层12可包含邻近衬底10的第二表面102的接合垫12P1和邻近衬底10的第一表面101的接合垫12P2。在一些实施例中，接合垫12P1嵌入衬底10中且未从第二表面102暴露。在一些其它实施例中，接合垫12P1可从衬底10的第二表面102暴露。接合垫12P2可从衬底10的第一表面101暴露。在一些实施例中，支撑件70附接到衬底10的第二表面102以密封空腔10C的底部。在一些实施例中，支撑件70可包含但不限于刚性支撑件。举例来说，刚性支撑件可包含金属膜，例如铜箔。
如图8B中所展示，接收堆叠结构20。堆叠结构20可包含第一半导体裸片30和堆叠于第一半导体裸片40上并电性连接第一半导体裸片40的至少一个第二半导体裸片40。第一半导体裸片30和第二半导体裸片40可通过导电结构34接合。在一些实施例中，底填充物层33可形成于第一半导体裸片30与第一半导体裸片40之间并包围导电结构34。在一些实施例中，例如当导电结构34的焊料342的熔点高于互连结构32的焊料322的熔点时，可省略底填充物层33。第一半导体裸片30和第一半导体裸片40可通过导电结构34通过直接接合(例如共熔接合)进行接合。举例来说，导电凸块341可通过例如电镀在第二半导体裸片40上形成，且焊料342可通过例如电镀在导电凸块341上形成。第一半导体裸片30和第一半导体裸片40可随后通过回流工艺接合。
如图8C中所展示，第一半导体裸片30利用至少部分插入空腔10C中的第二半导体裸片40接合到衬底10的第一表面101。在一些实施例中，第一半导体裸片30通过互连结构32接合到衬底10，并电性连接到从衬底10的第一表面101暴露的接合垫12P2。第一半导体裸片30和衬底10可通过互连结构32通过直接接合(例如共熔接合)进行接合。举例来说，导电凸块321可通过例如电镀在第一半导体裸片30上形成，且焊料322可通过例如电镀在导电凸块321上形成。第一半导体裸片30和衬底10可随后通过回流工艺接合。包围导电结构34的底填充物层33可防止导电结构34(例如导电结构34的焊料342)在互连结构32的回流工艺期间变形。或者或另外，导电结构34的焊料342的熔点高于互连结构32的焊料322的熔点，使得导电结构34(例如导电结构34的焊料342)并不在互连结构32的回流工艺期间熔化。
如图8D中所展示，将模制材料(例如环氧树脂)填充在空腔10C中以在空腔10C中形成包封层50，从而至少完全地包封第二半导体裸片40。举例来说，包封层50至少包封第二半导体裸片40的被动表面40B和侧壁40C。在一些实施例中，包封层50可被支撑件70阻挡且基本上与衬底10的第二表面102齐平。
如图8E中所展示，在形成包封层50之后，从衬底10的第二表面102去除支撑件70。在一些实施例中，在去除支撑件70之后将接合垫12P1嵌入衬底10中，且可对衬底10的第二表面102执行薄化工艺以暴露接合垫12P1，从而形成如图6所示的半导体装置封装5。薄化工艺可包含蚀刻、研磨或其它合适的工艺。在一些其它实施例中，可在去除支撑件70之前从衬底10的第二表面102暴露接合垫12P1，且可省略薄化工艺。在一些实施例中，可在接合垫12P1上形成电导体14。在一些实施例中，衬底10可通过电导体14进一步接合到封装衬底60。在一些其它实施例中，可在去除支撑件70之后对衬底10执行图案化工艺，以形成暴露接合垫12P1的凹部10R。因此，可形成如图7所示的半导体装置封装6。
在本公开的一些实施例中，半导体装置封装包含堆叠结构，所述堆叠结构部分插入衬底的空腔中以使得可减小半导体装置封装的厚度。堆叠结构由包封层包封及保护，且因此可提高半导体装置封装的可靠性。堆叠结构包含彼此堆叠且彼此电性连接的第一半导体裸片30和第二半导体裸片40。第一半导体裸片与第二半导体裸片之间的电性连接可以是其中可省略额外的插入件或互连衬底的无衬底连接，且因此可减少制造成本。因此，可缩短堆叠结构的电传输路径，可进一步减小半导体装置封装的厚度，且可增加I/O连接。
如本文所用，除非上下文另外明确规定，否则单数术语“一(a/an)”和“所述”可包含多个提及物。
如本文中所使用，术语“大约”、“基本上”、“基本”及“约”用以描述及解释小的变化。当与事件或情形结合使用时，所述术语可以指其中事件或情形明确发生的情况以及其中事件或情形极接近于发生的情况。举例来说，当结合数值使用时，术语可指代小于或等于所述数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％(例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％)，那么可认为所述两个数值“基本上”相同或相等。举例来说，“基本上”平行可指代相对于0°的小于或等于±10°的角度变化范围，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°、或小于或等于±0.05°。举例来说，“基本上”垂直可指代相对于90°的小于或等于±10°的角度变化范围，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°、或小于或等于±0.05°。
另外，有时在本文中按范围格式呈现量、比率和它数值。应理解，此范围格式是为了便利和简洁而使用，且应灵活地理解为不仅包含明确地规定为范围极限的数值，而且包含涵盖于所述范围内的所有各个数值或子范围，如同明确地规定各数值和子范围一般。
尽管已参考本公开的特定实施例描述并说明本公开，但这些描述和说明并不限制本公开。所属领域的技术人员应理解，可在不脱离如由所附权利要求书限定的本公开的真实精神和范围的情况下，作出各种改变且取代等效物。图解可能未必按比例绘制。归因于制造过程和公差，本公开中的艺术再现与实际装置之间可能存在区别。可存在并未特定说明的本公开的其它实施例。应将所述说明书和图式视为说明性的，而非限制性的。可做出修改以使特定情况、材料、物质组成、方法或过程适应于本公开的目标、精神以及范围。所有此类修改意图在所附权利要求书的范围内。虽然本文中所公开的方法是参考按特定次序执行的特定操作来描述，但应理解，这些操作可经组合、细分或重新排序以形成等效方法而不脱离本公开的教示内容。因此，除非本文中特别指示，否则操作的次序和分组不是对本公开的限制。

Claims (20)

1.一种半导体装置封装，其包括：
衬底，其包括电路层，所述衬底包含第一表面和与所述第一表面相对的第二表面，其中所述衬底限定穿过所述衬底的至少一个空腔及从所述第二表面凹入并部分暴露所述电路层的至少一个凹部；
堆叠结构，其包括：
第一半导体裸片，其安置于所述第一表面上且电性连接于所述电路层上；
至少一个第二半导体裸片，其堆叠于所述第一半导体裸片上且电性连接到所述第一半导体裸片，其中所述第二半导体裸片至少部分插入所述空腔中；以及
包封层，其安置于所述空腔中且至少包封所述第二半导体裸片，其中所述包封层进一步包括突出所述空腔并部分覆盖所述衬底的所述第二表面的突出部分。
2.根据权利要求1所述的半导体装置封装，其中所述凹部包含靠近所述空腔的第一侧向边缘，且所述包封层的突出部分的第一边缘基本上与所述凹部的所述第一侧向边缘对准。
3.根据权利要求2所述的半导体装置封装，其中所述凹部进一步包含远离所述空腔的第二侧向边缘，且所述突出部分进一步安置于所述凹部的所述第二侧向边缘与所述衬底的周缘之间。
4.根据权利要求3所述的半导体装置封装，其中所述包封层的突出部分的第二边缘基本上与所述凹部的所述第二侧向边缘对准。
5.根据权利要求1所述的半导体装置封装，其中所述包封层的所述突出部分包含非平面表面。
6.根据权利要求1所述的半导体装置封装，其进一步包括多个互连结构，其安置于所述衬底与所述第一半导体裸片之间，并将第一半导体裸片电性连接到所述电路层。
7.根据权利要求6所述的半导体装置封装，其中所述第一半导体裸片的主动表面面向所述第二半导体裸片的主动表面，且所述半导体装置封装进一步包括多个导电结构，所述多个导电结构安置于所述第二半导体裸片的所述主动表面与所述第一半导体裸片的所述主动表面之间并将所述第二半导体裸片电性连接到所述第一半导体裸片。
8.根据权利要求7所述的半导体装置封装，其中所述导电结构的熔点高于所述互连结构的熔点。
9.根据权利要求7所述的半导体装置封装，其进一步包括底填充料层，所述底填充料层安置于所述第二半导体裸片的所述主动表面与所述第一半导体裸片的所述主动表面之间且包围所述导电结构。
10.根据权利要求1所述的半导体装置封装，其中所述第一半导体裸片的主动表面面向所述第二半导体裸片的被动表面，且所述半导体装置封装进一步包括将所述第二半导体裸片电性连接到所述第一半导体裸片的多个接合线。
11.根据权利要求1所述的半导体装置封装，其中所述至少一个第二半导体裸片包括在所述第一半导体裸片上并列安置的多个第二半导体裸片。
12.根据权利要求1所述的半导体装置封装，其中所述至少一个第二半导体裸片包括堆叠在彼此上的多个第二半导体裸片。
13.根据权利要求1所述的半导体装置封装，其中所述电路层包括接合垫，所述合垫穿过所述凹部部分地从所述第二表面暴露，且所述接合垫在竖直突出方向上与所述包封层的所述突出部分部分地重叠。
14.一种半导体装置封装，其包括：
衬底，其包括电路层，所述衬底包含第一表面和与所述第一表面相对的第二表面，其中所述衬底限定穿过所述衬底的至少一个空腔；
堆叠结构，其包括：
第一半导体裸片，其安置于所述第一表面上且电性连接于所述电路层上；
至少一个第二半导体裸片，堆叠于所述第一半导体裸片上且电性连接到所述第一半导体裸片，其中所述第二半导体裸片至少部分地插入所述空腔中；以及
包封层，安置在所述空腔中且至少完全地包封所述第二半导体裸片。
15.根据权利要求14所述的半导体装置封装，其中所述包封层的表面与所述衬底的所述第二表面基本上齐平。
16.根据权利要求14所述的半导体装置封装，其中所述电路层包括从所述第二表面暴露的接合垫，且所述接合垫的表面基本上与所述第二表面齐平/或从所述第二表面凹入。
17.一种制造半导体装置封装的方法，其包括：
接收限定空腔的衬底；
接收堆叠结构，所述堆叠结构包括第一半导体裸片和堆叠于所述第一半导体裸片上的至少一个第二半导体裸片；
利用至少部分插入所述空腔中的所述第二半导体裸片将所述第一半导体裸片接合到所述衬底的第一表面；以及
将模制材料填充于所述空腔中以在所述空腔中形成包封层从而至少完全地包封所述第二半导体裸片。
18.根据权利要求17所述的方法，其进一步包括：
将支撑件附接到所述衬底的第二表面以密封所述空腔的底部；以及
将所述模制材料从所述衬底的所述第一表面填充于所述空腔中以形成所述包封层。
19.根据权利要求18所述的方法，其中所述支撑件包括柔性支撑件，且所述方法进一步包括：
在所述衬底的所述第二表面与所述柔性支撑件之间形成所述模制材料；
在将所述模制材料填充于所述空腔之后从所述衬底的所述第二表面去除所述柔性支撑件；以及
从所述第二表面部分地去除所述模制材料和所述衬底以暴露所述衬底的电路层。
20.根据权利要求18所述的方法，其中所述支撑件包括刚性支撑件，且所述方法进一步包括：
在将所述模制材料填充于所述空腔之后从所述衬底的所述第二表面去除所述刚性支撑件；以及
从所述第二表面薄化所述衬底以暴露所述衬底的电路层。
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