JP6200178B2 - 電子部品内蔵基板及びその製造方法 - Google Patents
電子部品内蔵基板及びその製造方法 Download PDFInfo
- Publication number
- JP6200178B2 JP6200178B2 JP2013068549A JP2013068549A JP6200178B2 JP 6200178 B2 JP6200178 B2 JP 6200178B2 JP 2013068549 A JP2013068549 A JP 2013068549A JP 2013068549 A JP2013068549 A JP 2013068549A JP 6200178 B2 JP6200178 B2 JP 6200178B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- substrate
- electronic component
- layer
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
- H05K2203/1469—Circuit made after mounting or encapsulation of the components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing & Machinery (AREA)
Description
Claims (10)
- 開口部を備えた基板と、
前記基板に形成された第1配線層と、
前記開口部内に配置され、厚みが前記基板の厚みよりも薄い電子部品と、
前記基板の一方の面に形成され、前記電子部品を封止する第1絶縁層と、
前記基板の他方の面に形成された第2絶縁層と、
前記第1絶縁層上に形成された第2配線層と、
前記第2絶縁層上に形成された第3配線層と
を有し、
前記電子部品の一方の面が前記基板の一方の面よりも内部に沈み込んでおり、
前記第1絶縁層は、前記基板の一方の面を被覆して前記開口部内を充填し、前記電子部品の一方の面上の領域に窪み部が設けられた内側絶縁層と、前記内側絶縁層上に形成され、前記窪み部を埋め込んで形成された外側絶縁層とから形成され、
前記基板の前記第2絶縁層側の最外面が半導体チップを搭載する部品搭載面として形成されることを特徴とする電子部品内蔵基板。 - 前記第1配線層は、前記基板の両面にそれぞれ形成されており、
前記第2配線層が、前記内側絶縁層及び外側絶縁層内に形成されたビア導体を介して前記第1配線層に接続されており、
前記第3配線層が、前記第2絶縁層内に形成されたビア導体を介して前記電子部品の接続端子及び前記第1配線層に接続されていることを特徴とする請求項1に記載の電子部品内蔵基板。 - 前記第1絶縁層の厚みは、前記第2絶縁層の厚みと略同一であることを特徴とする請求項1又は2に記載の電子部品内蔵基板。
- 前記開口部の外側周囲領域の前記基板の表面は、前記第1配線層が後退した露出面となっており、前記露出面と前記第2絶縁層との間に、前記内側絶縁層の補強絶縁部が形成されていることを特徴とする請求項1乃至3のいずれか一項に記載の電子部品内蔵基板。
- 前記第2絶縁層は、
前記基板の他方の面と、
前記開口部から前記基板の他方の面側に露出する前記内側絶縁層の面と、
前記内側絶縁層から前記基板の他方の面側に露出する前記電子部品の接続端子と
を被覆して設けられていることを特徴とする請求項1乃至4のいずれか一項に記載の電子部品内蔵基板。 - 第1配線層を備え、一方の面と他方の面とを有する基板を用意し、前記基板に開口部を形成する工程と、
前記開口部内に、厚みが前記基板の厚みよりも薄い電子部品を配置し、前記電子部品の一方の面が前記基板の一方の面よりも内部に沈み込んで配置される工程と、
前記基板の一方の面に前記電子部品を封止する内側絶縁層を形成し、前記電子部品の一方の面上の領域に前記内側絶縁層の窪み部が設けられる工程と、
前記内側絶縁層の上に前記窪み部を埋め込むように外側絶縁層を形成して前記基板の一方の面に前記内側絶縁層及び外側絶縁層から形成される第1絶縁層を得ると共に、前記基板の他方の面に第2絶縁層を形成する工程と、
前記第1絶縁層の上に第2配線層を形成すると共に、前記第2絶縁層の上に第3配線層を形成する工程とを有し、
前記基板の前記第2絶縁層側の最外面が半導体チップを搭載する部品搭載面として形成されることを電子部品内蔵基板の製造方法。 - 前記基板を用意し、開口部を形成する工程において、前記第1配線層は前記基板の両面にそれぞれ形成されており、
前記第2配線層及び第3配線層を形成する工程において
前記第2配線層は、前記第1絶縁層内に形成されたビア導体を介して前記第1配線層に接続され、
前記第3配線層は、前記第2絶縁層内に形成されたビア導体を介して前記電子部品の接続端子及び前記第1配線層に接続されることを特徴とする請求項6に記載の電子部品内蔵基板の製造方法。 - 前記第1絶縁層の厚みと前記第2絶縁層の厚みとが略同一に設定されることを特徴とする請求項6又は7に記載の電子部品内蔵基板の製造方法。
- 前記基板に開口部を形成する工程において、前記開口部の外側周囲領域の前記基板の表面が、前記第1配線層が外側に後退した露出面となるようにし、
前記内側絶縁層を形成する工程において、前記露出面の上に前記内側絶縁層の補強絶縁部が形成されることを特徴とする請求項6乃至8のいずれか一項に記載の電子部品内蔵基板の製造方法。 - 前記開口部内に電子部品を配置する工程の前に、
前記基板の他方の面に仮止めテープを接着して、前記基板の他方の面側の開口部の開口端を閉塞する工程を有し、
前記開口部内に電子部品を配置する工程は、前記開口部内の仮止めテープの上に前記電子部品を配置することを含み、
前記内側絶縁層を形成する工程は、前記内側絶縁層で前記基板の一方の面を被覆すると共に、前記内側絶縁層で前記開口部内を充填することを含み、
前記内側絶縁層を形成する工程の後に、前記仮止めテープを剥離する工程を有し、
前記第1絶縁層を得る工程において、前記内側絶縁層の上に外側絶縁層を積層して前記第1絶縁層が得られ、
前記第2絶縁層を形成する工程において、
前記第2絶縁層は、
前記基板の他方の面と、
前記開口部から前記基板の他方の面側に露出する前記内側絶縁層の面と、
前記内側絶縁層から前記基板の他方の面側に露出する前記電子部品の接続端子と
を被覆して形成されることを特徴とする請求項6乃至9のいずれか一項に記載の電子部品内蔵基板の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013068549A JP6200178B2 (ja) | 2013-03-28 | 2013-03-28 | 電子部品内蔵基板及びその製造方法 |
US14/221,567 US9331011B2 (en) | 2013-03-28 | 2014-03-21 | Electronic component built-in substrate and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013068549A JP6200178B2 (ja) | 2013-03-28 | 2013-03-28 | 電子部品内蔵基板及びその製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2014192452A JP2014192452A (ja) | 2014-10-06 |
JP2014192452A5 JP2014192452A5 (ja) | 2016-01-28 |
JP6200178B2 true JP6200178B2 (ja) | 2017-09-20 |
Family
ID=51620014
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013068549A Active JP6200178B2 (ja) | 2013-03-28 | 2013-03-28 | 電子部品内蔵基板及びその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US9331011B2 (ja) |
JP (1) | JP6200178B2 (ja) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101601815B1 (ko) * | 2014-02-06 | 2016-03-10 | 삼성전기주식회사 | 임베디드 기판, 인쇄회로기판 및 그 제조 방법 |
US10199337B2 (en) | 2015-05-11 | 2019-02-05 | Samsung Electro-Mechanics Co., Ltd. | Electronic component package and method of manufacturing the same |
KR20160132751A (ko) * | 2015-05-11 | 2016-11-21 | 삼성전기주식회사 | 전자부품 패키지 및 그 제조방법 |
US9984979B2 (en) | 2015-05-11 | 2018-05-29 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package and method of manufacturing the same |
US9837484B2 (en) * | 2015-05-27 | 2017-12-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming substrate including embedded component with symmetrical structure |
KR101994752B1 (ko) * | 2016-07-26 | 2019-07-01 | 삼성전기주식회사 | 팬-아웃 반도체 패키지 |
KR101952865B1 (ko) | 2016-10-10 | 2019-02-27 | 삼성전기주식회사 | 팬-아웃 반도체 패키지 및 감광성 수지 조성물 |
KR102004801B1 (ko) | 2016-11-17 | 2019-07-29 | 삼성전기주식회사 | 팬-아웃 반도체 패키지 |
US10700024B2 (en) * | 2017-08-18 | 2020-06-30 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
KR102029535B1 (ko) * | 2017-08-28 | 2019-10-07 | 삼성전기주식회사 | 팬-아웃 반도체 패키지 |
EP3474639B1 (en) * | 2017-10-20 | 2021-07-14 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Embedding a component into a component carrier by transferring the component into a cavity being already filled with filling material |
WO2019111873A1 (ja) | 2017-12-05 | 2019-06-13 | 株式会社村田製作所 | モジュール |
KR102005351B1 (ko) * | 2017-12-07 | 2019-07-31 | 삼성전자주식회사 | 팬-아웃 센서 패키지 |
KR102039711B1 (ko) * | 2018-03-13 | 2019-11-01 | 삼성전자주식회사 | 팬-아웃 부품 패키지 |
US10797017B2 (en) * | 2018-03-20 | 2020-10-06 | Unimicron Technology Corp. | Embedded chip package, manufacturing method thereof, and package-on-package structure |
CN208691627U (zh) * | 2018-08-03 | 2019-04-02 | 奥特斯科技(重庆)有限公司 | 具有嵌入腔中的部件且前侧上具有双介电层的部件承载件 |
US10790162B2 (en) * | 2018-09-27 | 2020-09-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and method |
KR102595864B1 (ko) * | 2018-12-07 | 2023-10-30 | 삼성전자주식회사 | 반도체 패키지 |
US10903169B2 (en) * | 2019-04-30 | 2021-01-26 | Advanced Semiconductor Engineering, Inc. | Conductive structure and wiring structure including the same |
US11145624B2 (en) | 2019-07-26 | 2021-10-12 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method for manufacturing the same |
JP2021082786A (ja) * | 2019-11-22 | 2021-05-27 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3709882B2 (ja) * | 2003-07-22 | 2005-10-26 | 松下電器産業株式会社 | 回路モジュールとその製造方法 |
TWI324901B (en) * | 2007-01-08 | 2010-05-11 | Unimicron Technology Corp | Printed circuit board structure integrating electronic components |
TWI363411B (en) * | 2008-07-22 | 2012-05-01 | Advanced Semiconductor Eng | Embedded chip substrate and fabrication method thereof |
JP2010114434A (ja) * | 2008-10-08 | 2010-05-20 | Ngk Spark Plug Co Ltd | 部品内蔵配線基板及びその製造方法 |
US8299366B2 (en) * | 2009-05-29 | 2012-10-30 | Ibiden Co., Ltd. | Wiring board and method for manufacturing the same |
JP5001395B2 (ja) | 2010-03-31 | 2012-08-15 | イビデン株式会社 | 配線板及び配線板の製造方法 |
US8895380B2 (en) * | 2010-11-22 | 2014-11-25 | Bridge Semiconductor Corporation | Method of making semiconductor assembly with built-in stiffener and semiconductor assembly manufactured thereby |
US9406658B2 (en) * | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
-
2013
- 2013-03-28 JP JP2013068549A patent/JP6200178B2/ja active Active
-
2014
- 2014-03-21 US US14/221,567 patent/US9331011B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20140291859A1 (en) | 2014-10-02 |
JP2014192452A (ja) | 2014-10-06 |
US9331011B2 (en) | 2016-05-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6200178B2 (ja) | 電子部品内蔵基板及びその製造方法 | |
KR102032171B1 (ko) | 전자 부품 내장 기판 및 그 제조 방법 | |
JP2009200389A (ja) | 電子部品内蔵基板の製造方法 | |
JP6208411B2 (ja) | 配線基板及びその製造方法 | |
JP2011159855A (ja) | 局所多層回路基板、および局所多層回路基板の製造方法 | |
JP2016134624A (ja) | 電子素子内蔵型印刷回路基板及びその製造方法 | |
US8161634B2 (en) | Method of fabricating a printed circuit board | |
JP2010157664A (ja) | 電気・電子部品内蔵回路基板とその製造方法 | |
WO2012128269A1 (ja) | 配線基板 | |
US20140076614A1 (en) | Wiring substrate | |
TW201444440A (zh) | 配線基板及其製造方法 | |
TWI477214B (zh) | 具有內埋元件的電路板及其製作方法 | |
TWI552662B (zh) | A manufacturing method of a substrate in which an element is incorporated, and a substrate having a built-in element manufactured by the method | |
JP5593863B2 (ja) | 積層回路基板および基板製造方法 | |
KR101205464B1 (ko) | 인쇄회로기판 제조방법 | |
KR101138542B1 (ko) | 다층 인쇄회로기판의 제조방법 | |
JP5385699B2 (ja) | 積層配線基板の製造方法 | |
JP6266908B2 (ja) | 電子部品内蔵基板の製造方法 | |
JP2010123830A (ja) | プリント配線板とその製造方法 | |
KR100917028B1 (ko) | 아노다이징을 이용한 금속 기판 및 이의 제조방법 | |
KR100888562B1 (ko) | 능동소자 내장형 인쇄회로기판 제조 방법 | |
JP4803918B2 (ja) | 多層配線基板の製造方法 | |
JP4803919B2 (ja) | 多層配線基板の製造方法 | |
JP2007115952A (ja) | インターポーザ基板及びその製造方法 | |
JP6075789B2 (ja) | 配線基板の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20151207 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20151207 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20161027 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20161206 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170117 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20170808 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20170825 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6200178 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |