JP2014192452A - 電子部品内蔵基板及びその製造方法 - Google Patents
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- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L2924/153—Connection portion
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- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
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- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
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- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
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Abstract
【解決手段】開口部2aを備えた基板2と、基板2に形成された配線層22と、開口部2a内に配置された電子部品40と、基板2の一方の面に形成され、電子部品40を封止する第1絶縁層50と、基板2の他方の面に形成された第2絶縁層60と、第1絶縁層50上に形成された配線層23と、第2絶縁層60上に形成された配線層23とを有し、第1絶縁層50は、基板2の一方の面を被覆して開口部2a内を充填する内側絶縁層52と、内側絶縁層52上に形成された外側絶縁層54とから形成されていることを含む。
【選択図】図10
Description
Claims (12)
- 開口部を備えた基板と、
前記基板に形成された第1配線層と、
前記開口部内に配置された電子部品と、
前記基板の一方の面に形成され、前記電子部品を封止する第1絶縁層と、
前記基板の他方の面に形成された第2絶縁層と、
前記第1絶縁層上に形成された第2配線層と、
前記第2絶縁層上に形成された第3配線層と
を有し、
前記第1絶縁層は、前記基板の一方の面を被覆して前記開口部内を充填する内側絶縁層と、前記内側絶縁層上に形成された外側絶縁層とから形成されていることを特徴とする電子部品内蔵基板。 - 前記第1配線層は、前記基板の両面にそれぞれ形成されており、
前記第2配線層が、前記内側絶縁層及び外側絶縁層内に形成されたビア導体を介して前記第1配線層に接続されており、
前記第3配線層が、前記第2絶縁層内に形成されたビア導体を介して前記電子部品の接続端子及び前記第1配線層に接続されていることを特徴とする請求項1に記載の電子部品内蔵基板。 - 前記第1絶縁層の厚みは、前記第2絶縁層の厚みと略同一であることを特徴とする請求項1又は2に記載の電子部品内蔵基板。
- 前記開口部の外側周囲領域の前記基板の表面は、前記第1配線層が後退した露出面となっており、前記露出面と前記第2絶縁層との間に、前記内側絶縁層の補強絶縁部が形成されていることを特徴とする請求項1乃至3のいずれか一項に記載の電子部品内蔵基板。
- 前記開口部に充填された部分の前記内側絶縁層に窪み部が形成されており、前記窪み部を充填して前記内側絶縁層の上に前記外側絶縁層が形成されて、前記第1絶縁層の表面が平坦化されていることを特徴とする請求項1乃至4のいずれか一項に記載の電子部品内蔵基板。
- 前記基板の前記第2絶縁層側の最外面が半導体チップを搭載する部品搭載面として形成されることを特徴とする請求項1乃至5のいずれか一項に記載の電子部品内蔵基板。
- 第1配線層を備えた基板を用意し、前記基板に開口部を形成する工程と、
前記開口部内に電子部品を配置する工程と、
前記基板の一方の面に前記電子部品を封止する内側絶縁層を形成する工程と、
前記内側絶縁層の上に外側絶縁層を形成して前記基板の一方の面に前記内側絶縁層及び外側絶縁層から形成される第1絶縁層を得ると共に、前記基板の他方の面に第2絶縁層を形成する工程と、
前記第1絶縁層の上に第2配線層を形成すると共に、前記第2絶縁層の上に第3配線層を形成する工程とを有することを電子部品内蔵基板の製造方法。 - 前記基板を用意し、開口部を形成する工程において、前記第1配線層は前記基板の両面にそれぞれ形成されており、
前記第2配線層及び第3配線層を形成する工程において
前記第2配線層は、前記第1絶縁層内に形成されたビア導体を介して前記第1配線層に接続され、
前記第3配線層は、前記第2絶縁層内に形成されたビア導体を介して前記電子部品の接続端子及び前記第1配線層に接続されることを特徴とする請求項7に記載の電子部品内蔵基板の製造方法。 - 前記第1絶縁層の厚みと前記第2絶縁層の厚みとが略同一に設定されることを特徴とする請求項7又は8に記載の電子部品内蔵基板の製造方法。
- 前記基板に開口部を形成する工程において、前記開口部の外側周囲領域の前記基板の表面が、前記第1配線層が外側に後退した露出面となるようにし、
前記内側絶縁層を形成する工程において、前記露出面の上に前記内側絶縁層の補強絶縁部が形成されることを特徴とする請求項7乃至9のいずれか一項に記載の電子部品内蔵基板の製造方法。 - 前記内側絶縁層を形成する工程において、前記開口部に充填された部分の前記内側絶縁層に窪み部が形成され、
前記外側絶縁層を形成する工程において、前記窪み部を充填して前記内側絶縁層の上に前記外側絶縁層が形成されて、前記第1絶縁層の表面が平坦化されることを特徴とする請求項7乃至10のいずれか一項に記載の電子部品内蔵基板の製造方法。 - 前記基板の前記第2絶縁層側の最外面が半導体チップを搭載する部品搭載面として形成されることを特徴とする請求項7乃至11のいずれか一項に記載の電子部品内蔵基板の製造方法。
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CN208691627U (zh) * | 2018-08-03 | 2019-04-02 | 奥特斯科技(重庆)有限公司 | 具有嵌入腔中的部件且前侧上具有双介电层的部件承载件 |
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