CN110957281A - 集成电路封装件和方法 - Google Patents

集成电路封装件和方法 Download PDF

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Publication number
CN110957281A
CN110957281A CN201910305554.5A CN201910305554A CN110957281A CN 110957281 A CN110957281 A CN 110957281A CN 201910305554 A CN201910305554 A CN 201910305554A CN 110957281 A CN110957281 A CN 110957281A
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redistribution structure
conductive
substrate
integrated circuit
package
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CN110957281B (zh
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蔡柏豪
翁得期
周孟纬
林孟良
庄博尧
郑心圃
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

在一个实施例中，一种封装件包括：第一再分布结构；第一集成电路管芯，连接到第一再分布结构；环形衬底，环绕第一集成电路管芯，环形衬底连接到第一再分布结构，环形衬底包括芯和延伸穿过芯的导电通孔；围绕环形衬底和第一集成电路管芯的密封剂，密封剂延伸穿过环形衬底；在密封剂上的第二再分布结构，第二再分布结构通过环形衬底的导电通孔连接到第一再分布结构。本发明实施例涉及集成电路封装件和方法。

Description

集成电路封装件和方法
技术领域
本发明实施例涉及集成电路封装件和方法。
背景技术
由于各种电子元件(例如，晶体管，二极管，电阻器，电容器等)的集成密度的不断提高，半导体工业经历了快速增长。在大多数情况下，集成密度的提高是由于最小部件尺寸的不断减小所致，这允许将更多组件集成到给定区域中。随着对缩小电子器件的需求的增长，出现了对更小和更有创造性的半导体管芯的封装技术的需求。这种封装系统的一个实例是叠层封装(PoP)技术。在PoP器件中，顶部半导体封装件堆叠在底部半导体封装件的顶部，以提供高水平的集成度和元件密度。PoP技术通常能够在印刷电路板(PCB)上生产具有增强功能和小占用面积的半导体器件。
发明内容
根据本发明的一些实施例，提供了一种封装件，包括：第一再分布结构；第一集成电路管芯，连接至所述第一再分布结构；环形衬底，围绕所述第一集成电路管芯，所述环形衬底连接至所述第一再分布结构，所述环形衬底包括芯和延伸穿过所述芯的导电通孔；密封剂，围绕所述环形衬底和所述第一集成电路管芯，所述密封剂延伸穿过所述环形衬底；以及第二再分布结构，位于所述密封剂上，所述第二再分布结构通过所述环形衬底的导电通孔连接至所述第一再分布结构。
根据本发明的另一些实施例，还提供了一种形成封装件的方法，包括：在衬底中图案化第一开口；在所述第一开口中形成导电通孔；形成连接至所述导电通孔的第一导电连接器，所述第一导电连接器位于所述衬底的第一侧上；在所述衬底中图案化腔；将所述衬底放置在所述第一再分布结构上，所述第一导电连接器耦合到所述第一再分布结构；将所述集成电路管芯放置在所述第一再分布结构上和所述衬底的腔中，所述集成电路管芯包括耦合到所述第一再分布结构的第二导电连接器；用密封剂封装所述集成电路管芯和所述衬底；和在所述密封剂上形成第二再分布结构，所述第二再分布结构通过所述衬底的导电通孔连接至所述第一再分布结构。
根据本发明的又一些实施例，还提供了一种形成封装件的方法，包括：将环形衬底连接至第一再分布结构，所述环形衬底包括：具有腔的芯；第一导电通孔，延伸穿过所述芯；和导线，位于所述芯上，所述导线连接至所述第一导电通孔；将第一集成电路管芯连接至所述第一再分布结构，所述第一集成电路管芯设置在所述环形衬底的腔中；用密封剂将所述环形衬底和所述第一集成电路管芯封装在一起；和在所述密封剂上形成第二再分布结构，所述第二再分布结构通过所述第一导电通孔和所述环形衬底的导线连接至所述第一再分布结构。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图7B是根据一些实施例的用于形成环形衬底的工艺的中间步骤的截面图。
图8至图17是根据一些实施例的用于将环形衬底与其他器件封装以形成封装组件的工艺的中间步骤的截面图。
图18是根据一些实施例的封装结构的截面图。
图19是根据一些其他实施例的封装结构的截面图。
图20是根据一些其他实施例的封装结构的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。
此外，使用空间相对术语，例如，“下面”，下方”，“下部”，“之上”，“上部”等以便于描述本公开的一个部件与另一个部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
根据一些实施例，形成或提供环形衬底。环形衬底包括具有导线和通孔的衬底芯。环形衬底中的腔可以容纳半导体器件，诸如集成电路管芯。然后可以将环形衬底封装，其中封装件包括设置在腔中的集成电路管芯。该封装件用例如模塑料封装。因为环形衬底是刚性的，所以在形成封装件时它提供机械支撑。通过避免密封剂与封装件的其他组件之间的热膨胀系数(CTE)不匹配，可以减小翘曲并且可以降低封装件的整体堆叠高度。
图1至图7B是根据一些实施例的用于形成环形衬底100的工艺的中间步骤的截面图。尽管示出了一个环形衬底100的形成，但是应当理解，可以使用相同的晶圆或衬底同时形成多个环形衬底100，并且可以随后将其分割以形成单独的环形衬底100。
在图1中，提供了在相对侧上具有晶种层104的衬底芯102。衬底芯102可以由预浸渍的复合纤维(“预浸料”)，绝缘膜或构建膜，纸，玻璃纤维，非织造玻璃纤维，硅等形成。衬底芯102由有助于实现与硅的CTE匹配的材料形成。在一些实施例中，衬底芯102由包括玻璃纤维和树脂的预浸料形成。晶种层104可以是一层或多层铜，钛，镍，铝，其组合物等，并且沉积或层压到衬底芯102的相对侧上。在一些实施例中，衬底芯102和晶种层104是覆铜环氧树脂浸渍的玻璃布层压板，覆铜聚酰亚胺浸渍的玻璃布层压板等。
在图2中，开口106形成在衬底芯102和晶种层104中。在一些实施例中，开口106通过激光钻孔形成。其他工艺，诸如使用钻头的机械钻孔，也可用于形成开口106。开口106可具有任何顶视图形状，诸如多边形，圆形等。然后可以执行清洁工艺以清洁开口106附近的区域，该区域可能已经被衬底芯102的去除材料弄脏。清洁工艺可以是去污工艺。去污可以通过机械方法(例如，用湿浆料中的细磨料喷砂)，化学方法(例如，用有机溶剂，高锰酸盐等的组合进行冲洗)，或通过机械和化学方法的组合来完成。
在图3中，导电通孔108形成在开口106中，并且导线110形成在衬底芯102的相对侧上。导电通孔108和导线110可以由诸如铜，钛，钨，铝等的导电材料形成。导电通孔108和导线110可以由相同材料或不同材料形成，并且可以通过相同工艺或不同工艺形成。在一些实施例中，导电通孔108利用第一工艺形成，并且导线110利用第二工艺形成。例如，可以使用诸如化学镀的第一镀工艺在开口106中沉积导电材料，从而形成导电通孔108。在使用化学镀的实施例中，可以在开口106中形成晶种层。可以使用晶种层104执行第二镀工艺，诸如电镀，化学镀等。在晶种层104上形成并图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以曝光以进行图案化。光刻胶的图案对应于导线110。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。导电材料可以通过镀形成，诸如电镀或化学镀等。去除光刻胶和晶种层104的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等。一旦去除光刻胶，就去除晶种层104的暴露部分，诸如通过使用可接受的蚀刻工艺，诸如通过湿法或干法蚀刻。晶种层104的剩余部分和导电材料形成导线110。
在图4中，阻焊层112形成在衬底芯102的相对侧上，并且形成在导线110上。阻焊层112保护衬底芯102的区域免受外部损坏。在一些实施例中，通过沉积光敏介电层，用光学图案曝光光敏材料，以及显影曝光的层以形成开口114来形成阻焊层112。在一些实施例中，通过沉积非光敏介电层(例如，氧化硅或氮化硅等)，并用可接受的光刻和蚀刻技术图案化介电层以形成开口114来形成阻焊层112。开口114暴露下面的导线110的部分，该导线110的部分可以在后续工艺中用作连接器焊盘。
在图5中，保护层116可选地形成在导线110的暴露部分上的开口114中。保护层116可各自为单层或包括多个层的复合层。保护层116可以由诸如镍，锡，锡-铅，金，银，钯，铟，镍-钯-金，镍-金等的金属或其组合形成。在一些实施例中，保护层116可以是化学镀镍浸金(ENIG)，其包括在导线110的暴露部分上的金层和在金层上的镍层。在一些实施例中，保护层116可以是化学镀镍化学镀钯浸金(ENEPIG)，其包括位于导线110的暴露部分上的金层，金层上的钯层和钯层上的镍层。保护层116可以通过电镀，化学镀，浸渍，物理气相沉积(PVD)或其组合形成。保护层116的硬度可以大于下面的导线110的硬度。
在图6中，导电连接器118形成在开口114中。在使用保护层116的实施例中，导电连接器118接触保护层116。在省略保护层116的实施例中，导电连接器118接触导线110的暴露部分。导电连接器118可以是球栅阵列(BGA)连接器，焊球，金属柱，可控塌陷芯片连接(C4)凸块，微凸块，化学镀镍-化学镀钯-浸金技术(ENEPIG)形成的凸块等。导电连接器118可以包括导电材料，诸如焊料，铜，铝，金，镍，银，钯，锡等，或它们的组合。在一些实施例中，导电连接器118是焊料连接器，其通过通过诸如蒸发，电镀，印刷，焊料转移，球放置等的常用方法首先形成焊料层来形成。一旦在结构上形成了一层焊料，就可以进行回流以将材料成形为所需的凸块形状。在另一实施例中，导电连接器118包括通过溅射，印刷，电镀，化学镀，化学气相沉积(CVD)等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本上垂直的侧壁。
在图7A中，通过去除部分衬底芯102和阻焊层112来形成腔120。可以通过具有计算机数字控制(CNC)的机械钻孔工艺来完成材料的去除以形成腔120。在这样的实施例中，通过机械钻孔去除材料，钻孔的位置由计算机或控制器控制。去除也可以通过其他工艺完成，诸如激光切割工艺，激光钻孔工艺等。材料的剩余部分形成环形衬底100。
图7B是图7A的环形衬底100的俯视图。可以看出，环形衬底100在俯视图中具有环形形状。腔120延伸穿过环形衬底100的中心部分以形成环。图7B中的示例性环形衬底100是矩形的。应当理解，其他实施例可以具有其他形状。例如，其他环形衬底100可以是圆形，三角形等。
图8至图17是根据一些实施例的用于将环形衬底100与其他器件封装以形成封装组件200的工艺的中间步骤的截面图。封装组件200包括多个区域，并且在每个区域中封装一个环形衬底100。示出了封装组件200的一个区域。
在图8中，提供载体衬底202，并且在载体衬底202上形成释放层204。载体衬底202可以是玻璃载体衬底，陶瓷载体衬底等。载体衬底202可以是晶圆，从而使得可以在载体衬底202上形成多个封装件。释放层204可以由基于聚合物的材料形成，其可以与载体衬底202一起从将在后续步骤中形成的上面的结构去除。在一些实施例中，释放层204是基于环氧树脂的热释放材料，其在加热时失去其粘合性，诸如光-热-转换(LTHC)释放涂层。在其他实施例中，释放层204可以是当暴露于UV光时其失去其粘合性的紫外(UV)胶。释放层204可以作为液体分配并固化，可以是层压到载体衬底202上的层压膜，或者可以是类似物。释放层204的顶面可以是水平的并且可以具有高度的共面性。
在图9中，在释放层204上形成第一再分布结构206。第一再分布结构206包括介电层208，212，216和220；金属化图案210，214和218；和凸块下金属(UBM)222。金属化图案210，214和218也可以称为再分布层或再分布线。第一再分布结构206被示出为示例。可以在第一再分布结构206中形成更多或更少的介电层和金属化图案。如果要形成更少的介电层和金属化图案，则可以省略下面讨论的步骤和工艺。如果要形成更多的介电层和金属化图案，则可以重复下面讨论的步骤和工艺。
作为形成第一再分布结构206的示例，介电层208沉积在释放层204上。在一些实施例中，介电层208由光敏材料形成，诸如聚苯并恶唑(PBO)，聚酰亚胺，苯并环丁烯(BCB)等，其可以使用光刻掩模图案化。可以通过旋涂，层压，CVD等或其组合来形成介电层208。然后图案化介电层208。图案化形成暴露释放层204的部分的开口。图案化可以通过可接受的工艺，诸如在介电层208是光敏材料时通过将介电层208暴露于光或者通过使用例如各向异性蚀刻来蚀刻。如果介电层208是光敏材料，则可以在曝光之后显影介电层208。
然后形成金属化图案210。金属化图案210包括在介电层208的主表面上并沿着介电层208的主表面延伸的导线。金属化图案210还包括延伸穿过介电层208的导电通孔。为了形成金属化图案210，在介电层208上方并且在延伸穿过介电层208的开口中形成晶种层。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和钛层上方的铜层。可以使用例如PVD等形成晶种层。然后在晶种层上形成并图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以进行图案化。光刻胶的图案对应于金属化图案210。图案化形成穿过光刻胶的开口以暴露晶种层。然后在光刻胶的开口中和晶种层的暴露部分上形成导电材料。导电材料可以通过镀形成，诸如电镀或化学镀等。导电材料可包括金属，如铜，钛，钨，铝等。导电材料和下面的晶种层的部分的组合形成金属化图案210。去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等。一旦去除光刻胶，就去除晶种层的暴露部分，诸如通过使用可接受的蚀刻工艺，诸如通过湿法或干法蚀刻。
介电层212沉积在金属化图案210和介电层208上。介电层212可以以与介电层208类似的方式形成，并且可以由与介电层208相同的材料形成。
然后形成金属化图案214。金属化图案214包括在介电层212的主表面上并沿着介电层212的主表面延伸的导线。金属化图案214还包括延伸穿过介电层212的导电通孔，以物理和电连接至金属化图案210。金属化图案214可以以与金属化图案210类似的方式，并且可以由与金属化图案210相同的材料形成。金属化图案214的导电通孔的宽度小于金属化图案210的导电通孔的宽度。从而，当图案化用于金属化图案214的介电层212时，介电层212中的开口的宽度小于介电层208中的开口的宽度。
介电层216沉积在金属化图案214和介电层212上。介电层216可以以与介电层208类似的方式形成，并且可以由与介电层208相同的材料形成。
然后形成金属化图案218。金属化图案218包括在介电层216的主表面上并沿着介电层216的主表面延伸的导线。金属化图案218还包括延伸穿过介电层216的导电通孔，以物理和电连接至金属化图案214。金属化图案218可以以与金属化图案210类似的方式形成，并且，可以由与金属化图案210相同的材料形成。金属化图案218的导电通孔的宽度小于金属化图案210的导电通孔的宽度。从而，当图案化用于金属化图案214的介电层216时，介电层216中的开口的宽度小于介电层208中的开口的宽度。
介电层220沉积在金属化图案218和介电层216上。介电层220可以以与介电层208类似的方式形成，并且可以由与介电层208相同的材料形成。
UBM222形成在介电层220上并且延伸穿过介电层220。作为形成UBM222的示例，介电层220可以被图案化以形成暴露金属化图案218的部分的开口。图案化可以通过可接受的工艺，诸如通过在介电层220是光敏材料时将介电层220暴露于光或者通过使用例如各向异性蚀刻进行蚀刻。如果介电层220是光敏材料，则可以在曝光之后可以显影介电层220。用于UBM222的开口可以比用于金属化图案210，214和218的导电通孔部分的开口宽。在介电层220上和开口中形成晶种层。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和钛层上方的铜层。可以使用例如PVD等形成晶种层。然后在晶种层上形成并图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以进行图案化。光刻胶的图案对应于UBM222。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。导电材料可以通过镀形成，诸如电镀或化学镀等。导电材料可包括金属，如铜，钛，钨，铝等。然后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等。一旦去除光刻胶，就诸如通过使用可接受的蚀刻工艺去除晶种层的暴露部分，诸如通过湿法或干法蚀刻。晶种层的剩余部分和导电材料形成UBM222。在UBM222不同地形成的实施例中，可以使用更多的光刻胶和图案化步骤。
UBM222可能不都具有相同的宽度。在一些实施例中，第一再分布结构206的第一区域206A中的UBM222的第一子集具有第一宽度W1，并且第一再分布结构206的第二区域206B中的UBM222的第二子集具有第二宽度W2。第一宽度W1可以与第二宽度W2不同，并且在一些实施例中，第一宽度W1大于第二宽度W2。
在图10中，环形衬底100放置在第一再分布结构206上方。环形衬底100可以使用例如拾取和放置工具对准和放置。环形衬底100的导电连接器118与第一区域206A中的UBM222对准，并且环形衬底100的腔120在第二区域206B中的UBM222上方对准。在导电连接器118是焊料的实施例中，导电连接器118可以不立即回流以将环形衬底100接合到UBM222。可以延迟导电连接器118的回流直到后续处理步骤。在导电连接器118是铜柱的实施例中，可以形成焊料，将导电连接器118接合到第一再分布结构206。
在图11中，集成电路管芯224放置在第一再分布结构206上方。集成电路管芯224可以是逻辑管芯(例如，中央处理单元，微控制器等)，存储器管芯(例如，动态随机存取存储器(DRAM)管芯，静态随机存取存储器(SRAM)管芯等)，电源管理管芯(例如，电源管理集成电路(PMIC)管芯)，射频(RF)管芯，传感器管芯，微电子-机械系统(MEMS)管芯，信号处理管芯(例如，数字信号处理(DSP)管芯)，前端管芯(例如，模拟前端(AFE)管芯)等，或其组合(例如，片上系统(SoC))。
集成电路管芯224包括半导体衬底，其中诸如晶体管，二极管，电容器，电阻器等的器件形成在半导体衬底中和/或上。器件可以通过互连结构互连以形成集成电路，该互连结构由例如半导体衬底上的一个或多个介电层中的金属化图案形成。集成电路管芯224还包括焊盘226，诸如铝焊盘，外部连接件连接至焊盘226。焊盘226位于可以被称为集成电路管芯224的相应有源侧的位置上，并且可以位于互连结构的最上层中。因为集成电路管芯224的有源侧面向第一再分布结构206，所以第一再分布结构206也可以被称为“前侧再分布结构”。导电连接器228可以形成在焊盘226上。导电连接器228可以由导电材料形成，诸如焊料，铜，铝，金，镍，银，钯，锡等，或它们的组合。在一些实施例中，导电连接器228是焊料连接器。
可以使用例如拾取和放置工具对准和放置集成电路管芯224。集成电路管芯224放置在腔120内，使得导电连接器228与第二区域206B中的UBM222对准。在放置集成电路管芯224之后，导电连接器228被回流以在相应的UBM222和焊盘226之间形成接头，从而将集成电路管芯224物理地和电气地连接至第一再分布结构206。在环形衬底100的导电连接器118是焊料并且回流延迟的实施例中，导电连接器118和228可以在相同的回流工艺中同时回流。这样，导电连接器118也可以回流以在相应的UBM222和导线110之间形成接头，从而将环形衬底100物理地和电气地连接至第一再分布结构206。换句话说，集成电路管芯224和环形衬底100可以同时接合到第一再分布结构206。导电连接器118和228可以是不同的尺寸。在一些实施例中，环形衬底100的高度H1小于或等于集成电路管芯224的高度H2。高度H1也可以大于高度H2。此外，集成电路管芯224的宽度小于腔120的宽度。
应当理解，集成电路管芯224和环形衬底100可以以任何顺序放置在第一再分布结构206上方。在一些实施例中，首先放置集成电路管芯224，并且将环形衬底100放置在集成电路管芯224周围。
在图12中，底部填充物230可以形成在集成电路管芯224和第一再分布结构206之间，围绕导电连接器228。这样，可以保护导电连接器228免受机械力的影响。底部填充物230可以在集成电路管芯224附接之后通过毛细管流动工艺形成，或者可以在附接集成电路管芯224之前通过合适的沉积方法形成。
在图13中，密封剂232形成在各种组件上。密封剂232可以是模塑料，环氧树脂等，并且可以通过压缩模塑，传递模塑等施加。密封剂232可以形成在第一再分布结构206上方，使得集成电路管芯224和环形衬底100被掩埋或覆盖，并且腔120被填充。掩埋环形衬底100的密封剂232的部分具有厚度T1。在一些实施例中，厚度T1在约10μm至约100μm的范围内。然后使密封剂232固化，并且可以任选地通过例如研磨或化学机械抛光(CMP)工艺平坦化。在形成之后，密封剂232具有高度H3，其大于高度H1和H2。密封剂232也形成在第一再分布结构206和集成电路管芯224之间，例如，在省略底部填充物230的实施例中。
环形衬底100占据封装组件200的垂直高度的重要部分，因此可以减少覆盖集成电路管芯224所需的密封剂232的量。例如，高度H3与高度H1的比率可以从大约1：0.14到大约1：0.60的范围内。因此可以增加封装组件200的总高度，而不会显著增加所使用的密封剂232的量。减少所使用的密封剂232的量可以帮助避免由密封剂232和封装组件200的其他组件之间的CTE不匹配引起的封装翘曲。
在图14中，在密封剂232中形成开口234，从而暴露环形衬底100的保护层116。开口234可以通过诸如激光钻孔，机械钻孔等的钻孔工艺形成。开口234可以具有锥形轮廓，具有上部宽度W3，以及下部宽度W4，其小于或等于上部宽度W3。在一些实施例中，上部宽度W3在约50μm至约350μm的范围内，下部宽度W4在约50μm至约200μm的范围内。
在图15中，在开口234中形成导电连接器236。导电连接器236可以由诸如焊料，铜，铝，金，镍，银，钯，锡等的金属或其组合形成。在一些实施例中，导电连接器236由诸如铜膏、焊膏、银膏等的膏形成，并且通过印刷工艺等分配。在使用印刷工艺的实施例中，使用模版将具有所需图案的导电连接器236的图像印刷在密封剂232上和开口234中。在形成之后，固化导电膏以使其硬化，从而形成导电连接器236。导电膏可以通过在约80℃至约230℃的温度下进行的退火工艺来固化，并且持续约20分钟到大约4小时的时间。在导电连接器236是膏的实施例中，导电连接器236可以过填充开口，使得它们具有延伸穿过密封剂232的通孔部分，以及沿着密封剂232的顶面延伸的上部。
在图16中，在导电连接器236和密封剂232上方形成第二再分布结构238。由于集成电路管芯224的有源侧背向第二再分布结构238，第二再分布结构238也可以称为“背侧再分布结构”。第二再分布结构238包括介电层240，244，248和252；金属化图案242，246和250；和UBM254。金属化图案也可以称为再分布层或再分布线。第二再分布结构238被示出为示例。可以在第二再分布结构238中形成更多或更少的介电层和金属化图案。如果要形成更少的介电层和金属化图案，则可以省略下面讨论的步骤和工艺。如果要形成更多的介电层和金属化图案，则可以重复下面讨论的步骤和工艺。
作为形成第二再分布结构238的示例，介电层240沉积在导电连接器236和密封剂232上。在一些实施例中，介电层240由诸如PBO、聚酰亚胺、BCB等的光敏材料形成，可以使用光刻掩模图案化。可以通过旋涂，层压，CVD等或其组合来形成介电层240。然后图案化介电层240。图案化形成暴露导电连接器236的部分的开口。图案化可以通过可接受的工艺，诸如通过当介电层240是光敏材料时将介电层240暴露于光或者通过使用例如各向异性蚀刻来蚀刻。如果介电层240是光敏材料，则可以在曝光之后显影介电层240。
在导电连接器236过填充开口的实施例中，介电层240可以用作平坦化复位层。值得注意的是，介电层240可以形成为比再分布结构的底部介电层的通常厚度更大的厚度，以允许平坦化。在形成之后，介电层240可以具有在约5μm至约15μm范围内的厚度T2。在一些实施例中，执行形成后平坦化工艺。平坦化工艺可以包括在电介质240上执行研磨工艺或CMP工艺。通过使用介电层240作为平坦化复位层，介电层240的顶面可以基本上是平面的，并且可以具有比介电层240的底面更高的平面度。在平坦化之后，可以减小介电层240的厚度。介电层240(例如，底部介电层)的厚度比第二再分布结构238的其他介电层厚，诸如介电层252(例如，顶部介电层)。
然后形成金属化图案242。金属化图案242包括在介电层240的主表面上并沿着介电层240的主表面延伸的导线。金属化图案242还包括延伸穿过介电层240的导电通孔，以物理地和电气地连接至导电连接器236。为了形成金属化图案242，在介电层240上方和延伸穿过介电层240的开口中形成晶种层。在一些实施例中，晶种层是金属层，其可以是单层或包括多个由不同材料形成的子层的复合层。在一些实施例中，晶种层包括钛层和钛层上方的铜层。可以使用例如PVD等形成晶种层。然后在晶种层上形成并图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以进行图案化。光刻胶的图案对应于金属化图案242。图案化形成穿过光刻胶的开口以暴露晶种层。然后在光刻胶的开口中和晶种层的暴露部分上形成导电材料。导电材料可以通过镀形成，例如电镀或化学镀等。导电材料可包括金属，如铜，钛，钨，铝等。导电材料和下面的晶种层的部分的组合形成金属化图案242。去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等。一旦去除光刻胶，就去除晶种层的暴露部分，诸如通过使用可接受的蚀刻工艺，诸如通过湿法或干法蚀刻。
介电层244沉积在金属化图案242和介电层240上。介电层244可以以与介电层240类似的方式形成，并且可以由与介电层240相同的材料形成。
然后形成金属化图案246。金属化图案246包括在介电层244的主表面上并沿着介电层244的主表面延伸的导线。金属化图案246还包括延伸穿过介电层244的导电通孔，以物理和电连接至金属化图案242。金属化图案246可以以与金属化图案242类似的方式形成，并且可以由与金属化图案242相同的材料形成。
介电层248沉积在金属化图案246和介电层244上。介电层248可以以与介电层240类似的方式形成，并且可以由与介电层240相同的材料形成。
然后形成金属化图案250。金属化图案250包括在介电层248的主表面上并沿介电层248的主表面延伸的导线。金属化图案250还包括延伸穿过介电层248的导电通孔，以物理和电连接至金属化图案246。金属化图案250可以以与金属化图案242类似的方式形成栅极，并且可以由与金属化图案242相同的材料形成。
介电层252沉积在金属化图案250和介电层248上。介电层252可以以与介电层240类似的方式形成，并且可以由与介电层240相同的材料形成。
UBM254形成在介电层252上并且延伸穿过介电层252。作为形成UBM254的示例，介电层252可以被图案化以形成暴露金属化图案250的部分的开口。图案化可以通过可接受的工艺，诸如通过当介电层252是光敏材料时将介电层252暴露于光或者通过使用例如各向异性蚀刻进行蚀刻。如果介电层252是光敏材料，则可以在曝光之后显影介电层252。用于UBM254的开口可以比用于金属化图案242，246和250的导电通孔部分的开口宽。在介电层252上方和在开口中形成晶种层。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和钛层上的铜层。可以使用例如PVD等形成晶种层。然后在晶种层上形成并图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以进行图案化。光刻胶的图案对应于UBM254。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。导电材料可以通过镀形成，诸如电镀或化学镀等。导电材料可包括金属，如铜，钛，钨，铝等。然后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等。一旦去除光刻胶，就去除晶种层的暴露部分，诸如通过使用可接受的蚀刻工艺，诸如通过湿法或干法蚀刻。晶种层和导电材料的剩余部分形成UBM254。在不同地形成UBM254的实施例中，可以使用更多的光刻胶和图案化步骤。
在形成之后，环形衬底100电连接封装组件200的各种部件。具体地，环形衬底100，导电连接器118和导电连接器236将第一再分布结构206电连接和物理连接至第二再分布结构238。因此，集成电路管芯224通过第一再分布结构206和环形衬底100电连接至第二再分布结构238。
在图17中，执行载体衬底去接合以将载体衬底202从第一再分布结构206(例如，介电层208)分离(或“去接合”)。在一些实施例中，去接合包括在释放层204上投射诸如激光或UV光的光，使得释放层204在光的热量下分解，并且可以去除载体衬底202。然后将结构翻转并放在胶带上。去接合暴露第一再分布结构206的金属化图案210。
图18是根据一些实施例的封装结构300的截面图。封装结构300包括第一封装件302，集成电路管芯304和封装衬底306。封装结构300可以被称为并排多芯片模块(SBS-MCM)。
第一封装件302是形成在封装组件200中的封装件之一。通过沿着划线区域(例如，在封装组件200的相邻封装区域之间)锯切对封装组件200执行分离工艺。得到的分离的第一封装件302来自分离的封装区域之一。
集成电路管芯304可以是与集成电路管芯224通信以形成完整系统的管芯。例如，在集成电路管芯224是逻辑管芯的实施例中，集成电路管芯304可以是存储器管芯，RF管芯，无源器件或其组合。集成电路管芯304包括半导体衬底，在半导体衬底中和/或上形成有诸如晶体管，二极管，电容器，电阻器等的器件。器件可以通过互连结构互连以形成集成电路，该互连结构由例如半导体衬底上的一个或多个介电层中的金属化图案形成。集成电路管芯304还包括焊盘308，诸如铝焊盘，外部连接形成在焊盘308上。焊盘308位于可以被称为集成电路管芯304的相应有源侧的位置上，并且可以位于互连结构的最上层中。导电连接器310可以形成在焊盘308上。导电连接器310可以由导电材料形成，诸如焊料，铜，铝，金，镍，银，钯，锡等，或它们的组合。使用导电连接器310将集成电路管芯304安装到UBM254。在一些实施例中，导电连接器310被回流以将集成电路管芯304附接到UBM254。在一些实施例中，形成底部填充物或密封剂以填充集成电路管芯304和第二再分布结构238之间的间隙。因为减少了使用的密封剂232的量，所以可以减小第一封装件302的厚度，这可以允许附接更大厚度的集成电路管芯304。例如，当集成电路管芯304是存储器件时，可以增加存储器件的容量。
然后使用导电连接器312将第一封装件302安装到封装衬底306。封装衬底306可以由诸如硅，锗，金刚石等的半导体材料制成。或者，也可以使用诸如硅锗，碳化硅，砷化镓，砷化铟，磷化铟，碳化硅锗，磷化镓砷，磷化镓铟等，它们的组合等的化合物材料。另外，封装衬底306可以是绝缘体上硅(SOI)衬底。通常，SOI衬底包括半导体材料层，诸如外延硅，锗，硅锗，SOI，绝缘体上硅-锗(SGOI)或其组合。在一个替代实施例中，封装衬底306基于绝缘芯，例如玻璃纤维增强树脂芯。一种示例性芯材料是玻璃纤维树脂，诸如FR4。芯材料的替代物包括双马来酰亚胺-三嗪(BT)树脂，或者可选地，其他PCB材料或膜。诸如味之素构建膜(ABF)或其他层压板的构建膜可用于封装衬底306。
封装衬底306可以包括有源和无源器件(未示出)。如本领域普通技术人员将认识到的，可以使用诸如晶体管，电容器，电阻器，这些的组合等各种各样的器件来产生封装结构300的设计的结构和功能要求。可以使用任何合适的方法形成器件。
封装衬底306还可以包括金属化层和通孔(未示出)以及位于金属化层和通孔上方的接合焊盘314。金属化层可以形成在有源和无源器件上方，并设计成连接各种器件以形成功能电路。金属化层可以由交替的介电层(例如，低k介电材料)和导电材料(例如，铜)形成，其中通孔互连导电材料层并且可以通过任何合适的工艺(诸如沉积，镶嵌，双镶嵌等)形成。在一些实施例中，封装衬底306基本上没有有源和无源器件。
导电连接器312可以由导电材料形成，诸如焊料，铜，铝，金，镍，银，钯，锡等，或它们的组合。在一些实施例中，导电连接器312被回流以将第一封装件302附接到接合焊盘314。导电连接器312将封装衬底306(包括封装衬底306中的金属化层)电连接和/或物理连接至第一封装件302的金属化图案210。在一些实施例中，无源器件(例如，表面安装器件(SMD)，未示出)可以在安装到封装衬底306上之前附接到第一封装件302(例如，接合到接合焊盘314)。在这样的实施例中，无源器件可以与导电连接器312接合到第一封装件302的相同表面。
导电连接器312可在其回流之前具有形成于其上的环氧树脂焊剂(未示出)，其中在第一封装件302附接到封装衬底306之后环氧树脂焊剂的至少一些环氧树脂部分仍然保留。保留的环氧树脂部分可以用作底部填充物以减少应力并保护由导电连接器312回流所产生的接头。在一些实施例中，底部填充物(未示出)可以形成在第一封装件302和封装衬底306之间并围绕导电连接器312。底部填充物可以在附接第一封装件302之后通过毛细管流动工艺形成，或者可以在附接第一封装件302之前通过合适的沉积方法形成。
图19是根据一些其他实施例的封装结构300的截面图。在所示的实施例中，底部填充物230也形成为围绕导电连接器118的子集。这样，可以保护一些导电连接器118免受机械力的影响。
图20是根据一些其他实施例的封装结构300的截面图。在所示的实施例中，底部填充物230也形成为包围所有导电连接器118。这样，可以保护所有的导电连接器118免受机械力。
实施例可以实现优点。环形衬底100是刚性的。与在第一再分布结构206上直接形成导电通孔相比，使用包含导电通孔108的环形衬底100可以增加封装组件200的垂直支撑。此外，通过将环形衬底100焊接到第一再分布结构206中，可以避免导电通孔从第一再分布结构206的分层。
在一个实施例中，一种封装件包括：第一再分布结构；第一集成电路管芯，连接至第一再分布结构；环形衬底，围绕第一集成电路管芯，环形衬底连接至第一再分布结构，环形衬底包括芯和延伸穿过芯的导电通孔；围绕环形衬底和第一集成电路管芯的密封剂，密封剂延伸穿过环形衬底；在密封剂上的第二再分布结构，第二再分布结构通过环形衬底的导电通孔连接至第一再分布结构。
在一些实施例中，封装件还包括：第一导电连接器，延伸穿过密封剂的第一部分，第一导电连接器将第一集成电路管芯连接至第一再分布结构；第二导电连接器延伸穿过密封剂的第二部分，第二导电连接器将环形衬底连接至第一再分布结构，第二导电连接器的尺寸与第一导电连接器的尺寸不同。在一些实施例中，封装件还包括：底部填充物，设置在第一集成电路管芯和第一再分布结构之间，底部填充物围绕第一导电连接器。在封装件的一些实施例中，底部填充物还围绕第二导电连接器的第一子集，而不包围第二导电连接器的第二子集。在封装件的一些实施例中，底部填充物还包围所有第二导电连接器。在封装件的一些实施例中，第一导电连接器和第二导电连接器包括铜柱。在封装件的一些实施例中，第一导电连接器和第二导电连接器包括焊料连接器。在一些实施例中，封装件还包括：第三导电连接器，其延伸穿过密封剂的第三部分，第三导电连接器将环形衬底连接至第二再分布结构。在封装件的一些实施例中，第三导电连接器包括导电膏。在封装件的一些实施例中，第二再分布结构包括底部介电层和顶部介电层，底部介电层接触第三导电连接器和密封剂，底部介电层的顶面具有比底部介电层的底面更高的平面度。底部介电层比顶部介电层厚。在封装件的一些实施例中，环形衬底还包括：第一导线，位于环形衬底的第一侧，第一导线将导电通孔连接至第一再分布结构；第一导线上的第一阻焊剂，第一阻焊剂包围第一导电连接器；环形衬底的第二侧上的第二导线，第二导线将导电通孔连接至第二再分布结构；第一导线上的第二阻焊剂，第二阻焊剂包围第三导电连接器。在封装件的一些实施例中，第一集成电路管芯的第一高度大于或等于环形衬底的第二高度。在一些实施例中，封装件还包括：连接至第二再分布结构的第二集成电路管芯；封装衬底连接至第一再分布结构。在封装件的一些实施例中，芯包括预浸渍的复合纤维。
在一个实施例中，一种方法包括：图案化衬底中的第一开口；在第一开口中形成导电通孔；形成连接至导电通孔的第一导电连接器，第一导电连接器位于衬底的第一侧上；图案化衬底中的腔；将衬底放置在第一再分布结构上，第一导电连接器耦合到第一再分布结构；将集成电路管芯放置在第一再分布结构上和衬底的腔中，集成电路管芯包括耦合到第一再分布结构的第二导电连接器；用密封剂封装集成电路管芯和衬底；在密封剂上形成第二再分布结构，第二再分布结构通过衬底的导电通孔连接至第一再分布结构。
在一些实施例中，该方法还包括：回流第一导电连接器和第二导电连接器，以同时将衬底和集成电路管芯接合到第一再分布结构。在一些实施例中，该方法还包括：在密封剂中形成第二开口；并在第二开口中分配导电膏。在该方法的一些实施例中，形成第二再分布结构包括：在导电膏和密封剂上形成底部介电层；平坦化底部介电层；并形成沿底部介电层延伸并穿过底部介电层的金属化图案。
在一个实施例中，一种方法包括：将环形衬底连接至第一再分布结构，环形衬底包括：具有腔的芯；第一导电通孔延伸穿过芯；和芯上的导线，导线连接至第一导电通孔；将第一集成电路管芯连接至第一再分布结构，第一集成电路管芯设置在环形衬底的腔中；用密封剂封装环形衬底和第一集成电路管芯；在密封剂上形成第二再分布结构，所述第二再分布结构通过所述第一导电通孔和所述环形衬底的导线连接至所述第一再分布结构。
在一些实施例中，该方法还包括：在密封剂中图案化开口，暴露环形衬底的导线；用导电膏填充开口以形成第二导电通孔，第二再分布结构连接至第二导电通孔。
根据本发明的一些实施例，提供了一种封装件，包括：第一再分布结构；第一集成电路管芯，连接至所述第一再分布结构；环形衬底，围绕所述第一集成电路管芯，所述环形衬底连接至所述第一再分布结构，所述环形衬底包括芯和延伸穿过所述芯的导电通孔；密封剂，围绕所述环形衬底和所述第一集成电路管芯，所述密封剂延伸穿过所述环形衬底；以及第二再分布结构，位于所述密封剂上，所述第二再分布结构通过所述环形衬底的导电通孔连接至所述第一再分布结构。
在上述封装件中，还包括：第一导电连接器，延伸穿过所述密封剂的第一部分，所述第一导电连接器将所述第一集成电路管芯连接至所述第一再分布结构；和第二导电连接器，延伸穿过所述密封剂的第二部分，所述第二导电连接器将环形衬底连接至所述第一再分布结构，所述第二导电连接器的尺寸与所述第一导电连接器的尺寸不同。
在上述封装件中，还包括：底部填充物，设置在所述第一集成电路管芯和所述第一再分布结构之间，所述底部填充物围绕所述第一导电连接器。
在上述封装件中，所述底部填充物还环绕所述第二导电连接器的第一子集，而不环绕所述第二导电连接器的第二子集。
在上述封装件中，所述底部填充物还环绕所有的所述第二导电连接器。
在上述封装件中，所述第一导电连接器和所述第二导电连接器包括铜柱。
在上述封装件中，所述第一导电连接器和所述第二导电连接器包括焊料连接器。
在上述封装件中，还包括：第三导电连接器，延伸穿过所述密封剂的第三部分，第三导电连接器将所述环形衬底连接至所述第二再分布结构。
在上述封装件中，所述第三导电连接器包括导电膏。
在上述封装件中，所述第二再分布结构包括底部介电层和顶部介电层，所述底部介电层接触所述第三导电连接器和所述密封剂，所述底部介电层的顶面比所述底部介电层的底面具有更高的平面度，所述底部介电层比所述顶部介电层厚。
在上述封装件中，所述环形衬底还包括：第一导线，位于所述环形衬底的第一侧上，所述第一导线将所述导电通孔连接至所述第一再分布结构；第一阻焊剂，位于所述第一导线上，所述第一阻焊剂环绕所述第一导电连接器；第二导线，位于所述环形衬底的第二侧上，所述第二导线将所述导电通孔连接至所述第二再分布结构；和第二阻焊剂，位于所述第一导线上，所述第二阻焊剂环绕所述第三导电连接器。
在上述封装件中，所述第一集成电路管芯的第一高度大于或等于所述环形衬底的第二高度。
在上述封装件中，还包括：第二集成电路管芯，连接至所述第二再分布结构；和封装衬底，连接至所述第一再分布结构。
在上述封装件中，所述芯包含预浸渍的复合纤维。
根据本发明的另一些实施例，还提供了一种形成封装件的方法，包括：在衬底中图案化第一开口；在所述第一开口中形成导电通孔；形成连接至所述导电通孔的第一导电连接器，所述第一导电连接器位于所述衬底的第一侧上；在所述衬底中图案化腔；将所述衬底放置在所述第一再分布结构上，所述第一导电连接器耦合到所述第一再分布结构；将所述集成电路管芯放置在所述第一再分布结构上和所述衬底的腔中，所述集成电路管芯包括耦合到所述第一再分布结构的第二导电连接器；用密封剂封装所述集成电路管芯和所述衬底；和在所述密封剂上形成第二再分布结构，所述第二再分布结构通过所述衬底的导电通孔连接至所述第一再分布结构。
在上述方法中，还包括：回流所述第一导电连接器和所述第二导电连接器以同时将所述衬底和所述集成电路管芯接合至所述第一再分布结构。
在上述方法中，还包括：在所述密封剂中形成第二开口；和在所述第二开口中分配导电膏。
在上述方法中，形成所述第二再分布结构包括：在所述导电膏和所述密封剂上形成底部介电层；平坦化所述底部介电层；和形成沿着所述底部介电层延伸并穿过所述底部介电层的金属化图案。
根据本发明的又一些实施例，还提供了一种形成封装件的方法，包括：将环形衬底连接至第一再分布结构，所述环形衬底包括：具有腔的芯；第一导电通孔，延伸穿过所述芯；和导线，位于所述芯上，所述导线连接至所述第一导电通孔；将第一集成电路管芯连接至所述第一再分布结构，所述第一集成电路管芯设置在所述环形衬底的腔中；用密封剂将所述环形衬底和所述第一集成电路管芯封装在一起；和在所述密封剂上形成第二再分布结构，所述第二再分布结构通过所述第一导电通孔和所述环形衬底的导线连接至所述第一再分布结构。
在上述方法中，还包括：在所述密封剂中图案化开口，从而暴露所述环形衬底的导线；以及用导电膏填充所述开口以形成第二导电通孔，所述第二再分布结构连接至所述第二导电通孔。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种封装件，包括：
第一再分布结构；
第一集成电路管芯，连接至所述第一再分布结构；
环形衬底，围绕所述第一集成电路管芯，所述环形衬底连接至所述第一再分布结构，所述环形衬底包括芯和延伸穿过所述芯的导电通孔；
密封剂，围绕所述环形衬底和所述第一集成电路管芯，所述密封剂延伸穿过所述环形衬底；以及
第二再分布结构，位于所述密封剂上，所述第二再分布结构通过所述环形衬底的导电通孔连接至所述第一再分布结构。
2.根据权利要求1所述的封装件，还包括：
第一导电连接器，延伸穿过所述密封剂的第一部分，所述第一导电连接器将所述第一集成电路管芯连接至所述第一再分布结构；和
第二导电连接器，延伸穿过所述密封剂的第二部分，所述第二导电连接器将环形衬底连接至所述第一再分布结构，所述第二导电连接器的尺寸与所述第一导电连接器的尺寸不同。
3.根据权利要求2所述的封装件，还包括：
底部填充物，设置在所述第一集成电路管芯和所述第一再分布结构之间，所述底部填充物围绕所述第一导电连接器。
4.根据权利要求3所述的封装件，其中，所述底部填充物还环绕所述第二导电连接器的第一子集，而不环绕所述第二导电连接器的第二子集。
5.根据权利要求3所述的封装件，其中，所述底部填充物还环绕所有的所述第二导电连接器。
6.根据权利要求2所述的封装件，其中，所述第一导电连接器和所述第二导电连接器包括铜柱。
7.根据权利要求2所述的封装件，其中，所述第一导电连接器和所述第二导电连接器包括焊料连接器。
8.根据权利要求2所述的封装件，还包括：
第三导电连接器，延伸穿过所述密封剂的第三部分，第三导电连接器将所述环形衬底连接至所述第二再分布结构。
9.一种形成封装件的方法，包括：
在衬底中图案化第一开口；
在所述第一开口中形成导电通孔；
形成连接至所述导电通孔的第一导电连接器，所述第一导电连接器位于所述衬底的第一侧上；
在所述衬底中图案化腔；
将所述衬底放置在所述第一再分布结构上，所述第一导电连接器耦合到所述第一再分布结构；
将所述集成电路管芯放置在所述第一再分布结构上和所述衬底的腔中，所述集成电路管芯包括耦合到所述第一再分布结构的第二导电连接器；
用密封剂封装所述集成电路管芯和所述衬底；和
在所述密封剂上形成第二再分布结构，所述第二再分布结构通过所述衬底的导电通孔连接至所述第一再分布结构。
10.一种形成封装件的方法，包括：
将环形衬底连接至第一再分布结构，所述环形衬底包括：
具有腔的芯；
第一导电通孔，延伸穿过所述芯；和
导线，位于所述芯上，所述导线连接至所述第一导电通孔；
将第一集成电路管芯连接至所述第一再分布结构，所述第一集成电路管芯设置在所述环形衬底的腔中；
用密封剂将所述环形衬底和所述第一集成电路管芯封装在一起；和
在所述密封剂上形成第二再分布结构，所述第二再分布结构通过所述第一导电通孔和所述环形衬底的导线连接至所述第一再分布结构。
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Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102568705B1 (ko) 2018-10-05 2023-08-22 삼성전자주식회사 반도체 패키지, 반도체 패키지 제조방법 및 재배선 구조체 제조방법
KR102540829B1 (ko) * 2018-10-05 2023-06-08 삼성전자주식회사 반도체 패키지, 반도체 패키지 제조방법 및 재배선 구조체 제조방법
US10903169B2 (en) * 2019-04-30 2021-01-26 Advanced Semiconductor Engineering, Inc. Conductive structure and wiring structure including the same
US11600567B2 (en) * 2019-07-31 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for manufacturing the same
USD920265S1 (en) * 2019-09-29 2021-05-25 China Chippacking Technology Co., Ltd. Integrated circuit package
USD920266S1 (en) * 2019-09-29 2021-05-25 China Chippacking Technology Co., Ltd. Integrated circuit package
DE102019132314B4 (de) * 2019-11-28 2022-03-03 Infineon Technologies Ag Package mit Einkapselung unter Kompressionsbelastung
CN113035801A (zh) * 2019-12-25 2021-06-25 台湾积体电路制造股份有限公司 存储器装置及其制造方法
KR20210087299A (ko) * 2020-01-02 2021-07-12 삼성전기주식회사 고주파 모듈 및 이를 포함하는 전자기기
US11735538B2 (en) * 2020-02-17 2023-08-22 Wolfspeed, Inc. Semiconductor having a backside wafer cavity for radio frequency (RF) passive device integration and/or improved cooling and process of implementing the same
KR20210104364A (ko) * 2020-02-17 2021-08-25 삼성전자주식회사 반도체 패키지
US11264359B2 (en) 2020-04-27 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Chip bonded to a redistribution structure with curved conductive lines
US11508665B2 (en) * 2020-06-23 2022-11-22 Taiwan Semiconductor Manufacturing Co., Ltd. Packages with thick RDLs and thin RDLs stacked alternatingly
US11444069B2 (en) * 2020-06-29 2022-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. 3D semiconductor package including memory array
US11670601B2 (en) 2020-07-17 2023-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Stacking via structures for stress reduction
US20220037243A1 (en) * 2020-07-31 2022-02-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method
CN114068487A (zh) 2020-08-06 2022-02-18 力成科技股份有限公司 封装结构及其制造方法
TWI777633B (zh) * 2020-08-06 2022-09-11 力成科技股份有限公司 封裝結構及其製造方法
US11540396B2 (en) * 2020-08-28 2022-12-27 Unimicron Technology Corp. Circuit board structure and manufacturing method thereof
US20220071010A1 (en) * 2020-08-28 2022-03-03 Unimicron Technology Corp. Circuit board structure and manufacturing method thereof
KR20220042705A (ko) * 2020-09-28 2022-04-05 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
US11894243B2 (en) * 2020-11-20 2024-02-06 Sj Semiconductor (Jiangyin) Corporation Wafer system-level fan-out packaging structure and manufacturing method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101720165A (zh) * 2008-10-08 2010-06-02 日本特殊陶业株式会社 组件内置布线基板及其制造方法
US20140054773A1 (en) * 2012-08-27 2014-02-27 Shinko Electric Industries Co., Ltd. Electronic component built-in substrate and method of manufacturing the same
JP2014192452A (ja) * 2013-03-28 2014-10-06 Shinko Electric Ind Co Ltd 電子部品内蔵基板及びその製造方法
US20160338202A1 (en) * 2015-05-11 2016-11-17 Samsung Electro-Mechanics Co., Ltd. Electronic component package and method of manufacturing the same
US20170309558A1 (en) * 2016-04-20 2017-10-26 Ibiden Co., Ltd. Interposer and method for manufacturing interposer

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101037229B1 (ko) * 2006-04-27 2011-05-25 스미토모 베이클리트 컴퍼니 리미티드 반도체 장치 및 반도체 장치의 제조 방법
TWI366896B (en) * 2006-11-30 2012-06-21 Carrier structure embedded with chip and method for fabricating thereof
US7989950B2 (en) * 2008-08-14 2011-08-02 Stats Chippac Ltd. Integrated circuit packaging system having a cavity
US20110024899A1 (en) * 2009-07-28 2011-02-03 Kenji Masumoto Substrate structure for cavity package
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US20130249101A1 (en) * 2012-03-23 2013-09-26 Stats Chippac, Ltd. Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
JP6152254B2 (ja) * 2012-09-12 2017-06-21 新光電気工業株式会社 半導体パッケージ、半導体装置及び半導体パッケージの製造方法
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
JP6173781B2 (ja) * 2013-06-10 2017-08-02 新光電気工業株式会社 配線基板及び配線基板の製造方法
US8980691B2 (en) * 2013-06-28 2015-03-17 Stats Chippac, Ltd. Semiconductor device and method of forming low profile 3D fan-out package
KR101550496B1 (ko) * 2013-07-24 2015-09-04 에스티에스반도체통신 주식회사 적층형 반도체패키지 및 그 제조방법
KR101514539B1 (ko) * 2013-08-29 2015-04-22 삼성전기주식회사 전자부품 내장기판
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US10121768B2 (en) * 2015-05-27 2018-11-06 Bridge Semiconductor Corporation Thermally enhanced face-to-face semiconductor assembly with built-in heat spreader and method of making the same
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
RU2663688C1 (ru) * 2014-09-26 2018-08-08 Интел Корпорейшн Корпусированная интегральная схема, содержащая соединенный проволочными перемычками многокристальный пакет
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
KR20160132751A (ko) * 2015-05-11 2016-11-21 삼성전기주식회사 전자부품 패키지 및 그 제조방법
US10109588B2 (en) 2015-05-15 2018-10-23 Samsung Electro-Mechanics Co., Ltd. Electronic component package and package-on-package structure including the same
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
KR102450576B1 (ko) 2016-01-22 2022-10-07 삼성전자주식회사 전자 부품 패키지 및 그 제조방법
US10818621B2 (en) * 2016-03-25 2020-10-27 Samsung Electronics Co., Ltd. Fan-out semiconductor package
US10068855B2 (en) 2016-09-12 2018-09-04 Samsung Electro-Mechanics Co., Ltd. Semiconductor package, method of manufacturing the same, and electronic device module
US10026681B2 (en) * 2016-09-21 2018-07-17 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
KR101952864B1 (ko) * 2016-09-30 2019-02-27 삼성전기주식회사 팬-아웃 반도체 패키지
KR101939046B1 (ko) * 2017-10-31 2019-01-16 삼성전기 주식회사 팬-아웃 반도체 패키지
KR101942746B1 (ko) * 2017-11-29 2019-01-28 삼성전기 주식회사 팬-아웃 반도체 패키지
KR101912290B1 (ko) * 2017-12-06 2018-10-29 삼성전기 주식회사 팬-아웃 반도체 패키지

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101720165A (zh) * 2008-10-08 2010-06-02 日本特殊陶业株式会社 组件内置布线基板及其制造方法
US20140054773A1 (en) * 2012-08-27 2014-02-27 Shinko Electric Industries Co., Ltd. Electronic component built-in substrate and method of manufacturing the same
JP2014192452A (ja) * 2013-03-28 2014-10-06 Shinko Electric Ind Co Ltd 電子部品内蔵基板及びその製造方法
US20160338202A1 (en) * 2015-05-11 2016-11-17 Samsung Electro-Mechanics Co., Ltd. Electronic component package and method of manufacturing the same
US20170309558A1 (en) * 2016-04-20 2017-10-26 Ibiden Co., Ltd. Interposer and method for manufacturing interposer

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