TW202015137A - 封裝體及其形成方法 - Google Patents

封裝體及其形成方法 Download PDF

Info

Publication number
TW202015137A
TW202015137A TW108133988A TW108133988A TW202015137A TW 202015137 A TW202015137 A TW 202015137A TW 108133988 A TW108133988 A TW 108133988A TW 108133988 A TW108133988 A TW 108133988A TW 202015137 A TW202015137 A TW 202015137A
Authority
TW
Taiwan
Prior art keywords
package
ring
dielectric layer
substrate
integrated circuit
Prior art date
Application number
TW108133988A
Other languages
English (en)
Other versions
TWI720624B (zh
Inventor
蔡柏豪
翁得期
周孟緯
林孟良
莊博堯
鄭心圃
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202015137A publication Critical patent/TW202015137A/zh
Application granted granted Critical
Publication of TWI720624B publication Critical patent/TWI720624B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

在一實施例中，封裝體包含:第一重佈線結構；第一積體電路晶粒連接至第一重佈線結構；環狀基底圍繞第一積體電路晶粒，環狀基底連接至第一重佈線結構，環狀基底包含核心及延伸通過核心的導通孔；封裝劑圍繞環狀基底和第一積體電路晶粒，封裝劑延伸通過環狀基底；以及第二重佈線結構在封裝劑上，第二重佈線結構透過環狀基底的導通孔連接至第一重佈線結構。

Description

封裝體及其形成方法
本發明實施例係有關於半導體技術，且特別是有關於封裝體及其形成方法。
由於各種電子組件(例如電晶體、二極體、電阻、電容等)的積體密度持續改善，因此半導體工業已經歷了快速成長。在多數情況下，積體密度的改善源自最小部件尺寸的迭代縮小，使得更多組件能夠集成在既定區域中。隨著縮小電子元件的需求的成長，已經出現了對更小且更有創意的半導體晶粒封裝技術的需求。此封裝系統的一個範例為層疊封裝(Package-on-Package，PoP)技術。在層疊封裝裝置中，頂部半導體封裝體堆疊於底部半導體封裝體的頂部上，以提供高度積體和組件密度。層疊封裝技術一般能夠在印刷電路板(printed circuit board，PCB)上生產具有增強功能和小佔用面積的半導體裝置。
在一些實施例中，提供封裝體，封裝體包含第一重佈線結構；第一積體電路晶粒，連接至第一重佈線結構；環狀基底，圍繞第一積體電路晶粒，環狀基底連接至第一重佈線結構，環狀基底包含核心及延伸通過核心的導通孔；封裝劑，圍繞環狀基底和第一積體電路晶粒，封裝劑延伸通過環狀基底；以及第二重佈線結構，在封裝劑上，第二重佈線結構透過環狀基底的導通孔連接至第一重佈線結構。
在一些其他實施例中，提供封裝體的形成方法，此方法包含將基底圖案化以形成第一開口；在第一開口中形成導通孔；形成第一導電連接器連接至導通孔，第一導電連接器在基底的第一側上；將基底圖案化以形成空腔；將基底放置在第一重佈線結構上，第一導電連接器耦接至第一重佈線結構；將積體電路晶粒放置於第一重佈線結構上並在基底的空腔中，積體電路晶粒包含耦接至第一重佈線結構的第二導電連接器；以封裝劑封裝積體電路晶粒和基底；以及在封裝劑上形成第二重佈線結構，第二重佈線結構透過基底的導通孔連接至第一重佈線結構。
在另外一些實施例中，提供封裝體的形成方法，此方法包含將環狀基底連接至第一重佈線結構，環狀基底包含:核心，具有空腔；第一導通孔，延伸通過核心；及導線，在核心上，導線連接至第一導通孔；將第一積體電路晶粒連接至第一重佈線結構，第一積體電路晶粒設置於環狀基底的空腔中；以封裝劑封裝環狀基底和第一積體電路晶粒；以及在封裝劑上形成第二重佈線結構，第二重佈線結構透過環狀基底的第一導通孔和導線連接至第一重佈線結構。
要瞭解的是以下的揭露內容提供許多不同的實施例或範例，以實施提供之主體的不同部件。以下敘述各個構件及其排列方式的特定範例，以求簡化揭露內容的說明。當然，這些僅為範例並非用以限定本發明。例如，以下的揭露內容敘述了將一第一部件形成於一第二部件之上或上方，即表示其包含了所形成的上述第一部件與上述第二部件是直接接觸的實施例，亦包含了尚可將附加的部件形成於上述第一部件與上述第二部件之間，而使上述第一部件與上述第二部件可能未直接接觸的實施例。此外，揭露內容中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。
再者，為了方便描述圖式中一元件或部件與另一(複數)元件或(複數)部件的關係，可使用空間相關用語，例如“在...之下”、“下方”、“下部”、“上方”、“上部”及類似的用語。除了圖式所繪示的方位之外，空間相關用語也涵蓋裝置在使用或操作中的不同方位。所述裝置也可被另外定位(例如，旋轉90度或者位於其他方位)，並對應地解讀所使用的空間相關用語的描述。
依據一些實施例，形成或提供環狀基底。環狀基底包含具有導線和導通孔的基底核心。環狀基底中的空腔(cavity)可容納半導體元件(例如積體電路晶粒)。接著，可將環狀基底與包含設置於空腔中的積體電路晶粒的封裝體一起封裝。例如以模塑化合物將封裝體封裝。由於環狀基底為剛性，因此當形成封裝體時，環狀基底提供機械性支撐。透過避免封裝劑(encapsulant)與封裝體的其他組件之間的熱膨脹係數(coefficient of thermal expansion，CTE)不匹配，可縮小翹曲並降低封裝體的整體堆疊高度。
第1-7B圖為依據一些實施例之形成環狀基底的製程的中間步驟的剖面示意圖。雖然顯示形成一個環狀基底100，但是應當理解的是可透過使用相同的晶圓或基底同時形成多個環狀基底100，且之後可單切以形成個別的環狀基底100。
在第1圖中，提供具有晶種層104在兩側上的基底核心102。基底核心102可形成自預浸漬複合纖維(預浸料)(prepreg)、絕緣膜或增層膜、紙、玻璃纖維、不織布玻璃纖維、矽或類似物。基底核心102由有助於與矽達到熱膨脹係數匹配的材料形成。在一些實施例中，基底核心102由包含玻璃纖維和樹脂的預浸料形成。晶種層104可為一層或多層銅、鈦、鎳、鋁、前述之組合或類似物，且沉積或層壓至基底核心102的兩側上。在一些實施例中，基底核心102和晶種層104為覆銅環氧樹脂浸漬的玻璃布層積物、覆銅聚醯亞胺浸漬的玻璃布層積物或類似物。
在第2圖中，開口106形成於基底核心102和晶種層104中。在一些實施例中，開口106透過雷射鑽孔形成。也可使用其他製程(例如以鑽頭進行機械鑽孔)來形成開口106。開口106可具有任何上視形狀，例如多邊形、圓形或類似形狀。接著，可進行清潔製程以清潔開口106附近沾有基底核心102的移除材料的區域。清潔製程可為去汙(desmear)製程。去汙製程可機械性(例如以濕漿料中的細磨料噴砂)、化學性完成(以有機溶劑、過錳酸鹽和類似物的組合清洗)或透過機械性和化學性製程的組合完成。
在第3圖中，導通孔108形成於開口106中，且導線110形成於基底核心102的兩側上。導通孔108和導線110可由導電材料形成，例如銅、鈦、鎢、鋁或類似物。導通孔108和導線110可由相同材料或不同材料形成，且可透過相同製程或不同製程形成。在一些實施例中，導通孔108透過第一製程形成，而導線110透過第二製程形成。舉例來說，可使用第一鍍覆製程(例如無電電鍍)以在開口106中沉積導電材料，進而形成導通孔108。在使用無電電鍍的實施例中，晶種層可形成於開口106中。可透過使用晶種層104進行第二鍍覆製程(例如電鍍、無電電鍍或類似方法)。在晶種層104上形成光阻並將光阻圖案化。光阻可透過旋塗或類似方法形成，且可將光阻曝光以圖案化。光阻的圖案對應至導線110。圖案化形成開口通過光阻以暴露出晶種層。導電材料形成於光阻的開口中以及晶種層的暴露部分上。導電材料可透過鍍覆形成，例如電鍍或無電電鍍或類似方法。移除光阻和晶種層104沒有導電材料形成於其上的部分。光阻可透過合適的灰化或剝離製程移除，例如使用氧電漿或類似物。當移除光阻之後，例如透過使用合適的蝕刻製程(例如濕蝕刻或乾蝕刻)移除晶種層104的暴露部分。晶種層104的剩下部分和導電材料形成導線110。
在第4圖中，防焊層112形成於基底核心102的兩側上及導線110上。防焊層112保護基底核心102的區域免受外部損壞。在一些實施例中，防焊層112透過沉積感光性介電層，以光學圖案將感光材料曝光，並將曝光層顯影以形成開口114來形成。在一些實施例中，防焊層112透過沉積非感光性介電層(例如氧化矽或氮化矽或類似物)，並以合適的光微影和蝕刻技術將介電層圖案化以形成開口114來形成。開口114暴露出導線110可在後續製程中作為連接墊的下方部分。
在第5圖中，保護層116選擇性地形成於開口114中(導線110的暴露部分上)。保護層116可各為單一層或包含複數層的複合層。保護層116可由金屬形成，例如鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似物或前述之組合。在一些實施例中，保護層116可為化學鍍鎳浸金(Electroless Nickel Immersion Gold，ENIG)，其包含在導線110的暴露部分上的金層及在金層上的鎳層。在一些實施例中，保護層116可為化學鍍鎳鈀浸金(Electroless Nickel Electroless Palladium Immersion Gold，ENEPIG)，其包含在導線110的暴露部分上的金層、在金層上的鈀層及在鈀層上的鎳層。保護層116可透過電鍍、無電電鍍、浸漬、物理氣相沉積(physical vapor deposition，PVD)或前述之組合形成。保護層116的硬度可大於下方導線110的硬度。
在第6圖中，導電連接器118形成於開口114中。在使用保護層116的實施例中，導電連接器118接觸保護層116。在省略保護層116的實施例中，導電連接器118接觸導線110的暴露部分。導電連接器118可為球柵陣列(ball grid array，BGA)連接器、焊球、金屬柱、控制塌陷高度晶片連接(controlled collapse chip connection，C4)凸塊、微凸塊、化學鍍鎳鈀浸金(ENEPIG)形成的凸塊或類似物。導電連接器118可包含導電材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似物或前述之組合。在一些實施例中，導電連接器118為焊料連接器，焊料連接器透過先使用常用方法(例如蒸鍍、電鍍、印刷、焊料轉印、植焊球或類似方法)形成焊料層來形成。當焊料層形成於結構上之後，可進行回焊以將材料塑形為所期望的凸塊形狀。在另一實施例中，導電連接器118包括金屬柱(例如銅柱)，金屬柱透過濺鍍、印刷、電鍍、無電電鍍、化學氣相沉積(chemical vapor deposition，CVD)或類似方法形成。金屬柱可無焊料且具有大致垂直的側壁。
在第7A圖中，空腔120透過移除基底核心102和防焊層112的一部分形成。移除材料形成空腔120可透過使用電腦數值控制(computer numeric control，CNC)的機械鑽孔製程來達成。在這些實施例中，材料可透過機械鑽孔移除，鑽孔的位置由電腦或控制器來控制。移除也可透過其他製程達成，例如雷射切割製程、雷射鑽孔製程或類似方法。材料的剩下部分形成環狀基底100。
第7B圖為第7A圖的環狀基底100的由上而下視圖。如圖所示，環狀基底100在由上而下視圖中具有環形。空腔120延伸通過環狀基底100的中心部分以形成環。第7B圖中的範例環狀基底100為矩形。應當理解的是，在其他實施例中可具有其他形狀。舉例來說，環狀基底100可為圓形、三角形或類似形狀。
第8-17圖為依據一些實施例之將環狀基底100與其他元件封裝以形成封裝組件200的製程的中間步驟的剖面示意圖。封裝組件200包含多個區域，且在每一區中封裝一個環狀基底100。圖中顯示封裝組件200的一區。
在第8圖中，提供承載基底202，且離型層(release layer)204形成於承載基底202上。承載基底202可為玻璃承載基底、陶瓷承載基底或類似物。承載基底202可為晶圓，使得多個封裝體可形成於承載基底202上。離型層204可由聚合物為主的材料形成，可將離型層204與承載基底202一同從後續步驟中形成的上方結構移除。在一些實施例中，離型層204為環氧基熱釋放材料，環氧基熱釋放材料在加熱時失去其黏性，例如光熱轉換(light-to-heat conversion，LTHC)釋放塗層。在其他實施例中，離型層204為紫外(ultra-violet，UV)膠，紫外膠在暴露於紫外光時失去其黏性。離型層204可以液態配置並固化，可為層壓至承載基底202上的層疊膜或可為類似物。離型層204的頂表面可齊平且可據又高度的共平面性。
在第9圖中，第一重佈線結構206形成於離型層204上。第一重佈線結構206包含介電層208、212、216和220、金屬圖案210、214和218及凸塊下金屬層(under bump metallurgies，UBMs)222。金屬圖案210、214和218也可被稱為重佈線層或重佈線。顯示第一重佈線結構206作為範例，可在第一重佈線結構206中形成更多或更少的介電層和金屬圖案。如果形成較少的介電層和金屬圖案，可省略以下所述的步驟和製程。如果形成較多的介電層和金屬圖案，可重複以下所述的步驟和製程。
作為形成第一重佈線結構206的範例，介電層208沉積於離型層204上。在一些實施例中，介電層208由感光材料形成，例如聚苯並噁唑(polybenzoxazole，PBO)、聚醯亞胺、苯並環丁烯(benzocyclobutene，BCB)或類似物，且可透過使用微影遮罩來圖案化。介電層208可透過旋塗、層壓、化學氣相沉積、類似方法或前述之組合形成。接著，將介電層208圖案化。圖案化形成開口暴露出離型層204的一部分。可透過合適的製程來圖案化，例如當介電層208為感光材料時，將介電層208暴露於光線，或例如透過非等向性蝕刻來蝕刻。如果介電層208為感光材料，可在曝光後將介電層208顯影。
接著，形成金屬圖案210。金屬圖案210包含在介電層208的主表面上並沿介電層208的主表面延伸的導線。金屬圖案210更包含延伸通過介電層208的導通孔。為了形成金屬圖案210，晶種層形成於介電層208上方以及延伸通過介電層208的開口中。在一些實施例中，晶種層為金屬層，金屬層可為單一層或包括由不同材料形成的複數個子層的複合層。在一些實施例中，晶種層包括鈦層和在鈦層上方的銅層。晶種層可透過使用例如物理氣相沉積或類似方法形成。接著，在晶種層上形成光阻並將光阻圖案化。光阻可透過旋塗或類似方法形成，且可曝光以圖案化。光阻的圖案對應至金屬圖案210。圖案化形成開口通過光阻以暴露出晶種層。接著，導電材料形成於光阻的開口中和晶種層的暴露部分上。導電材料可透過鍍覆(例如電鍍或無電電鍍或類似方法)形成。導電材料可包括金屬，例如銅、鈦、鎢、鋁或類似物。導電材料和下方部分的晶種層的組合形成金屬圖案210。移除光阻和晶種層不形成導電材料於其上的部分。光阻可透過合適的灰化或剝離製程移除，例如使用氧電漿或類似物。當移除光阻之後，例如透過使用合適的蝕刻製程移除晶種層的暴露部分，例如透過濕蝕刻或乾蝕刻。
介電層212沉積於金屬圖案210和介電層208上。介電層212可以相似於介電層208的形成方法形成，且可由與介電層208相同的材料形成。
接著，形成金屬圖案214。金屬圖案214包含在介電層212的主表面上並沿介電層212的主表面延伸的導線。金屬圖案214更包含延伸通過介電層212的導通孔，以物理及電性連接至金屬圖案210。金屬圖案214可以相似於金屬圖案210的形成方法形成，且可由與金屬圖案210相同的材料形成。金屬圖案214的導通孔具有比金屬圖案210的導通孔更小的寬度。如此一來，當為了形成金屬圖案214而將介電層212圖案化時，介電層212中的開口的寬度小於介電層208中的開口的寬度。
介電層216沉積於金屬圖案214和介電層212上。介電層216可以相似於介電層208的形成方法形成，且可由與介電層208相同的材料形成。
接著，形成金屬圖案218。金屬圖案218包含在介電層216的主表面上並沿介電層216的主表面延伸的導線。金屬圖案218更包含延伸通過介電層216的導通孔，以物理及電性連接至金屬圖案214。金屬圖案218可以相似於金屬圖案210的形成方法形成，且可由與金屬圖案210相同的材料形成。金屬圖案218的導通孔具有比金屬圖案210的導通孔更小的寬度。如此一來，當為了形成金屬圖案218而將介電層216圖案化時，介電層216中的開口的寬度小於介電層208中的開口的寬度。
介電層220沉積於金屬圖案218和介電層216上。介電層220可以相似於介電層208的形成方法形成，且可由與介電層208相同的材料形成。
凸塊下金屬層222形成於介電層220上並延伸通過介電層220。作為形成凸塊下金屬層222的範例，可將介電層220圖案化以形成暴露出金屬圖案218的一部分的開口。可透過合適的製程來圖案化，例如當介電層220為感光材料時，將介電層220暴露於光線，或例如透過非等向性蝕刻來蝕刻。如果介電層220為感光材料，可在曝光後將介電層220顯影。用於凸塊下金屬層222的開口比用於金屬圖案210、214和218的導通孔部分的開口更寬。晶種層形成於介電層220上方及開口中。在一些實施例中，晶種層為金屬層，金屬層可為單一層或包括由不同材料形成的複數個子層的複合層。在一些實施例中，晶種層包括鈦層和在鈦層上方的銅層。晶種層可透過使用例如物理氣相沉積或類似方法形成。接著，在晶種層上形成光阻並將光阻圖案化。光阻可透過旋塗或類似方法形成，且可曝光以圖案化。光阻的圖案對應至凸塊下金屬層222。圖案化形成開口通過光阻以暴露出晶種層。接著，導電材料形成於光阻的開口中和晶種層的暴露部分上。導電材料可透過鍍覆(例如電鍍或無電電鍍或類似方法)形成。導電材料可包括金屬，例如銅、鈦、鎢、鋁或類似物。接著，移除光阻和晶種層不形成導電材料於其上的部分。光阻可透過合適的灰化或剝離製程移除，例如使用氧電漿或類似物。當移除光阻之後，例如透過使用合適的蝕刻製程移除晶種層的暴露部分，例如透過濕蝕刻或乾蝕刻。晶種層的剩下部分和導電材料形成凸塊下金屬層222。在形成不同的凸塊下金屬層222的實施例中，可使用更多的光阻和圖案化步驟。
凸塊下金屬層222可不全具有相同寬度。在一些實施例中，在第一區206A的第一重佈線結構206的凸塊下金屬層222的第一子集具有第一寬度W1 ，而在第二區206B的第一重佈線結構206的凸塊下金屬層222的第二子集具有第二寬度W2 。第一寬度W1 可不同於第二寬度W2 ，且在一些實施例中，第一寬度W1 大於第二寬度W2 。
在第10圖中，環狀基底100放置於第一重佈線結構206上方。環狀基底100可例如使用取放(pick-and-place)工具對齊及放置。環狀基底100的導電連接器118與第一區206A的凸塊下金屬層222對齊，且環狀基底100的空腔120與第二區206B的凸塊下金屬層222對齊。在導電連接器118為焊料的實施例中，可不立即將導電連接器118回焊來將環狀基底100接合至凸塊下金屬層222。導電連接器118的回焊步驟可延遲至後續的製程步驟。在導電連接器118為銅柱的實施例中，可形成焊料將導電連接器118接合至第一重佈線結構206。
在第11圖中，積體電路晶粒224放置於第一重佈線結構206上方。積體電路晶粒224可為邏輯晶粒(例如中央處理器、微控制器等)、記憶體晶粒(例如動態隨機存取記憶體(dynamic random access memory，DRAM)晶粒、靜態隨機存取記憶體(static random access memory，SRAM)晶粒)、電源管理晶粒(例如電源管理積體電路(power management integrated circuit，PMIC)晶粒)、射頻(radio frequency，RF)晶粒、感測晶粒、微機電系統(micro-electro-mechanical-system，MEMS)晶粒、訊號處理晶粒(例如數位訊號處理(digital signal processing，DSP)晶粒)、前端晶粒(例如類比前端(analog front-end，AFE)晶粒)、類似物或前述之組合(例如系統晶片(system-on-chip，SoC))。
積體電路晶粒224包含半導體基底，有著例如電晶體、二極體、電容、電阻等的元件形成於半導體基底中及/或半導體基底上。這些元件可透過例如在半導體基底上的一個或多個介電層中的金屬圖案所形成的互連結構來互連，以形成積體電路。積體電路晶粒224更包括接墊226，以作外部連接。接墊226在被稱為積體電路晶粒224的相應主動側上，且可在互連結構的最上層中。由於積體電路晶粒224的主動側面向第一重佈線結構206，因此第一重佈線結構206也可被稱為“前側重佈線結構”。導電連接器228可形成於接墊226上。導電連接器228可由導電材料形成，例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似物或前述之組合。在一些實施例中，導電連接器228為焊料連接器。
積體電路晶粒224可例如使用取放工具對齊及放置。積體電路晶粒224放置於空腔120中，使得導電連接器228對齊第二區206B中的凸塊下金屬層222。在放置積體電路晶粒224之後，將導電連接器228回焊以形成對應的凸塊下金屬層222與接墊226之間的接合，將積體電路晶粒224物理及電性地連接至第一重佈線結構206。在環狀基底100的導電連接器118為焊料並延遲回焊的實施例中，可在相同的回焊製程中同時將導電連接器118和228回焊。如此一來，也可將導電連接器118回焊以形成對應的凸塊下金屬層222與導線110之間的接合，將環狀基底100物理及電性地連接至第一重佈線結構206。換句話說，積體電路晶粒224和環狀基底100可同時接合至第一重佈線結構206。導電連接器118和228可為不同尺寸。在一些實施例中，環狀基底100的高度H1 小於或等於積體電路晶粒224的高度H2 。高度H1 也可大於高度H2 。再者，積體電路晶粒224的寬度小於空腔120的寬度。
應當理解的是，積體電路晶粒224和環狀基底100可以任何順序放置於第一重佈線結構206上方。在一些實施例中，先放置積體電路晶粒224，且放置環狀基底100圍繞積體電路晶粒224。
在第12圖中，底部填充材料230可形成於積體電路晶粒224與第一重佈線結構206之間圍繞導電連接器228。如此一來，可保護導電連接器228免受機械力影響。底部填充材料230可在附接積體電路晶粒224之後以毛細流動製程(capillary flow process)形成，或可在附接積體電路晶粒224之前以合適的沉積方法形成。
在第13圖中，封裝劑232形成於各種組件上。封裝劑232可為模塑化合物、環氧樹脂或類似物，且可透過壓縮成形、轉移成形或類似方法來應用。封裝劑232可形成於第一重佈線結構206上方，以掩埋或覆蓋積體電路晶粒224和環狀基底100，並填充空腔120。掩埋環狀基底100的封裝劑232的部分具有厚度T1 。在一些實施例中，厚度T1 在約10µm至約100µm的範圍中。接著，將封裝劑232固化，且可選擇性地透過例如研磨或化學機械研磨(chemical-mechanical polish，CMP)製程來平坦化。在形成之後，封裝劑232具有高度H3 ，高度H3 大於高度H1 和H2 。例如在省略底部填充材料230的實施例中，封裝劑232也可形成於第一重佈線結構206與積體電路晶粒224之間。
環狀基底100佔據封裝組件200的垂直高度的顯著部分，所以可減少需覆蓋積體電路晶粒224的封裝劑232的量。舉例來說，高度H3 與高度H1 的比例可在約1:0.14至約1:0.60。因此，可增加封裝組件200的整體高度而不顯著地增加封裝劑232的使用量。減少封裝劑232的使用量可幫助避免由封裝劑232與封裝組件200的其他組件之間的熱膨脹係數不匹配導致的封裝翹曲。
在第14圖中，形成於封裝劑232中的開口234暴露出環狀基底100的保護層116。開口234可透過鑽孔製程形成，例如雷射鑽孔、機械鑽孔或類似方法。開口234可具有有著上部寬度W3 以及小於或等於上部寬度W3 的下部寬度W4 的錐形輪廓。在一些實施例中，上部寬度W3 在約50µm至約350µm的範圍中，且下部寬度W4 在約50µm至約200µm的範圍中。
在第15圖中，導電連接器236形成於開口234中。導電連接器236可由金屬形成，例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似物或前述之組合。在一些實施例中，導電連接器236由膏(paste)形成，例如銅膏、焊料膏、銀膏或類似物，且透過印刷製程或類似方法配製。在使用印刷製程的實施例中，有著所期望圖案的導電連接器236透過使用模板印刷在封裝劑232上及開口234中。在形成之後，將導電膏固化以將其硬化，進而形成導電連接器236。導電膏可透過退火製程來固化，退火製程在溫度約80ºC至約230ºC中進行，且持續時間在約20分至約4小時。在導電連接器236為膏的實施例中，導電連接器236可過填充開口，使得導電連接器236具有延伸通過封裝劑232的導通孔部分以及沿封裝劑232的頂表面延伸的上部。
在第16圖中，第二重佈線結構238形成於導電連接器236和封裝劑232上方。由於積體電路晶粒224的主動側遠離第二重佈線結構238，因此第二重佈線結構238也可被稱為“背側重佈線結構”。 第二重佈線結構238包含介電層240、244、248和252、金屬圖案242、246和250以及凸塊下金屬層254。金屬圖案可被稱為重佈線層或重佈線。顯示第二重佈線結構238作為範例，可在第二重佈線結構238中形成更多或更少的介電層和金屬圖案。如果形成較少的介電層和金屬圖案，可省略以下所述的步驟和製程。如果形成較多的介電層和金屬圖案，可重複以下所述的步驟和製程。
作為形成第二重佈線結構238的範例，介電層240沉積於導電連接器236和封裝劑232上。在一些實施例中，介電層240由感光材料形成，例如聚苯並噁唑、聚醯亞胺、苯並環丁烯或類似物，且可透過使用微影遮罩來圖案化。介電層240可透過旋塗、層壓、化學氣相沉積、類似方法或前述之組合形成。接著，將介電層240圖案化。圖案化形成開口暴露出導電連接器236的一部分。可透過合適的製程來圖案化，例如當介電層240為感光材料時，將介電層240暴露於光線，或例如透過非等向性蝕刻來蝕刻。如果介電層240為感光材料，可在曝光後將介電層240顯影。
在導電連接器236過填充開口的實施例中，可將介電層240用作平坦化重置層。可注意的是，可形成介電層240具有比一般重佈線結構的底部介電層更大的厚度，以便於平坦化。在形成之後，介電層240可具有厚度T2 在約5µm至約15µm的範圍中。在一些實施例中，進行後形成平坦化製程。平坦化製程可包含在介電層240上進行研磨製程或化學機械研磨製程。透過使用介電層240作為平坦化重置層，介電層240的頂表面可大致平坦，且可具有比介電層240的頂表面更高的平坦度。在平坦化之後，可減少介電層240的厚度。介電層240的厚度(例如底部介電層)比第二重佈線結構238的其他介電層(例如介電層252(例如頂部介電層))更厚。
接著，形成金屬圖案242。金屬圖案242包含在介電層240的主表面上並沿介電層208的主表面延伸的導線。金屬圖案242更包含延伸通過介電層240的導通孔，以物理及電性連接至導電連接器236。為了形成金屬圖案242，晶種層形成於介電層240上方以及延伸通過介電層240的開口中。在一些實施例中，晶種層為金屬層，金屬層可為單一層或包括由不同材料形成的複數個子層的複合層。在一些實施例中，晶種層包括鈦層和在鈦層上方的銅層。晶種層可透過使用例如物理氣相沉積或類似方法形成。接著，在晶種層上形成光阻並將光阻圖案化。光阻可透過旋塗或類似方法形成，且可曝光以圖案化。光阻的圖案對應至金屬圖案242。圖案化形成開口通過光阻以暴露出晶種層。接著，導電材料形成於光阻的開口中和晶種層的暴露部分上。導電材料可透過鍍覆(例如電鍍或無電電鍍或類似方法)形成。導電材料可包括金屬，例如銅、鈦、鎢、鋁或類似物。導電材料和下方部分的晶種層的組合形成金屬圖案242。移除光阻和晶種層不形成導電材料於其上的部分。光阻可透過合適的灰化或剝離製程移除，例如使用氧電漿或類似物。當移除光阻之後，例如透過使用合適的蝕刻製程移除晶種層的暴露部分，例如透過濕蝕刻或乾蝕刻。
介電層244沉積於金屬圖案242和介電層240上。介電層244可以相似於介電層240的形成方法形成，且可由與介電層240相同的材料形成。
接著，形成金屬圖案246。金屬圖案246包含在介電層244的主表面上並沿介電層244的主表面延伸的導線。金屬圖案246更包含延伸通過介電層244的導通孔，以物理及電性連接至金屬圖案242。金屬圖案246可以相似於金屬圖案242的形成方法形成，且可由與金屬圖案242相同的材料形成。
介電層248沉積於金屬圖案246和介電層244上。介電層248可以相似於介電層240的形成方法形成，且可由與介電層240相同的材料形成。
接著，形成金屬圖案250。金屬圖案250包含在介電層248的主表面上並沿介電層248的主表面延伸的導線。金屬圖案250更包含延伸通過介電層248的導通孔，以物理及電性連接至金屬圖案246。金屬圖案250可以相似於金屬圖案242的形成方法形成，且可由與金屬圖案242相同的材料形成。
介電層252沉積於金屬圖案250和介電層248上。介電層252可以相似於介電層240的形成方法形成，且可由與介電層240相同的材料形成。
凸塊下金屬層254形成於介電層252上並延伸通過介電層252。作為形成凸塊下金屬層254的範例，可將介電層252圖案化以形成暴露出金屬圖案250的一部分的開口。可透過合適的製程來圖案化，例如當介電層252為感光材料時，將介電層252暴露於光線，或例如透過非等向性蝕刻來蝕刻。如果介電層252為感光材料，可在曝光後將介電層252顯影。用於凸塊下金屬層254的開口比用於金屬圖案242、246和250的導通孔部分的開口更寬。晶種層形成於介電層252上方及開口中。在一些實施例中，晶種層為金屬層，金屬層可為單一層或包括由不同材料形成的複數個子層的複合層。在一些實施例中，晶種層包括鈦層和在鈦層上方的銅層。晶種層可透過使用例如物理氣相沉積或類似方法形成。接著，在晶種層上形成光阻並將光阻圖案化。光阻可透過旋塗或類似方法形成，且可曝光以圖案化。光阻的圖案對應至凸塊下金屬層254。圖案化形成開口通過光阻以暴露出晶種層。導電材料形成於光阻的開口中和晶種層的暴露部分上。導電材料可透過鍍覆(例如電鍍或無電電鍍或類似方法)形成。導電材料可包括金屬，例如銅、鈦、鎢、鋁或類似物。接著，移除光阻和晶種層不形成導電材料於其上的部分。光阻可透過合適的灰化或剝離製程移除，例如使用氧電漿或類似物。當移除光阻之後，例如透過使用合適的蝕刻製程移除晶種層的暴露部分，例如透過濕蝕刻或乾蝕刻。晶種層的剩下部分和導電材料形成凸塊下金屬層254。在形成不同的凸塊下金屬層254的實施例中，可使用更多的光阻和圖案化步驟。
在形成之後，環狀基底100電性連接封裝組件200的各種部件。特別來說，環狀基底100、導電連接器118和導電連接器236將第一重佈線結構206電性及物理連接至第二重佈線結構238。因此，積體電路晶粒224透過第一重佈線結構206和環狀基底100電性連接至第二重佈線結構238。
在第17圖中，進行承載基底去接合以將承載基底202與第一重佈線結構206(例如介電層208)分離(或“去接合”)。在一些實施例中，去接合包含將光線(例如雷射光或紫外光)投射至離型層204，使得離型層204在光的熱量下分解，且可移除承載基底202。接著，將結構翻轉並放置於膠帶上。去接合步驟暴露出第一重佈線結構206的金屬圖案210。
第18圖為依據一些實施例之封裝結構300的剖面示意圖。封裝結構300包含第一封裝體302、積體電路晶粒304和封裝基底306。封裝結構300可被稱為並排多晶片模組(side-by-side multi-chip-module，SBS-MCM)。
積體電路晶粒304可為與積體電路晶粒224相通的晶粒，以形成完整的系統。舉例來說，在積體電路晶粒224為邏輯晶粒的實施例中，積體電路晶粒304為記憶體晶粒、射頻晶粒、被動元件或前述之組合。積體電路晶粒304包含半導體基底，有著例如電晶體、二極體、電容、電阻等的元件形成於半導體基底中及/或半導體基底上。這些元件可透過例如在半導體基底上的一個或多個介電層中的金屬圖案所形成的互連結構來互連，以形成積體電路。積體電路晶粒304更包括接墊308，例如鋁墊，以作外部連接。接墊308在被稱為積體電路晶粒304的相應主動側上，且可在互連結構的最上層中。導電連接器310可形成於接墊308上。導電連接器310可由導電材料形成，例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似物或前述之組合。積體電路晶粒304透過使用導電連接器310堆疊至凸塊下金屬層254。在一些實施例中，將導電連接器310回焊以將積體電路晶粒304附接至凸塊下金屬層254。在一些實施例中，形成底部填充材料或封裝劑，以填充積體電路晶粒304與第二重佈線結構238之間的間隙。由於降低了封裝劑232的使用量，可降低第一封裝體302的厚度，其可接合更大厚度的積體電路晶粒304。舉例來說，當積體電路晶粒304為記憶體元件時，可增加記憶體元件的容量。
接著，第一封裝體302透過使用導電連接器312堆疊至封裝基底306。封裝基底306可由半導體材料製成，例如矽、鍺、鑽石或類似物。或者，也可使用化合物材料，例如矽鍺、碳化矽、砷化鎵、砷化銦、磷化鎵、碳化矽鍺、磷化鎵砷、磷化鎵銦、前述之組合和類似物。此外，封裝基底306可為絕緣層上覆矽(silicon-on-insulator，SOI)基底。一般來說，絕緣層上覆矽基底包含半導體材料層，例如磊晶矽、鍺、矽鍺、絕緣層上覆矽、絕緣層上覆矽鍺(silicon-germanium-on-insulator，SGOI)或前述之組合。在另一實施例中，封裝基底306為以絕緣核心為基底，例如玻璃纖維強化樹脂核心。範例的核心材料為玻璃纖維樹脂，例如FR4。核心材料的替代品包含雙馬來醯亞胺-三嗪(bismaleimide-triazine，BT)樹脂或其他印刷電路板材料或薄膜。可使用例如味之素增層膜(Ajinomoto Build-up film，ABF)或其他層疊物的增層膜作為封裝基底306。
封裝基底306可包含主動元件和被動元件(未顯示)。本發明所屬技術領域中具通常知識者將理解，可使用廣泛的各種元件(例如電晶體、電容、電阻、前述之組合和類似物)來產生所設計的封裝結構300的結構和功能需求。這些元件可透過使用合適的方法形成。
封裝基底306也可包含金屬層和導通孔(未顯示)，且接合墊314在金屬層和導通孔上方。金屬層可形成於設計的主動元件和被動元件上方，以連接各種元件來形成功能電路。金屬層可由介電質(例如低介電常數介電材料)和導電材料(例如銅)的交錯層形成，導通孔將導電材料層互連，且可透過合適的製程(例如沉積、鑲嵌、雙鑲嵌或類似方法)形成。在一些實施例中，封裝基底306大致沒有主動元件或被動元件。
導電連接器312可由導電材料形成，例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似物或前述之組合。在一些實施例中，將導電連接器312回焊以將第一封裝體302附接至接合墊314。導電連接器312將封裝基底306(包含封裝基底306中的金屬層)電性及/或物理耦接至第一封裝體302的金屬圖案210。在一些實施例中，在堆疊於封裝基底306上之前，可將被動元件(例如表面安裝元件(surface mount devices，SMDs)，未顯示)附接至第一封裝體302(例如接合至接合墊314)。在這些實施例中，被動元件可接合至與接合導電連接器312相同之第一封裝體302的表面。
在導電連接器312以剩下的至少一些環氧助焊劑的環氧樹脂部分回焊之前以及在第一封裝體302附接至封裝基底306之後，導電連接器312可具有環氧助焊劑(未顯示)形成於其上。環氧樹脂部分可作為底部填充材料來降低應力並保護將導電連接器312回焊時的接點。在一些實施例中，底部填充材料(未顯示)可形成於第一封裝體302與封裝基底306之間並圍繞導電連接器312。底部填充材料可在附接第一封裝體302之後以毛細流動製程形成，或可在附接第一封裝體302之前以合適的沉積方法形成。
第19圖為依據一些其他實施例之封裝結構300的剖面示意圖。在所示的實施例中，底部填充材料230也形成圍繞導電連接器118的子集。如此一來，可保護一些導電連接器118免受機械力影響。
第20圖為依據一些其他實施例之封裝結構300的剖面示意圖。在所示的實施例中，底部填充材料230也形成圍繞所有的導電連接器118。如此一來，可保護所有的導電連接器118免受機械力影響。
本發明實施例可達成許多優點。環狀基底100為剛性。相較於在第一重佈線結構206上直接形成導通孔，透過使用含有導通孔108的環狀基底100，可增加封裝組件的垂直支撐力。再者，透過將環狀基底100焊接至第一重佈線結構206，可避免第一重佈線結構206的導通孔剝離。
在一實施例中，封裝體包含:第一重佈線結構；第一積體電路晶粒連接至第一重佈線結構；環狀基底圍繞第一積體電路晶粒，環狀基底連接至第一重佈線結構，環狀基底包含核心及延伸通過核心的導通孔；封裝劑圍繞環狀基底和第一積體電路晶粒，封裝劑延伸通過環狀基底；以及第二重佈線結構在封裝劑上，第二重佈線結構透過環狀基底的導通孔連接至第一重佈線結構。
在一些實施例中，封裝體更包含:複數個第一導電連接器延伸通過封裝劑的第一部分，第一導電連接器將第一積體電路晶粒連接至第一重佈線結構；以及複數個第二導電連接器延伸通過封裝劑一第二部分，第二導電連接器將環狀基底連接至第一重佈線結構，第二導電連接器的尺寸不同於第一導電連接器的尺寸。在一些實施例中，封裝體更包含:底部填充材料設置於第一積體電路晶粒與第一重佈線結構之間，底部填充材料圍繞第一導電連接器。在封裝體的一些實施例中，底部填充材料更圍繞第二導電連接器的第一子集而不圍繞第二導電連接器的第二子集。在封裝體的一些實施例中，底部填充材料更圍繞所有的第二導電連接器。在封裝體的一些實施例中，第一導電連接器和第二導電連接器包含銅柱。在封裝體的一些實施例中，第一導電連接器和第二導電連接器包含焊料連接器。在一些實施例中，封裝體更包含:複數個第三導電連接器延伸通過封裝劑的第三部分，第三導電連接器將環狀基底連接至第二重佈線結構。在封裝體的一些實施例中，第三導電連接器包含導電膏。在封裝體的一些實施例中，第二重佈線結構包含底部介電層和頂部介電層，底部介電層接觸第三導電連接器和封裝劑，底部介電層的頂表面具有比底部介電層的底表面更高的平坦度，底部介電層比頂部介電層更厚。在封裝體的一些實施例中，環狀基底更包含:第一導線在環狀基底的第一側上，第一導線將導通孔連接至第一重佈線結構；第一防焊層在第一導線上，第一防焊層圍繞第一導電連接器；第二導線在環狀基底的第二側上，第二導線將導通孔連接至第二重佈線結構；以及第二防焊層在第二導線上，第二防焊層圍繞第三導電連接器。在封裝體的一些實施例中，第一積體電路晶粒的第一高度大於環狀基底的第二高度。在一些實施例中，封裝體更包含:第二積體電路晶粒連接至第二重佈線結構；以及封裝基底連接至第一重佈線結構。在封裝體的一些實施例中，核心包含預浸漬複合纖維。
在一實施例中，封裝體的形成方法包含:將基底圖案化以形成第一開口；在第一開口中形成導通孔；形成第一導電連接器連接至導通孔，第一導電連接器在基底的第一側上；將基底圖案化以形成空腔；將基底放置在第一重佈線結構上，第一導電連接器耦接至第一重佈線結構；將積體電路晶粒放置於第一重佈線結構上並在基底的空腔中，積體電路晶粒包含耦接至第一重佈線結構的第二導電連接器；以封裝劑封裝積體電路晶粒和基底；以及在封裝劑上形成第二重佈線結構，第二重佈線結構透過基底的導通孔連接至第一重佈線結構。
在一些實施例中，此方法更包含:將第一導電連接器和第二導電連接器回焊，以將基底和積體電路晶粒同時接合至第一重佈線結構。在一些實施例中，此方法更包含:在封裝劑中形成第二開口；以及在第二開口中配置導電膏。在此方法的一些實施例中，形成第二重佈線結構的步驟包含:在導電膏和封裝劑上形成底部介電層；將底部介電層平坦化；以及形成金屬圖案沿底部介電層延伸並通過底部介電層。
在一實施例中，封裝體的形成方法包含:將環狀基底連接至第一重佈線結構，環狀基底包含:核心具有空腔；第一導通孔延伸通過核心；及導線在核心上，導線連接至第一導通孔；將第一積體電路晶粒連接至第一重佈線結構，第一積體電路晶粒設置於環狀基底的空腔中；以封裝劑封裝環狀基底和第一積體電路晶粒；以及在封裝劑上形成第二重佈線結構，第二重佈線結構透過環狀基底的第一導通孔和導線連接至第一重佈線結構。
在一些實施例中，此方法更包含:將封裝劑圖案化以形成暴露出環狀基底的導線的開口；以及以導電膏填充開口以形成第二導通孔，第二重佈線結構連接至第二導通孔。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更加了解本發明實施例。本技術領域中具有通常知識者應可理解，且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本發明的發明精神與範圍。在不背離本發明的發明精神與範圍之前提下，可對本發明實施例進行各種改變、置換或修改。
100:環狀基底 102:基底核心 104:晶種層 106、114、234:開口 108:導通孔 110:導線 112:防焊層 116:保護層 118、228、236、310、312:導電連接器 120:空腔 200:封裝組件 202:承載基底 204:離型層 206:第一重佈線結構 206A:第一區 206B:第二區 208、212、216、220、240、244、248、252:介電層 210、214、218、242、246、250:金屬圖案 222、254:凸塊下金屬層 224、304:積體電路晶粒 226、308:接墊 230:底部填充材料 232:封裝劑 238:第二重佈線結構 300:封裝結構 302:第一封裝體 306:封裝基底 314:接合墊 H1、H2、H3:高度 T1、T2:厚度 W1:第一寬度 W2:第二寬度 W3:上部寬度 W4:下部寬度
根據以下的詳細說明並配合所附圖式可以更加理解本發明實施例。應注意的是，根據本產業的標準慣例，圖示中的各種部件(feature)並未必按照比例繪製。事實上，可能任意的放大或縮小各種部件的尺寸，以做清楚的說明。 第1至6圖、第7A至7B圖為依據一些實施例之形成環狀基底的製程的中間步驟的剖面示意圖。 第8-17圖為依據一些實施例之將環狀基底與其他元件封裝以形成封裝組件的製程的中間步驟的剖面示意圖。 第18圖為依據一些實施例之封裝結構的剖面示意圖。 第19圖為依據一些其他實施例之封裝結構的剖面示意圖。 第20圖為依據一些其他實施例之封裝結構的剖面示意圖。
118、228、236、310、312:導電連接器
208:介電層
210:金屬圖案
222、254:凸塊下金屬層
224、304:積體電路晶粒
226、308:接墊
230:底部填充材料
232:封裝劑
238:第二重佈線結構
300:封裝結構
302:第一封裝體
306:封裝基底
314:接合墊

Claims (20)

  1. 一種封裝體，包括: 一第一重佈線結構； 一第一積體電路晶粒，連接至該第一重佈線結構； 一環狀基底，圍繞該第一積體電路晶粒，該環狀基底連接至該第一重佈線結構，該環狀基底包括一核心及延伸通過該核心的一導通孔； 一封裝劑，圍繞該環狀基底和該第一積體電路晶粒，該封裝劑延伸通過該環狀基底；以及 一第二重佈線結構，在該封裝劑上，該第二重佈線結構透過該環狀基底的該導通孔連接至該第一重佈線結構。
  2. 如申請專利範圍第1項所述之封裝體，更包括: 複數個第一導電連接器，延伸通過該封裝劑的一第一部分，該複數個第一導電連接器將該第一積體電路晶粒連接至該第一重佈線結構；以及 複數個第二導電連接器，延伸通過該封裝劑的一第二部分，該複數個第二導電連接器將該環狀基底連接至該第一重佈線結構，該複數個第二導電連接器的尺寸不同於該複數個第一導電連接器的尺寸。
  3. 如申請專利範圍第2項所述之封裝體，更包括: 一底部填充材料，設置於該第一積體電路晶粒與該第一重佈線結構之間，該底部填充材料圍繞該複數個第一導電連接器。
  4. 如申請專利範圍第3項所述之封裝體，其中該底部填充材料更圍繞該複數個第二導電連接器的一第一子集而不圍繞該複數個第二導電連接器的一第二子集。
  5. 如申請專利範圍第3項所述之封裝體，其中該底部填充材料更圍繞所有的該複數個第二導電連接器。
  6. 如申請專利範圍第2項所述之封裝體，其中該複數個第一導電連接器和該複數個第二導電連接器包括銅柱。
  7. 如申請專利範圍第2項所述之封裝體，其中該複數個第一導電連接器和該複數個第二導電連接器包括焊料連接器。
  8. 如申請專利範圍第2項所述之封裝體，更包括: 複數個第三導電連接器，延伸通過該封裝劑的一第三部分，該複數個第三導電連接器將該環狀基底連接至該第二重佈線結構。
  9. 如申請專利範圍第8項所述之封裝體，其中該複數個第三導電連接器包括導電膏。
  10. 如申請專利範圍第8項所述之封裝體，其中該第二重佈線結構包括一底部介電層和一頂部介電層，該底部介電層接觸該複數個第三導電連接器和該封裝劑，該底部介電層的頂表面具有比該底部介電層的底表面更高的平坦度，該底部介電層比該頂部介電層更厚。
  11. 如申請專利範圍第8項所述之封裝體，其中該環狀基底更包括: 一第一導線，在該環狀基底的一第一側上，該第一導線將該導通孔連接至該第一重佈線結構； 一第一防焊層，在該第一導線上，該第一防焊層圍繞該複數個第一導電連接器； 一第二導線，在該環狀基底的一第二側上，該第二導線將該導通孔連接至該第二重佈線結構；以及 一第二防焊層，在該第二導線上，該第二防焊層圍繞該複數個第三導電連接器。
  12. 如申請專利範圍第1項所述之封裝體，其中該第一積體電路晶粒的一第一高度大於該環狀基底的一第二高度。
  13. 如申請專利範圍第1項所述之封裝體，更包括: 一第二積體電路晶粒，連接至該第二重佈線結構；以及 一封裝基底，連接至該第一重佈線結構。
  14. 如申請專利範圍第1項所述之封裝體，其中該核心包括一預浸漬複合纖維。
  15. 一種封裝體的形成方法，包括: 將一基底圖案化以形成一第一開口； 在該第一開口中形成一導通孔； 形成一第一導電連接器連接至該導通孔，該第一導電連接器在該基底的一第一側上； 將該基底圖案化以形成一空腔； 將該基底放置在一第一重佈線結構上，該第一導電連接器耦接至該第一重佈線結構； 將一積體電路晶粒放置於該第一重佈線結構上並在該基底的該空腔中，該積體電路晶粒包括耦接至該第一重佈線結構的一第二導電連接器； 以一封裝劑封裝該積體電路晶粒和該基底；以及 在該封裝劑上形成一第二重佈線結構，該第二重佈線結構透過該基底的該導通孔連接至該第一重佈線結構。
  16. 如申請專利範圍第15項所述之封裝體的形成方法，更包括: 將該第一導電連接器和該第二導電連接器回焊，以將該基底和該積體電路晶粒同時接合至該第一重佈線結構。
  17. 如申請專利範圍第15項所述之封裝體的形成方法，更包括: 在該封裝劑中形成一第二開口；以及 在該第二開口中配置一導電膏。
  18. 如申請專利範圍第17項所述之封裝體的形成方法，其中形成該第二重佈線結構的步驟包括: 在該導電膏和該封裝劑上形成一底部介電層； 將該底部介電層平坦化；以及 形成一金屬圖案沿該底部介電層延伸並通過該底部介電層。
  19. 一種封裝體的形成方法，包括: 將一環狀基底連接至一第一重佈線結構，該環狀基底包括: 一核心，具有一空腔； 一第一導通孔，延伸通過該核心；及 一導線，在該核心上，該導線連接至該第一導通孔； 將一第一積體電路晶粒連接至該第一重佈線結構，該第一積體電路晶粒設置於該環狀基底的該空腔中； 以一封裝劑封裝該環狀基底和該第一積體電路晶粒；以及 在該封裝劑上形成一第二重佈線結構，該第二重佈線結構透過該環狀基底的該第一導通孔和該導線連接至該第一重佈線結構。
  20. 如申請專利範圍第19項所述之封裝體的形成方法，更包括: 將該封裝劑圖案化以形成暴露出該環狀基底的該導線的一開口；以及 以一導電膏填充該開口以形成一第二導通孔，該第二重佈線結構連接至該第二導通孔。
TW108133988A 2018-09-27 2019-09-20 封裝體及其形成方法 TWI720624B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862737246P 2018-09-27 2018-09-27
US62/737,246 2018-09-27
US16/207,850 2018-12-03
US16/207,850 US10790162B2 (en) 2018-09-27 2018-12-03 Integrated circuit package and method

Publications (2)

Publication Number Publication Date
TW202015137A true TW202015137A (zh) 2020-04-16
TWI720624B TWI720624B (zh) 2021-03-01

Family

ID=69946075

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108133988A TWI720624B (zh) 2018-09-27 2019-09-20 封裝體及其形成方法

Country Status (4)

Country Link
US (2) US10790162B2 (zh)
KR (1) KR102324012B1 (zh)
CN (1) CN110957281B (zh)
TW (1) TWI720624B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI789804B (zh) * 2020-08-06 2023-01-11 力成科技股份有限公司 封裝結構及其製造方法
US11916035B2 (en) 2020-08-06 2024-02-27 Powertech Technology Inc. Package structure and manufacturing method thereof

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102568705B1 (ko) 2018-10-05 2023-08-22 삼성전자주식회사 반도체 패키지, 반도체 패키지 제조방법 및 재배선 구조체 제조방법
KR102540829B1 (ko) * 2018-10-05 2023-06-08 삼성전자주식회사 반도체 패키지, 반도체 패키지 제조방법 및 재배선 구조체 제조방법
US10903169B2 (en) * 2019-04-30 2021-01-26 Advanced Semiconductor Engineering, Inc. Conductive structure and wiring structure including the same
US11600567B2 (en) * 2019-07-31 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for manufacturing the same
USD920266S1 (en) * 2019-09-29 2021-05-25 China Chippacking Technology Co., Ltd. Integrated circuit package
USD920265S1 (en) * 2019-09-29 2021-05-25 China Chippacking Technology Co., Ltd. Integrated circuit package
DE102019132314B4 (de) * 2019-11-28 2022-03-03 Infineon Technologies Ag Package mit Einkapselung unter Kompressionsbelastung
CN113035801A (zh) * 2019-12-25 2021-06-25 台湾积体电路制造股份有限公司 存储器装置及其制造方法
KR20210087299A (ko) * 2020-01-02 2021-07-12 삼성전기주식회사 고주파 모듈 및 이를 포함하는 전자기기
KR20210104364A (ko) 2020-02-17 2021-08-25 삼성전자주식회사 반도체 패키지
US11735538B2 (en) * 2020-02-17 2023-08-22 Wolfspeed, Inc. Semiconductor having a backside wafer cavity for radio frequency (RF) passive device integration and/or improved cooling and process of implementing the same
US11264359B2 (en) 2020-04-27 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Chip bonded to a redistribution structure with curved conductive lines
US11508665B2 (en) * 2020-06-23 2022-11-22 Taiwan Semiconductor Manufacturing Co., Ltd. Packages with thick RDLs and thin RDLs stacked alternatingly
US11444069B2 (en) * 2020-06-29 2022-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. 3D semiconductor package including memory array
US11670601B2 (en) 2020-07-17 2023-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Stacking via structures for stress reduction
US20220037243A1 (en) * 2020-07-31 2022-02-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method
US11991824B2 (en) * 2020-08-28 2024-05-21 Unimicron Technology Corp. Circuit board structure and manufacturing method thereof
US11540396B2 (en) * 2020-08-28 2022-12-27 Unimicron Technology Corp. Circuit board structure and manufacturing method thereof
KR20220042705A (ko) * 2020-09-28 2022-04-05 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
US11894243B2 (en) * 2020-11-20 2024-02-06 Sj Semiconductor (Jiangyin) Corporation Wafer system-level fan-out packaging structure and manufacturing method

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101037229B1 (ko) * 2006-04-27 2011-05-25 스미토모 베이클리트 컴퍼니 리미티드 반도체 장치 및 반도체 장치의 제조 방법
TWI366896B (en) * 2006-11-30 2012-06-21 Carrier structure embedded with chip and method for fabricating thereof
US7989950B2 (en) * 2008-08-14 2011-08-02 Stats Chippac Ltd. Integrated circuit packaging system having a cavity
JP2010114434A (ja) 2008-10-08 2010-05-20 Ngk Spark Plug Co Ltd 部品内蔵配線基板及びその製造方法
US20110024899A1 (en) * 2009-07-28 2011-02-03 Kenji Masumoto Substrate structure for cavity package
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US20130249101A1 (en) * 2012-03-23 2013-09-26 Stats Chippac, Ltd. Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
JP5993248B2 (ja) * 2012-08-27 2016-09-14 新光電気工業株式会社 電子部品内蔵基板及びその製造方法
JP6152254B2 (ja) * 2012-09-12 2017-06-21 新光電気工業株式会社 半導体パッケージ、半導体装置及び半導体パッケージの製造方法
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
JP6200178B2 (ja) * 2013-03-28 2017-09-20 新光電気工業株式会社 電子部品内蔵基板及びその製造方法
JP6173781B2 (ja) * 2013-06-10 2017-08-02 新光電気工業株式会社 配線基板及び配線基板の製造方法
US8980691B2 (en) * 2013-06-28 2015-03-17 Stats Chippac, Ltd. Semiconductor device and method of forming low profile 3D fan-out package
KR101550496B1 (ko) * 2013-07-24 2015-09-04 에스티에스반도체통신 주식회사 적층형 반도체패키지 및 그 제조방법
KR101514539B1 (ko) * 2013-08-29 2015-04-22 삼성전기주식회사 전자부품 내장기판
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US10121768B2 (en) * 2015-05-27 2018-11-06 Bridge Semiconductor Corporation Thermally enhanced face-to-face semiconductor assembly with built-in heat spreader and method of making the same
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
KR102165024B1 (ko) * 2014-09-26 2020-10-13 인텔 코포레이션 와이어-접합 멀티-다이 스택을 구비한 집적 회로 패키지
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
KR20160132751A (ko) * 2015-05-11 2016-11-21 삼성전기주식회사 전자부품 패키지 및 그 제조방법
US10199337B2 (en) * 2015-05-11 2019-02-05 Samsung Electro-Mechanics Co., Ltd. Electronic component package and method of manufacturing the same
US10109588B2 (en) 2015-05-15 2018-10-23 Samsung Electro-Mechanics Co., Ltd. Electronic component package and package-on-package structure including the same
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
KR102450576B1 (ko) * 2016-01-22 2022-10-07 삼성전자주식회사 전자 부품 패키지 및 그 제조방법
US10818621B2 (en) * 2016-03-25 2020-10-27 Samsung Electronics Co., Ltd. Fan-out semiconductor package
JP2017195261A (ja) * 2016-04-20 2017-10-26 イビデン株式会社 インターポーザ及びインターポーザの製造方法
US10068855B2 (en) 2016-09-12 2018-09-04 Samsung Electro-Mechanics Co., Ltd. Semiconductor package, method of manufacturing the same, and electronic device module
US10026681B2 (en) * 2016-09-21 2018-07-17 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
KR101952864B1 (ko) * 2016-09-30 2019-02-27 삼성전기주식회사 팬-아웃 반도체 패키지
KR101939046B1 (ko) * 2017-10-31 2019-01-16 삼성전기 주식회사 팬-아웃 반도체 패키지
KR101942746B1 (ko) * 2017-11-29 2019-01-28 삼성전기 주식회사 팬-아웃 반도체 패키지
KR101912290B1 (ko) * 2017-12-06 2018-10-29 삼성전기 주식회사 팬-아웃 반도체 패키지

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI789804B (zh) * 2020-08-06 2023-01-11 力成科技股份有限公司 封裝結構及其製造方法
US11916035B2 (en) 2020-08-06 2024-02-27 Powertech Technology Inc. Package structure and manufacturing method thereof

Also Published As

Publication number Publication date
US11527474B2 (en) 2022-12-13
US20210013053A1 (en) 2021-01-14
TWI720624B (zh) 2021-03-01
KR102324012B1 (ko) 2021-11-10
CN110957281B (zh) 2023-06-30
US10790162B2 (en) 2020-09-29
KR20200036771A (ko) 2020-04-07
US20200105663A1 (en) 2020-04-02
CN110957281A (zh) 2020-04-03

Similar Documents

Publication Publication Date Title
TWI720624B (zh) 封裝體及其形成方法
US11721559B2 (en) Integrated circuit package pad and methods of forming
TWI683378B (zh) 半導體封裝及其製造方法
CN109786266B (zh) 半导体封装件及其形成方法
TWI727463B (zh) 封裝體及其形成方法
US10163802B2 (en) Fan-out package having a main die and a dummy die, and method of forming
TWI683410B (zh) 半導體封裝及其形成方法
CN108987380B (zh) 半导体封装件中的导电通孔及其形成方法
US9082636B2 (en) Packaging methods and structures for semiconductor devices
CN110660753B (zh) 半导体封装件和方法
TWI697085B (zh) 半導體元件及其形成方法
US11145614B2 (en) Semiconductor device and method of manufacture
KR102295360B1 (ko) 집적형 팬아웃 패키지 및 그를 형성하는 방법
KR102331050B1 (ko) 반도체 패키지 및 그 형성 방법
TW202133376A (zh) 半導體封裝及其製造方法
CN113140516A (zh) 封装件及其形成方法
TW202008481A (zh) 形成半導體封裝體的方法
KR102379087B1 (ko) 반도체 디바이스 및 제조 방법
US20230105359A1 (en) Integrated Circuit Packages