JP6227803B2 - 銅合金導電性経路構造体を備えるマイクロ電子基板 - Google Patents
銅合金導電性経路構造体を備えるマイクロ電子基板 Download PDFInfo
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Description
Claims (17)
- 少なくとも1つの誘電体層と、
前記誘電体層に隣接する第1面、及び、反対側の第2面、を有する少なくとも1つの銅合金導電性経路と、
を備え、
前記少なくとも1つの銅合金導電性経路は、銅と、タングステン、モリブデン、またはそれらの組み合わせの合金化金属と、を含み、
前記少なくとも1つの銅合金導電性経路は、少なくとも1つの傾斜銅合金導電性経路を含み、
前記少なくとも1つの傾斜銅合金導電性経路の銅は、傾斜銅合金層の第1面と第2面とのうちの一方と前記傾斜銅合金層の前記第1面と前記第2面とのうちの他方との間で実質的線形濃度傾斜度を有する、
マイクロ電子基板。 - 前記少なくとも1つの傾斜銅合金導電性経路は、前記傾斜銅合金層の前記第1面と前記傾斜銅合金層の前記第2面とのうちの一方に近接する約90%から100%の間の銅と前記傾斜銅合金層の前記第1面と前記傾斜銅合金層の前記第2面とのうちの他方に近接する約0%から10%の間の銅とを含む
請求項1に記載のマイクロ電子基板。 - 前記少なくとも1つの銅合金導電性経路は、共堆積金属をさらに含む、
請求項1に記載のマイクロ電子基板。 - 前記共堆積金属は、ニッケル、コバルト、鉄、またはそれらの組み合わせを含む、
請求項3に記載のマイクロ電子基板。 - 前記少なくとも1つの傾斜銅合金導電性経路は、前記傾斜銅合金層の前記第1面と前記傾斜銅合金層の前記第2面とのうちの一方に近接する約90%から100%の間の銅と、前記傾斜銅合金層の前記第1面と前記傾斜銅合金層の前記第2面とのうちの他方に近接する約0%から10%の間の銅とを含む、
請求項3に記載のマイクロ電子基板。 - 前記少なくとも1つの傾斜銅合金導電性経路は、前記傾斜銅合金層の前記第1面と前記傾斜銅合金層の前記第2面とのうちの一方に近接する約90%から100%の間の濃度の銅を含み、残りは前記合金化金属及び約複数の微量レベルから10%の間の濃度を有する前記共堆積金属であり、前記傾斜銅合金層の前記第1面と前記傾斜銅合金層の前記第2面とのうちの他方に近接する約0%から10%の間の濃度の銅を含み、残りは前記合金化金属及び約複数の微量レベルから10%の間の濃度を有する前記共堆積金属である、
請求項3に記載のマイクロ電子基板。 - 第1面を有する誘電体層を形成する段階と、
前記誘電体層の前記第1面上に金属被膜層を形成する段階と、
前記金属被膜層を電着溶液に接触させる段階と、
前記電着溶液と前記誘電体層との間の電位を誘導することによって、前記金属被膜層から銅合金層を形成する段階と、
を備える
マイクロ電子基板を製造する方法であって、
前記銅合金層は、銅と、タングステン、モリブデン、またはそれらの組み合わせの合金化金属と、ニッケル、コバルト、鉄、またはそれらの組み合わせの共堆積金属と、を含み、
前記銅合金層は、前記誘電体層に隣接する第1面、及び、反対側の第2面と、を含み、
前記電着溶液と前記誘電体層との間の電位を誘導することによって前記誘電体層の前記第1面上に銅合金層を形成する前記段階は、前記電着溶液と前記誘電体層との間の前記電位を変化させることによって傾斜銅合金層を形成する段階を含む、
マイクロ電子基板を製造する方法。 - 前記傾斜銅合金層を形成する前記段階は、前記傾斜銅合金層の第1面と前記傾斜銅合金層の第2面とのうちの一方に近接する約90%から100%の間の銅と、前記傾斜銅合金層の前記第1面と前記傾斜銅合金層の前記第2面とのうちの他方に近接する約0%から10%の間の銅と、を含む前記傾斜銅合金層を形成する段階を含む、
請求項7に記載の方法。 - 前記傾斜銅合金層を形成する前記段階は、前記傾斜銅合金層の前記第1面と前記傾斜銅合金層の前記第2面とのうちの一方に近接する約90%から100%の間の濃度の銅を含み、残りは前記合金化金属及び約複数の微量レベルから10%の間の濃度を有する共堆積金属であり、前記傾斜銅合金層の前記第1面と前記傾斜銅合金層の前記第2面とのうちの他方に近接する約0%から10%の間の濃度の銅を含み、残りは前記合金化金属及び約複数の微量レベルから10%の間の濃度を有する共堆積金属を含む前記傾斜銅合金層を形成する段階を含む、
請求項7に記載の方法。 - 少なくとも1つの傾斜銅合金導電性経路を形成する前記傾斜銅合金層をエッチングする段階、
をさらに備える
請求項7に記載の方法。 - 前記傾斜銅合金層の前記銅は、実質的線形濃度傾斜度を有する、
請求項7から10の何れか一項に記載の方法。 - ボードと、
前記ボードに取り付けられるマイクロ電子コンポーネントと、
を備え、
前記マイクロ電子コンポーネントは、少なくとも1つの誘電体層と、前記誘電体層に隣接する第1面及び反対側の第2面を含む少なくとも1つの銅合金導電性経路と、を含むマイクロ電子基板を有し、
前記少なくとも1つの銅合金導電性経路は、銅と、タングステン、モリブデン、またはそれらの組み合わせの合金化金属とを含み、
前記少なくとも1つの銅合金導電性経路は、少なくとも1つの傾斜銅合金導電性経路を含み、
前記少なくとも1つの傾斜銅合金導電性経路の銅は、傾斜銅合金層の第1面と第2面とのうちの一方と前記傾斜銅合金層の前記第1面と前記第2面とのうちの他方との間で実質的線形濃度傾斜度を有する、
コンピューティングデバイス。 - 前記少なくとも1つの傾斜銅合金導電性経路は、前記傾斜銅合金層の前記第1面と前記傾斜銅合金層の前記第2面とのうちの一方に近接する約90%から100%の間の銅を含み、前記傾斜銅合金層の前記第1面と前記傾斜銅合金層の前記第2面とのうちの他方に近接する約0%から10%の間の銅を含む、
請求項12に記載のコンピューティングデバイス。 - 前記少なくとも1つの銅合金導電性経路は、共堆積金属をさらに含む、
請求項12に記載のコンピューティングデバイス。 - 前記共堆積金属は、ニッケル、コバルト、鉄、またはそれらの組み合わせを含む、
請求項14に記載のコンピューティングデバイス。 - 前記少なくとも1つの傾斜銅合金導電性経路は、前記傾斜銅合金層の前記第1面と前記傾斜銅合金層の前記第2面とのうちの一方に近接する約90%から100%の間の銅を含み、前記傾斜銅合金層の前記第1面と前記傾斜銅合金層の前記第2面とのうちの他方に近接する約0%から10%の間の銅を含む、
請求項14に記載のコンピューティングデバイス。 - 前記少なくとも1つの傾斜銅合金導電性経路は、前記傾斜銅合金層の前記第1面と前記傾斜銅合金層の前記第2面とのうちの一方に近接する約90%から100%の間の濃度の銅を含み、残りは前記合金化金属及び約微量レベルから10%の間の濃度を有する前記共堆積金属であり、前記傾斜銅合金層の前記第1面と前記傾斜銅合金層の前記第2面とのうちの他方に近接する約0%から10%の間の濃度の銅を含み、残りは前記合金化金属と約微量レベルから10%の間の濃度を有する前記共堆積金属である、
請求項14に記載のコンピューティングデバイス。
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Publication number | Priority date | Publication date | Assignee | Title |
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TWI678772B (zh) * | 2017-04-28 | 2019-12-01 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
US20200066830A1 (en) * | 2018-08-21 | 2020-02-27 | Intel Corporation | Magnetic core inductors on package substrates |
Family Cites Families (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57837A (en) | 1980-06-03 | 1982-01-05 | Jeol Ltd | Spliter for liquid chromatograph mass spectrometer |
JP3286651B2 (ja) * | 1993-12-27 | 2002-05-27 | 株式会社住友金属エレクトロデバイス | セラミック多層配線基板およびその製造法並びにセラミック多層配線基板用導電材料 |
EP0751567B1 (en) | 1995-06-27 | 2007-11-28 | International Business Machines Corporation | Copper alloys for chip interconnections and method of making |
JP3570837B2 (ja) | 1997-01-21 | 2004-09-29 | 京セラ株式会社 | 半導体素子収納用パッケージ |
US6329065B1 (en) * | 1998-08-31 | 2001-12-11 | Kyocera Corporation | Wire board and method of producing the same |
US6441492B1 (en) * | 1999-09-10 | 2002-08-27 | James A. Cunningham | Diffusion barriers for copper interconnect systems |
JP4592936B2 (ja) | 2000-12-05 | 2010-12-08 | Jx日鉱日石金属株式会社 | 電子回路用銅箔及び電子回路の形成方法 |
US6555906B2 (en) * | 2000-12-15 | 2003-04-29 | Intel Corporation | Microelectronic package having a bumpless laminated interconnection layer |
US6447933B1 (en) * | 2001-04-30 | 2002-09-10 | Advanced Micro Devices, Inc. | Formation of alloy material using alternating depositions of alloy doping element and bulk material |
JP2003064451A (ja) * | 2001-06-11 | 2003-03-05 | Hitachi Ltd | 複合傾斜合金板とその製造方法およびこの複合傾斜合金板を用いたシャドウマスクを備えたカラー陰極線管 |
JP2003011273A (ja) * | 2001-07-02 | 2003-01-15 | Mitsubishi Shindoh Co Ltd | 金属化ポリイミドフィルム |
JP2003037204A (ja) * | 2001-07-25 | 2003-02-07 | Kyocera Corp | 半導体素子収納用パッケージ |
US6812143B2 (en) * | 2002-04-26 | 2004-11-02 | International Business Machines Corporation | Process of forming copper structures |
JP4077770B2 (ja) | 2003-06-26 | 2008-04-23 | 京セラ株式会社 | 半導体素子収納用パッケージおよびこれを用いた半導体装置 |
JP2005044832A (ja) * | 2003-07-22 | 2005-02-17 | Toshiba Corp | セラミックス回路基板 |
US7948069B2 (en) * | 2004-01-28 | 2011-05-24 | International Rectifier Corporation | Surface mountable hermetically sealed package |
US7416789B2 (en) | 2004-11-01 | 2008-08-26 | H.C. Starck Inc. | Refractory metal substrate with improved thermal conductivity |
TWI242290B (en) * | 2004-11-22 | 2005-10-21 | Au Optronics Corp | Fabrication method of thin film transistor |
KR100610275B1 (ko) * | 2004-12-16 | 2006-08-09 | 알티전자 주식회사 | 고출력 발광 다이오드 패키지 및 그 제조방법 |
US7579274B2 (en) * | 2006-02-21 | 2009-08-25 | Alchimer | Method and compositions for direct copper plating and filing to form interconnects in the fabrication of semiconductor devices |
US20080223287A1 (en) * | 2007-03-15 | 2008-09-18 | Lavoie Adrien R | Plasma enhanced ALD process for copper alloy seed layers |
DE102007015502A1 (de) * | 2007-03-30 | 2008-10-02 | Advanced Micro Devices, Inc., Sunnyvale | CMP-System mit einem Wirbelstromsensor mit geringerer Höhe |
JP2009076694A (ja) * | 2007-09-20 | 2009-04-09 | Panasonic Corp | 窒化物半導体装置およびその製造方法 |
JP5084668B2 (ja) * | 2008-08-28 | 2012-11-28 | 京セラ株式会社 | プローブカード用配線基板およびこれを用いたプローブカード |
US7951708B2 (en) * | 2009-06-03 | 2011-05-31 | International Business Machines Corporation | Copper interconnect structure with amorphous tantalum iridium diffusion barrier |
MY154122A (en) | 2010-01-15 | 2015-05-15 | Jx Nippon Mining & Metals Corp | Electronic circuit, method for forming same, and copper clad laminate for forming electronic circuit |
US8304913B2 (en) * | 2010-09-24 | 2012-11-06 | Intel Corporation | Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby |
KR101230262B1 (ko) * | 2010-10-12 | 2013-02-06 | 국방과학연구소 | 경사기능층을 가지는 텅스텐-구리 합금의 제조방법 |
WO2012101876A1 (ja) * | 2011-01-26 | 2012-08-02 | 三菱電機株式会社 | 透明電極基板およびその製造方法、光電変換装置およびその製造方法、光電変換モジュール |
JP5677585B2 (ja) * | 2011-10-28 | 2015-02-25 | 京セラ株式会社 | 回路基板およびこれを備える電子装置 |
US9024205B2 (en) * | 2012-12-03 | 2015-05-05 | Invensas Corporation | Advanced device assembly structures and methods |
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