US6441492B1 - Diffusion barriers for copper interconnect systems - Google Patents

Diffusion barriers for copper interconnect systems Download PDF

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US6441492B1
US6441492B1 US09672473 US67247300A US6441492B1 US 6441492 B1 US6441492 B1 US 6441492B1 US 09672473 US09672473 US 09672473 US 67247300 A US67247300 A US 67247300A US 6441492 B1 US6441492 B1 US 6441492B1
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    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
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    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
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    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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    • H01L21/76867Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
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    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
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    • H01L23/5226Via connections in a multilevel interconnection structure
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    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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Abstract

An integrated circuit includes a substrate, at least one dielectric layer adjacent the substrate, and an interconnect structure in the at least one dielectric layer and comprising a copper portion and a barrier layer between the copper portion and adjacent portions of the at least one dielectric layer. Moreover, the barrier layer preferably comprises at least one of rhodium, ruthenium and rhenium. These materials are virtually insoluble and immiscible in copper, and can be readily deposited by electroless deposition, for example. The barrier layer may be in contact with the adjacent portions of the at least one dielectric layer. In addition, at least one other barrier layer can be provided between the barrier layer and the copper portion. The interconnect structure in some embodiments may extend both laterally and vertically within the at least one dielectric layer.

Description

RELATED APPLICATION

This application is based upon provisional application Ser. No. 60/159,068, filed Oct. 12, 1999, now Ser. No. 60/153,400, filed Sep. 10, 1999, and is a continuation-in-part of U.S. patent application Ser. No. 09/657,740 filed Sep. 8, 2000, which, in turn, is a continuation-in-part of U.S. patent application Ser. No. 09/642,140 filed on Aug. 18, 2000, which, in turn, is a continuation-in-part application of U.S. patent application Ser. No. 09/619,587 filed on Jul. 19, 2000, the entire disclosures of all of which are incorporated herein by reference.

FIELD OF THE INVENTION

The invention relates to the field of integrated circuits, and more particularly, to the field of fabrication of current carrying interconnects, contacts, and vias.

BACKGROUND OF THE INVENTION

By the mid-1999 time frame, the integrated circuit industry was on its way to an apparent conversion of aluminum alloy based interconnects to a copper-based technology. Motivations for this change included the lower resistivity of copper, its higher electromigration resistance, and possible cost reductions from the damascene process which typically used lower cost electro-chemically deposited copper. The lower resistivity of copper held the promise of reduced RC delays in the interconnects, thus enabling higher performance circuits. This was particularly important for high performance logic applications, such as microprocessor chips where clock rates escalated with each new generation.

The status of this effort and some of the technical problems being faced may be found, for example, in two articles which appeared in the August 1999, Semiconductor International: (1) “Aluminum Persists as Copper Age Dawns” by Alexander E. Braun, pg 58, and (2) “Dual Damascene Challenges Dielectric Etch” by Peter Singer, pg. 68.

As explained in the second article and in other contemporaneous technical literature, the dual damascene process requires two etch-stop layers. They are generally composed of CVD silicon nitride. One nitride layer is at the bottom over the substrate, and the other lies at an intermediate position defining the bottom of the trench. In dual damascene, the interconnect metal is deposited or let into both the trench and into the underlying via. The metal is formed within both simultaneously.

The high selectively possible between silicon oxide dielectrics and a nitride dielectric, employing known plasma etch chemistries, allows the via opening to the underlying conductor to be held to a controlled diameter and also allows some misalignment to the underlying metal target. The via diameter may be almost as small as the minimum feature size of the particular technology, that is, on the order of a 0.25 micron by the late 1990's.

Accepted industry jargon refers to a via as an electrical connection from one level of interconnect to another. A contact is generally considered a metal electrical connection to doped silicon, and as such, refers to structures which normally are found under the interconnects. (An rare exception to this positional relationship may be a “contact” to a doped polysilicon interconnect.)

Vias and contacts may be self-aligned to the underlying target conductor. This means that some degree of mis-registration is allowed, in other words, the cylindrically shaped dielectric opening or aperture may be somewhat outside the metal target area. The bottom metal may not have to be larger than the contact or via aperture. In some cases, such a structure has been referred to as a borderless contact or via. The patent literature contains many varied schemes for achieving such structures. Most of the approaches employ etch stops, an idea that is quite old going back at least as early as Haskell's U.S. Pat. No. 5,057,902 filed in 1989. Other schemes, mainly for self-aligned contacts to MOS transistors, use edge spacers, or spacers and etch stops. Various etch stop materials have been proposed, but silicon nitride dominates actual use in the industry. A self-aligned structure allows tighter design rules, and, thus, improves the packing density—a major driving force in the industry.

If the nitride etch stop layers are not present in the dual damascene scheme, the system may not be used for self-aligned vias. This is because when the trench is etched with the via aperture already formed, which is the usual practice, the insulator adjacent to the metal conductor can be severely over etched, possibly all the way down to underlying conductive structures. This could create a short. And, in some cases, the opening next to the bottom conductor could assume a very narrow slit geometry which could be difficult to cover with a barrier layer by conventional techniques. The upper or intermediate nitride layer forms an etch stop for accurately locating the bottom of the trench.

The lower level nitride layer in dual damascene may also serve as a diffusion barrier over an underlying copper interconnect.

With good oxide/nitride etch selectively and proper sequencing of the dielectric film removal process, a self-aligned via may be provided in the dual damascene process to an underlying tungsten plug or copper conductor. But the nitride layers, with their high dielectric constant relative to SiO2 (about 7.5 vs. 3.9) increases the capacitive coupling between interconnects, thereby increasing RC delays. This is a strongly negative factor in the development of interconnects for modern high performance logic applications.

Indeed, a great deal of work was under way in the late 1990's to develop a lower dielectric constant interconnect dielectric, that is, a replacement for more or less pure SiO2. But no clear winner had emerged by mid-1999. Candidates for low k materials included: fluorine containing silicon oxides; porous spin-on-glasses; spin-on glasses containing only hydrogen, oxygen and silicon; and various polymers such as polyimide.

In a related area, the electromigration resistance of copper vias may be degraded by flux divergence at the copper barrier metal or tungsten interface.

Another concern in copper-based metal systems is that the diffusion barrier within very narrow high-aspect ratio vias may be such that the barrier thickness is not uniform or continuous and copper may migrate into the inter-metal dielectric and degrade the interconnect leakage characteristics or diffuse downward into the active area causing shifts in transistor characteristics.

SUMMARY OF THE INVENTION

In view of the foregoing background, an object of this invention is to provide a copper-based interconnect system with relative freedom from the problems mentioned above. For example, the copper-based interconnect system in accordance with the invention may not have: increased capacitive coupling from the presence of nitride etch stop layers; excessive degradation of the electromigration resistance of the interconnects as a result of void formation at the vias; excessive copper diffusion through a nonuniform barrier layer on the side walls of vias; and an inability of the system to provide self-aligned vias.

These and other objects, features and advantages in accordance with the present invention are provided by an integrated circuit comprising a substrate, at least one dielectric layer adjacent the substrate, and an interconnect structure in the at least one dielectric layer and comprising a copper portion and a barrier layer between the copper portion and adjacent portions of the at least one dielectric layer. Moreover, the barrier layer preferably comprises at least one of rhodium, ruthenium and rhenium. These materials are virtually insoluble and immiscible in copper, and can be readily deposited by electroless deposition, for example.

The barrier layer may be in contact with the adjacent portions of the at least one dielectric layer. In addition, at least one other barrier layer can be provided between the barrier layer and the copper portion.

The interconnect structure in some embodiments may extend both laterally and vertically within the at least one dielectric layer. In other words, the interconnect structure may include a laterally extending interconnect line and one or more vias.

The barrier layer may also comprise at least one of chromium, tungsten, tantalum, and molybdenum. The barrier layer may also comprise silicon. These materials may also be deposited using sputter deposition, for example.

In some embodiments, an adhesion layer may be provided between the barrier layer and adjacent portions of the at least one dielectric layer. For example, the adhesion layer may comprise titanium.

The copper portion may comprise a copper alloy. In addition, the copper portion may include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant to further enhance electromigration properties.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a cross-sectional view of a portion of an integrated circuit device illustrating a prior art dual-damascene copper-based interconnect with a tungsten plug contact showing a self-aligned copper via to an underlying copper metal one interconnect.

FIG. 2 is a cross-sectional view of a portion of an integrated circuit device illustrating forming of an aperture through the dielectric for a self-aligned contact according to the invention.

FIG. 3 is a cross-sectional view of the integrated circuit device of FIG. 2 after forming the barrier and seed layers and plating the copper.

FIG. 4 is a cross-sectional view of the integrated circuit device of FIG. 3 after CMP planarization of the plated copper and selective deposition of a top side barrier film.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will now be described more fully hereinafter with reference to the accompanying drawings in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the illustrated embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.

Referring initially to FIG. 1, an integrated circuit portion 10 including a prior art copper-based dual damascene system is first described. The integrated circuit 10 includes a substrate 11 with has shallow trench isolation (STI) areas 12, and source/drain doped silicon regions 13. A gate electrode 14 is formed above the substrate surface between the source/drain regions 13. A tungsten plug 15 extends downwardly to contact a source/drain region 13. The opening for the tungsten plug 15 is lined with contacting barrier and adhesion films 16.

The flat upper surface over the tungsten plug 15 represents CMP processing. Contacting the tungsten plug 15 is a single-damascene metal-one copper interconnect level 17 with an associated barrier metal layer 18 typically Ta, TaN or other refractory metal or compound. After CMP, the copper metal-one interconnect level 17 is coated with nitride film 24. Stacked layers 20, 21, 22 and 23 are SiO2 dielectric layers typically deposited using high density plasma CVD methods (HDPCVD) as will be appreciated by those skilled in the art. Nitride layers 24 and 25 are used as etch stop layers. The integrated circuit 10 also illustratively includes a barrier layer 26 and a seed layer 27 lining the opening for the second interconnect 12. The second or upper copper interconnect level 28 is typically plated copper and is shown after CMP planarization as will be appreciated by those skilled in the art.

The upper copper interconnect level 28 is shown mis-aligned to the edge of the copper one interconnect level 17. This represents a self-aligned structure. This is accomplished by first etching the via aperture through the upper nitride film 25, but stopping at the lower nitride layer 24. The resist is stripped and the trench mask is applied. The intermediate dielectric layer 22 is then etched to the lower nitride 24 using oxide-only etching chemistry. Finally, changing chemistries again, the exposed nitride film 24 is etched with nitride etching chemistry exposing the copper surface, but not appreciably etching the SiO2 next to the edge of the copper one interconnect level 17.

Referring now to FIG. 2 an early stage in preparation of an embodiment of the invention is now described. A single damascene copper interconnect line 57 is illustrated adjacent a substrate 51. For clarity of illustration other structures and layers beneath the copper interconnect line 57 are not shown. The copper interconnect line 57 with its associated barrier metal layer 58 are CMP planarized to the dashed line 61. A dielectric layer 62 is the dielectric layer into which the interconnect line 57 is let or formed as will be appreciated by those skilled in the art. Dielectric layer 63 is formed over the lower dielectric layer 61. The dielectric layers 61, 63 may be any suitable dielectric material, such as SiO2, for example, which may be deposited by HDPCVD. In addition, the dielectric layers 61, 63 may have a substantially uniform etch rate from top to bottom.

The exposed copper surface is then activated with PdCl2, for example, and then electrolessly plated with Co+P, Co+P+W or Co, forming an upper layer 65 as shown in the illustrated embodiment. Lopatin, et. al, showed that an alloy of Co(87%)W(2%)P(11%) may be selectively applied to copper by first activation with a PdCl2+dilute HF. Lopatin used 150-200 ml/l of HF with 1% PdCl2 solution for 2-3 seconds. This paper is entitled “Electroless Cu and barrier layers for sub-micron multilevel multilevel interconnects” is found in SPIE Vol. 3214 (1997), pg. 21, and is incorporated hereby by reference in its entirety.

Workers at IBM selectively deposited Co+P alloy on copper in the presence of polyimide by activating the surface with a Pd containing solution. U.S. Pat. No. 5,380,560, for example, lists details on Pd ion concentration and immersion times for this type of work. This patent is also incorporated in its entirety by reference. The IBM researchers suggest that in order to assure selectively, the device may be rinsed in citrate solution to remove extraneous metal deposition between copper lines. The IBM papers discussing this work may be found in E. J. O'Sullivan, et al, “Electrolessly deposited diffusion barriers for microelectronics,” IBM J. Res. Dev., Vol.42, No.5, September, 1998, pg. 607; and Milan Paunovic, et al, “Electrochemically Deposited Diffusion Barriers,” J. Electrochem. Soc., 141, No. 7, July 1994, pg. 1843. These paper are also incorporated herein by reference in their entirety. The Co-based barrier may be deposited to a thickness of about 100 to 500 A.

Following the barrier layer 65 deposition, an anneal at around 400° C. for several hours would diffuse in the Co a few monolayers deep such that a hardened, more electromigration resistant skin of Cu+Co alloy would exist in the copper interconnect surface.

Electrolessly plated metal films tend to be more conformal and uniform in thickness than films deposited by sputtering, for example. FIG. 3 shows the integrated circuit device 50 after formation of an electrolessly deposited barrier layer 66, a Cu or an alloy seed layer 67, and the thick electroplated copper or copper alloy layer 68. The barrier layer 66 may also be a Co+P or Co+W+P or Co layer as described above, but in this case, the plating is onto an insulator.

This may be accomplished, as is known in the art, by first immersion of the wafers into stannous chloride solution followed by immersion into PdCl2 solution. This and other activation processors for dielectrics, and metals which do not normally receive plated deposits such chromium, is given in U.S. Pat. No. 4,181,760 to Feldstein which is incorporated herein by reference in its entirety. This activation film may be only a monolayer in thickness.

The activation is followed by deposition of the alloy seed layer 67, such as Cu+about 1 to 5% Cd or Zn. Other dopants may be used also, as described in the listed applications by Cunningham at the end of this detailed description. This layer 67 may be electroplated or deposited by electroless methods. Prior to its application, the surface of the barrier layer 66 may be activated using PdCl2. The seed layer 67 would be about 100 to 400 Å thick. The alloy is more electromigration resistant than undoped Cu and protects the via from unwanted void formation when current flows at high current density upward into the via. The barrier layer 65 and its associated thin Cu alloy protects the via from downward current flow.

The seed layer 67 may be also deposited by sputtering. The dopants in the seed layer may be driven into the overlying copper layer 68 by a heat treatment, as described in greater detail in U.S. patent application Ser. No. 09/045,610, for example.

The thick copper film 68 may be electroplated Cu or a Cu alloy which includes a dopant, such as described in U.S. patent applications, Ser. No. 09/045,610 filed on March 20, Ser. No. 09/148,096 filed on Sep. 4, 1998; Ser. No. 09/271,179 filed on Mar. 17, 1999; and Ser. No. 09/289,331 filed on Apr. 9, 1999.

The thick copper layer 68 may also be deposited by electroless methods. This has been reported by Pai and Ting in “Selective Electroless Copper for VLSI Interconnection”, IEEE Electron Device Letters, Vol. 10, No. 9, September 1989, pg. 423, the entire disclosure of which is incorporated hereby reference.

FIG. 4 shows the device 50 after CMP planarization and after the application of another Co-based electrolessly-deposited barrier layer 70 on the via surface. This film 70 could be about 50 to 200 Å thick. The via is now ready to receive the next overlying copper interconnect as described above and as will be readily appreciated by those skilled in the art. Alternatively, the copper via surface could simply be displacement plated with Pd, Pt, Au, Rh or other noble metal as described in Ser. No. 09/642,140 filed on Aug. 18, 2000.

Annealing would offer improved electromigration resistance as described above. Alternatively, the copper surface could be left bare and covered later with the application of the barrier film associated with the next interconnect.

Another embodiment for improved self-aligned vias is the case where dual damascene and the nitride etch stops are used, as discussed above. In this embodiment, use is made of electroless barrier layers as described above together with doped copper alloy film. This gives rise to a dual damascene based via with improved electromigration resistance and substantially complete freedom from expensive vacuum-system-based film deposition systems for metal deposition. Alternatively, the copper seed layer may be deposited by sputtering.

It will be appreciated by one-skilled in-the-art that a dual damascene structure can be used and combined with the self-aligned via process shown in FIGS. 2, 3 and 4. This requires one less nitride layer, that is, the bottom nitride film, may be eliminated.

Since copper is approximately 9 at. % soluble in Co at 100° C. or lower, Co or its alloys is not a ideal diffusion barrier for Cu, and it would be limited in the downward scaling of its thickness. A nickel-based diffusion barrier is even less robust since Cu and Ni form a continuous series of solid solutions.

Prior art diffusion barrier metals for copper that have been extensively characterized and used in the industry include Cr, W, Ta and Mo. In some cases, as is well known, the metals are combined with nitrogen in varying concentrations or with other elements to further reduce the diffusion rates of copper through the barrier material. As discussed in the parent application Ser. No. 09/045,610 filed on Mar. 20, 1998, a desirable if not necessary metallurgical property for a robust diffusion barrier is that it have very low solubility for the metal to be blocked, and that it form no compounds. In other words, the barrier metal should be virtually insoluble and immiscible with the metal to be blocked in the solid phase. Exceptions to this rule are various barriers which have been used for blocking aluminum, such as Ti, which are actually sacrificial barriers where compound formation rates are slow enough for some applications.

The metals mentioned above, that is Cr, W, Ta and Mo, all have these properties with copper. But no technology currently exits to deposit them by electroless means.

An element which has the necessary metallurgical properties, as mentioned above, for viable use as a barrier and which may also be electrolessly deposited is ruthenium. Ru is a quite conductive metal (resistivity about 7 μ ohm cm) with a high melting point of about 2300° C. It lies in Periodic Table Group VIII under iron. With copper, Ru is virtually insoluble in both the liquid and solid states.

Details for electroless plating of Ru on various metals and dielectrics are given in E. Torikai, Y. Kawami, and K. Takenaka, Japanese patent Kokai Tokkyo Kuho 84-80766(1984). A two page description of the Japanese method may be found in “Electroless Plating” edited by Glenn O. Mallory and Juan B. Hajdu published by American Electroplaters and Surface Finishers Society, Inc. and distributed and published by Noyes Publications, New York. See page 437. The metal is deposited in nitrosylammine complexes in combination with the reducing agent hydrazine. Activation is accomplished in the usual manner with PdCl2 or other noble metals in solution.

Another metal with the necessary metallurgical properties for success as a diffusion barrier for copper is rhodium. The text on electroless plating listed above gives a recipe for electroless plating of Rh on page 439.

Another metal with the necessary metallurgical properties for success as a diffusion barrier for copper is rhenium.

In the form of thin films Ru, Re or Rh may be improved in their ability to block solid state diffusion of copper by stuffing of grain boundaries with various agents such as nitrogen and trace amounts of oxygen. Alternatively, the elements may be combined with Si or other suitable refractory metals such as Cr, W, Ta and Mo and deposited by sputtering in an amorphous state as in known in the art. Any of these metals or alloys mentioned may be deposited by sputtering. A very thin film of Ti, for example, may be placed under the barrier metals to improve the adhesion to oxide dielectrics.

RuO2 is a conductive oxide, with a resistivity of about 64μ ohm cm, which has been explored as barrier to aluminum. Information on this work may be found, for example, in Keizo Sakiyama, et al, “Deposition and Properties of Reactively Sputtered Ruthenium Dioxide Films,” J. Electrochem. Soc., Vol. 140, No.3, March 1993, page 834.

Ruthenium metal and its oxide may also be deposited by organometallic CVD methods. The CVD method is also known for excellent step coverage. M. L. Green and coworkers at AT&T Bell Labs reported such a process in the J. Blectrochem. Soc., Vol. 132, No. 11, November 1985, page 2677. Among several precursors explored, Ru3(CO)12 produced metallic Ru films with “excellent” film adhesion and a resistivity of 17μ ohm cm.

Other related concepts and discussions are provided in the following U.S. patent applications to Cunningham: Ser. No. 09/045,610, filed on Mar. 20, 1998; Ser. No. 09/148,096 filed on Sep. 4, 1998; Ser. No. 09/271,179 filed on Mar. 17, 1999; Ser. No. 09/289,331 filed on Apr. 9, 1999; Ser. No. 09/619,587 filed on Jul. 19, 2000; Ser. No. 09/642,140 filed on Aug. 18, 2000; Ser. No. 09/657,740 filed on Sep. 8, 2000; serial No. 60/159,068 filed on Oct. 12, 1999. The entire disclosure of each of these applications is incorporated herein by reference.

The embodiments described above are provided by way of illustration only and are not intended to limit the invention. Thus, many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Accordingly, it is understood that the invention is not to be limited to the illustrated embodiments disclosed, and that other modifications and embodiments are intended to be included within the spirit and scope of the appended claims.

Claims (34)

What is claimed is:
1. An integrated circuit comprising:
a substrate;
at least one dielectric layer adjacent said substrate; and
an interconnect structure in said at least one dielectric layer and comprising a copper portion and a copper-diffusion barrier layer between said copper portion and adjacent portions of said at least one dielectric layer;
said copper-diffusion barrier layer comprising at least one of rhodium, ruthenium and rhenium.
2. An integrated circuit according to claim 1 wherein said copper-diffusion barrier layer comprising at least one of rhodium, ruthenium and rhenium is in contact with the adjacent portions of the at least one dielectric layer.
3. An integrated circuit according to claim 2 further comprising at least one other copper-diffusion barrier layer between said copper-diffusion barrier layer comprising at least one of rhodium, ruthenium and rhenium and said copper portion.
4. An integrated circuit according to claim 1 wherein said interconnect structure extends both laterally and vertically within said at least one dielectric layer.
5. An integrated circuit according to claim 1 wherein said copper-diffusion barrier layer comprising at least one of rhodium, ruthenium and rhenium further comprises at least one of chromium, tungsten, tantalum, and molybdenum.
6. An integrated circuit according to claim 1 wherein said copper-diffusion barrier layer comprising at least one of rhodium, ruthenium and rhenium further comprises silicon.
7. An integrated circuit according to claim 1 further comprising an adhesion layer between said copper-diffusion barrier layer comprising at least one of rhodium, ruthenium and rhenium and adjacent portions of said at least one dielectric layer.
8. An integrated circuit according to claim 7 wherein said adhesion layer comprises titanium.
9. An integrated circuit according to claim 1 wherein said copper portion comprises a copper alloy.
10. An integrated circuit according to claim 1 wherein said copper portion comprises at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant.
11. An integrated circuit comprising:
a substrate;
at least one dielectric layer adjacent said substrate; and
an interconnect structure in said at least one dielectric layer and comprising a copper portion and a copper-diffusion barrier layer between said copper portion and adjacent portions of said at least one dielectric layer;
said copper-diffusion barrier layer comprising rhodium.
12. An integrated circuit according to claim 11 wherein said rhodium copper-diffusion barrier layer is in contact with the adjacent portions of the at least one dielectric layer.
13. An integrated circuit according to claim 12 further comprising at least one other copper-diffusion barrier layer between said rhodium copper-diffusion barrier layer and said copper portion.
14. An integrated circuit according to claim 11 wherein said interconnect structure extends both laterally and vertically within said at least one dielectric layer.
15. An integrated circuit according to claim 11 wherein said rhodium copper-diffusion barrier layer further comprises at least one of chromium, tungsten, tantalum, and molybdenum.
16. An integrated circuit according to claim 11 wherein said rhodium copper-diffusion barrier layer further comprises silicon.
17. An integrated circuit according to claim 11 wherein said copper portion comprises a copper alloy.
18. An integrated circuit according to claim 11 wherein said copper portion comprises at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant.
19. An integrated circuit comprising:
a substrate;
at least one dielectric layer adjacent said substrate; and
an interconnect structure in said at least one dielectric layer and comprising a copper portion and a copper-diffusion barrier layer between said copper portion and adjacent portions of said at least one dielectric layer;
said copper-diffusion barrier layer comprising ruthenium.
20. An integrated circuit according to claim 19 wherein said ruthenium copper-diffusion barrier layer is in contact with the adjacent portions of the at least one dielectric layer.
21. An integrated circuit according to claim 20 further comprising at least one other copper diffusion barrier layer between said ruthenium copper-diffusion barrier layer and said copper portion.
22. An integrated circuit according to claim 19 wherein said interconnect structure extends both laterally and vertically within said at least one dielectric layer.
23. An integrated circuit according to claim 19 wherein said ruthenium copper-diffusion barrier layer further comprises at least one of chromium, tungsten, tantalum, and molybdenum.
24. An integrated circuit according to claim 19 wherein said ruthenium copper-diffusion barrier layer further comprises silicon.
25. An integrated circuit according to claim 19 wherein said copper portion comprises a copper alloy.
26. An integrated circuit according to claim 19 wherein said copper portion comprises at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant.
27. An integrated circuit comprising:
a substrate;
at least one dielectric layer adjacent said substrate; and
an interconnect structure in said at least one dielectric layer and comprising a copper portion and a copper-diffusion barrier layer between said copper portion and adjacent portions of said at least one dielectric layer;
said copper-diffusion barrier layer comprising rhenium.
28. An integrated circuit according to claim 27 wherein said rhenium copper-diffusion barrier layer is in contact with the adjacent portions of the at least one dielectric layer.
29. An integrated circuit according to claim 28 further comprising at least one other copper-diffusion barrier layer between said rhenium copper-diffusion barrier layer and said copper portion.
30. An integrated circuit according to claim 27 wherein said interconnect structure extends both laterally and vertically within said at least one dielectric layer.
31. An integrated circuit according to claim 27 wherein said rhenium copper-diffusion barrier layer further comprises at least one of chromium, tungsten, tantalum, and molybdenum.
32. An integrated circuit according to claim 27 wherein said rhenium copper-diffusion barrier layer further comprises silicon.
33. An integrated circuit according to claim 27 wherein said copper portion comprises a copper alloy.
34. An integrated circuit according to claim 27 wherein said copper portion comprises at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant.
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US09642140 US6551872B1 (en) 1999-07-22 2000-08-18 Method for making integrated circuit including interconnects with enhanced electromigration resistance using doped seed layer and integrated circuits produced thereby
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Cited By (130)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020084529A1 (en) * 2000-12-28 2002-07-04 Dubin Valery M. Interconnect structures and a method of electroless introduction of interconnect structures
US20030190426A1 (en) * 2002-04-03 2003-10-09 Deenesh Padhi Electroless deposition method
US20030189026A1 (en) * 2002-04-03 2003-10-09 Deenesh Padhi Electroless deposition method
US20030190812A1 (en) * 2002-04-03 2003-10-09 Deenesh Padhi Electroless deposition method
US20030203617A1 (en) * 2002-04-26 2003-10-30 Michael Lane Process of forming copper structures
US20030207560A1 (en) * 2002-05-03 2003-11-06 Dubin Valery M. Use of conductive electrolessly deposited etch stop layers, liner layers and via plugs in interconnect structures
US20040051117A1 (en) * 2002-07-02 2004-03-18 Oliver Chyan Method of using materials based on Ruthenium and Iridium and their oxides, as a Cu diffusion barrier, and integrated circuits incorporating same
US6713377B2 (en) * 1998-07-31 2004-03-30 Industrial Technology Research Institute Method of electroless plating copper on nitride barrier
US20040087141A1 (en) * 2002-10-30 2004-05-06 Applied Materials, Inc. Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application
US20040084773A1 (en) * 2002-10-31 2004-05-06 Johnston Steven W. Forming a copper diffusion barrier
US6787912B2 (en) * 2002-04-26 2004-09-07 International Business Machines Corporation Barrier material for copper structures
US6790767B2 (en) 2001-11-28 2004-09-14 Dongbu Electronics Co., Ltd. Method for formation of copper diffusion barrier film using aluminum
US20040248403A1 (en) * 2003-06-09 2004-12-09 Dubin Valery M. Method for forming electroless metal low resistivity interconnects
US20050001325A1 (en) * 2003-07-03 2005-01-06 International Business Machines Corporation Selective capping of copper wiring
US6841466B1 (en) 2003-09-26 2005-01-11 Taiwan Semiconductor Manufacturing Company Method of selectively making copper using plating technology
US20050081785A1 (en) * 2003-10-15 2005-04-21 Applied Materials, Inc. Apparatus for electroless deposition
US20050101132A1 (en) * 2000-12-06 2005-05-12 Ki-Bum Kim Copper interconnect structure having stuffed diffusion barrier
US20050124158A1 (en) * 2003-10-15 2005-06-09 Lopatin Sergey D. Silver under-layers for electroless cobalt alloys
US20050136193A1 (en) * 2003-10-17 2005-06-23 Applied Materials, Inc. Selective self-initiating electroless capping of copper with cobalt-containing alloys
US20050179138A1 (en) * 2001-10-22 2005-08-18 Lsi Logic Corporation Method for creating barriers for copper diffusion
US20050260345A1 (en) * 2003-10-06 2005-11-24 Applied Materials, Inc. Apparatus for electroless deposition of metals onto semiconductor substrates
US20050263066A1 (en) * 2004-01-26 2005-12-01 Dmitry Lubomirsky Apparatus for electroless deposition of metals onto semiconductor substrates
US20050274622A1 (en) * 2004-06-10 2005-12-15 Zhi-Wen Sun Plating chemistry and method of single-step electroplating of copper on a barrier metal
US20060003570A1 (en) * 2003-12-02 2006-01-05 Arulkumar Shanmugasundram Method and apparatus for electroless capping with vapor drying
US6998343B1 (en) 2003-11-24 2006-02-14 Lsi Logic Corporation Method for creating barrier layers for copper diffusion
US20060134855A1 (en) * 2004-12-17 2006-06-22 Hynix Semiconductor, Inc. Method for fabricating capacitor of semiconductor device
US20060165892A1 (en) * 2005-01-27 2006-07-27 Applied Materials, Inc. Ruthenium containing layer deposition method
US20060162658A1 (en) * 2005-01-27 2006-07-27 Applied Materials, Inc. Ruthenium layer deposition apparatus and method
US7087104B2 (en) 2003-06-26 2006-08-08 Intel Corporation Preparation of electroless deposition solutions
US20070071888A1 (en) * 2005-09-21 2007-03-29 Arulkumar Shanmugasundram Method and apparatus for forming device features in an integrated electroless deposition system
US20070090094A1 (en) * 2005-10-26 2007-04-26 Cabot Microelectronics Corporation CMP of copper/ruthenium substrates
US20070111519A1 (en) * 2003-10-15 2007-05-17 Applied Materials, Inc. Integrated electroless deposition system
US20070148826A1 (en) * 2005-10-07 2007-06-28 International Business Machines Corporation Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement
US7265048B2 (en) 2005-03-01 2007-09-04 Applied Materials, Inc. Reduction of copper dewetting by transition metal deposition
US20070246792A1 (en) * 2006-04-25 2007-10-25 Chih-Chao Yang Method for fabricating back end of the line structures with liner and seed materials
US20070275557A1 (en) * 2006-03-15 2007-11-29 International Business Machines Corporation Formation of oxidation-resistant seed layer for interconnect applications
US20070280848A1 (en) * 2004-03-24 2007-12-06 Jagdish Narayan Methods Of Forming Alpha And Beta Tantalum Films With Controlled And New Microstructures
US20080142971A1 (en) * 2006-12-14 2008-06-19 Lam Research Corporation Interconnect structure and method of manufacturing a damascene structure
US20080274369A1 (en) * 2005-04-21 2008-11-06 Lee Eal H Novel Ruthenium-Based Materials and Ruthenium Alloys, Their Use in Vapor Deposition or Atomic Layer Deposition and Films Produced Therefrom
US7514353B2 (en) 2005-03-18 2009-04-07 Applied Materials, Inc. Contact metallization scheme using a barrier layer over a silicide layer
US20090111280A1 (en) * 2004-02-26 2009-04-30 Applied Materials, Inc. Method for removing oxides
US7651934B2 (en) 2005-03-18 2010-01-26 Applied Materials, Inc. Process for electroless copper deposition
US7659203B2 (en) 2005-03-18 2010-02-09 Applied Materials, Inc. Electroless deposition process on a silicon contact
US20100038782A1 (en) * 2008-08-12 2010-02-18 International Business Machines Corporation Nitrogen-containing metal cap for interconnect structures
US7745324B1 (en) 2009-01-09 2010-06-29 International Business Machines Corporation Interconnect with recessed dielectric adjacent a noble metal cap
US20100295181A1 (en) * 2009-05-19 2010-11-25 International Business Machines Corporation Redundant metal barrier structure for interconnect applications
US7867900B2 (en) 2007-09-28 2011-01-11 Applied Materials, Inc. Aluminum contact integration on cobalt silicide junction
US20120061840A1 (en) * 2007-01-11 2012-03-15 Huang Chun-Jen Damascene interconnection structure and dual damascene process thereof
US8293643B2 (en) 2010-06-21 2012-10-23 International Business Machines Corporation Method and structure of forming silicide and diffusion barrier layer with direct deposited film on silicon
US8679983B2 (en) 2011-09-01 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and nitrogen
US8679982B2 (en) 2011-08-26 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and oxygen
US8765574B2 (en) 2012-11-09 2014-07-01 Applied Materials, Inc. Dry etch process
US8771539B2 (en) 2011-02-22 2014-07-08 Applied Materials, Inc. Remotely-excited fluorine and water vapor etch
US8801952B1 (en) 2013-03-07 2014-08-12 Applied Materials, Inc. Conformal oxide dry etch
US8808563B2 (en) 2011-10-07 2014-08-19 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
US8895449B1 (en) 2013-05-16 2014-11-25 Applied Materials, Inc. Delicate dry clean
US8921234B2 (en) 2012-12-21 2014-12-30 Applied Materials, Inc. Selective titanium nitride etching
US8927390B2 (en) 2011-09-26 2015-01-06 Applied Materials, Inc. Intrench profile
US8951429B1 (en) 2013-10-29 2015-02-10 Applied Materials, Inc. Tungsten oxide processing
US8956980B1 (en) 2013-09-16 2015-02-17 Applied Materials, Inc. Selective etch of silicon nitride
US8969212B2 (en) 2012-11-20 2015-03-03 Applied Materials, Inc. Dry-etch selectivity
US8975152B2 (en) 2011-11-08 2015-03-10 Applied Materials, Inc. Methods of reducing substrate dislocation during gapfill processing
US8980763B2 (en) 2012-11-30 2015-03-17 Applied Materials, Inc. Dry-etch for selective tungsten removal
US8999856B2 (en) 2011-03-14 2015-04-07 Applied Materials, Inc. Methods for etch of sin films
US9023734B2 (en) 2012-09-18 2015-05-05 Applied Materials, Inc. Radical-component oxide etch
US9023732B2 (en) 2013-03-15 2015-05-05 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9034770B2 (en) 2012-09-17 2015-05-19 Applied Materials, Inc. Differential silicon oxide etch
US9040422B2 (en) 2013-03-05 2015-05-26 Applied Materials, Inc. Selective titanium nitride removal
US9064816B2 (en) 2012-11-30 2015-06-23 Applied Materials, Inc. Dry-etch for selective oxidation removal
US9064815B2 (en) 2011-03-14 2015-06-23 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US9111877B2 (en) 2012-12-18 2015-08-18 Applied Materials, Inc. Non-local plasma oxide etch
US9114438B2 (en) 2013-05-21 2015-08-25 Applied Materials, Inc. Copper residue chamber clean
US9117855B2 (en) 2013-12-04 2015-08-25 Applied Materials, Inc. Polarity control for remote plasma
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US9136273B1 (en) 2014-03-21 2015-09-15 Applied Materials, Inc. Flash gate air gap
US9159606B1 (en) 2014-07-31 2015-10-13 Applied Materials, Inc. Metal air gap
US9165786B1 (en) 2014-08-05 2015-10-20 Applied Materials, Inc. Integrated oxide and nitride recess for better channel contact in 3D architectures
US9190293B2 (en) 2013-12-18 2015-11-17 Applied Materials, Inc. Even tungsten etch for high aspect ratio trenches
US9236266B2 (en) 2011-08-01 2016-01-12 Applied Materials, Inc. Dry-etch for silicon-and-carbon-containing films
US9236265B2 (en) 2013-11-04 2016-01-12 Applied Materials, Inc. Silicon germanium processing
US9245762B2 (en) 2013-12-02 2016-01-26 Applied Materials, Inc. Procedure for etch rate consistency
US9263278B2 (en) 2013-12-17 2016-02-16 Applied Materials, Inc. Dopant etch selectivity control
US9269590B2 (en) 2014-04-07 2016-02-23 Applied Materials, Inc. Spacer formation
US9287095B2 (en) 2013-12-17 2016-03-15 Applied Materials, Inc. Semiconductor system assemblies and methods of operation
US9287134B2 (en) 2014-01-17 2016-03-15 Applied Materials, Inc. Titanium oxide etch
US9293568B2 (en) 2014-01-27 2016-03-22 Applied Materials, Inc. Method of fin patterning
US9299575B2 (en) 2014-03-17 2016-03-29 Applied Materials, Inc. Gas-phase tungsten etch
US9299582B2 (en) 2013-11-12 2016-03-29 Applied Materials, Inc. Selective etch for metal-containing materials
US9299538B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9299537B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9299583B1 (en) 2014-12-05 2016-03-29 Applied Materials, Inc. Aluminum oxide selective etch
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9324576B2 (en) 2010-05-27 2016-04-26 Applied Materials, Inc. Selective etch for silicon films
US9343272B1 (en) 2015-01-08 2016-05-17 Applied Materials, Inc. Self-aligned process
US9349605B1 (en) 2015-08-07 2016-05-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US9355862B2 (en) 2014-09-24 2016-05-31 Applied Materials, Inc. Fluorine-based hardmask removal
US9355856B2 (en) 2014-09-12 2016-05-31 Applied Materials, Inc. V trench dry etch
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9368364B2 (en) 2014-09-24 2016-06-14 Applied Materials, Inc. Silicon etch process with tunable selectivity to SiO2 and other materials
US9373522B1 (en) 2015-01-22 2016-06-21 Applied Mateials, Inc. Titanium nitride removal
US9373517B2 (en) 2012-08-02 2016-06-21 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9378969B2 (en) 2014-06-19 2016-06-28 Applied Materials, Inc. Low temperature gas-phase carbon removal
US9378978B2 (en) 2014-07-31 2016-06-28 Applied Materials, Inc. Integrated oxide recess and floating gate fin trimming
US9385028B2 (en) 2014-02-03 2016-07-05 Applied Materials, Inc. Air gap process
US9390937B2 (en) 2012-09-20 2016-07-12 Applied Materials, Inc. Silicon-carbon-nitride selective etch
US9396989B2 (en) 2014-01-27 2016-07-19 Applied Materials, Inc. Air gaps between copper lines
US9406523B2 (en) 2014-06-19 2016-08-02 Applied Materials, Inc. Highly selective doped oxide removal method
US9425058B2 (en) 2014-07-24 2016-08-23 Applied Materials, Inc. Simplified litho-etch-litho-etch process
US9449846B2 (en) 2015-01-28 2016-09-20 Applied Materials, Inc. Vertical gate separation
US9478432B2 (en) 2014-09-25 2016-10-25 Applied Materials, Inc. Silicon oxide selective removal
US9496167B2 (en) 2014-07-31 2016-11-15 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9493879B2 (en) 2013-07-12 2016-11-15 Applied Materials, Inc. Selective sputtering for pattern transfer
US9502258B2 (en) 2014-12-23 2016-11-22 Applied Materials, Inc. Anisotropic gap etch
US9499898B2 (en) 2014-03-03 2016-11-22 Applied Materials, Inc. Layered thin film heater and method of fabrication
US9530856B2 (en) 2013-12-26 2016-12-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US9553102B2 (en) 2014-08-19 2017-01-24 Applied Materials, Inc. Tungsten separation
US9576809B2 (en) 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9659753B2 (en) 2014-08-07 2017-05-23 Applied Materials, Inc. Grooved insulator to reduce leakage current
US9691645B2 (en) 2015-08-06 2017-06-27 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US9721789B1 (en) 2016-10-04 2017-08-01 Applied Materials, Inc. Saving ion-damaged spacers
US9728437B2 (en) 2015-02-03 2017-08-08 Applied Materials, Inc. High temperature chuck for plasma processing systems
US9741593B2 (en) 2015-08-06 2017-08-22 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US9768034B1 (en) 2016-11-11 2017-09-19 Applied Materials, Inc. Removal methods for high aspect ratio structures
US9773648B2 (en) 2013-08-30 2017-09-26 Applied Materials, Inc. Dual discharge modes operation for remote plasma
US9847289B2 (en) 2014-05-30 2017-12-19 Applied Materials, Inc. Protective via cap for improved interconnect performance
US9865484B1 (en) 2016-06-29 2018-01-09 Applied Materials, Inc. Selective etch using material modification and RF pulsing
US9881805B2 (en) 2015-03-02 2018-01-30 Applied Materials, Inc. Silicon selective removal
US9885117B2 (en) 2014-03-31 2018-02-06 Applied Materials, Inc. Conditioned semiconductor system parts
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US9947549B1 (en) 2016-10-10 2018-04-17 Applied Materials, Inc. Cobalt-containing material removal

Citations (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6181012B2 (en)
US4233067A (en) 1978-01-19 1980-11-11 Sumitomo Electric Industries, Ltd. Soft copper alloy conductors
JPS60110868A (en) 1983-11-18 1985-06-17 Mitsubishi Metal Corp Surface hardened au alloy member
US4592891A (en) 1984-06-14 1986-06-03 Nippon Mining Co., Ltd. Corrosion-resistant copper alloy
JPS62127438A (en) 1985-11-26 1987-06-09 Nippon Mining Co Ltd Bonding wire for semiconductor device
JPS62133050A (en) 1985-12-03 1987-06-16 Nippon Mining Co Ltd Manufacture of high strength and high conductivity copper-base alloy
US4732731A (en) 1985-08-29 1988-03-22 The Furukawa Electric Co., Ltd. Copper alloy for electronic instruments and method of manufacturing the same
US4750029A (en) 1984-08-31 1988-06-07 Mitsubishi Shindoh Co., Ltd. Copper base lead material for leads of semiconductor devices
JPS6428337A (en) 1987-07-24 1989-01-30 Furukawa Electric Co Ltd High-strength and high-conductivity copper alloy
JPS6456842A (en) 1987-08-27 1989-03-03 Nippon Mining Co Copper alloy foil for flexible circuit board
US4908275A (en) 1987-03-04 1990-03-13 Nippon Mining Co., Ltd. Film carrier and method of manufacturing same
JPH02230756A (en) 1989-03-03 1990-09-13 Seiko Epson Corp Copper electrode wiring material
US4986856A (en) 1987-06-25 1991-01-22 The Furukawa Electric Co., Ltd. Fine copper wire for electronic instruments and method of manufacturing the same
US5130274A (en) 1991-04-05 1992-07-14 International Business Machines Corporation Copper alloy metallurgies for VLSI interconnection structures
US5143867A (en) 1991-02-13 1992-09-01 International Business Machines Corporation Method for depositing interconnection metallurgy using low temperature alloy processes
US5592024A (en) 1993-10-29 1997-01-07 Kabushiki Kaisha Toshiba Semiconductor device having a wiring layer with a barrier layer
US5624506A (en) 1993-09-30 1997-04-29 Kabushiki Kaisha Kobe Seiko Sho Copper alloy for use in electrical and electronic parts
JPH09157775A (en) 1995-09-27 1997-06-17 Nikko Kinzoku Kk Copper alloy for electronic equipment
US5674787A (en) 1996-01-16 1997-10-07 Sematech, Inc. Selective electroless copper deposited interconnect plugs for ULSI applications
US5694184A (en) 1995-08-01 1997-12-02 Kabushiki Kaisha Toshiba Liquid crystal display device
JPH108167A (en) 1996-06-18 1998-01-13 Mitsubishi Shindoh Co Ltd Excellent copper alloy hot workability
US5719447A (en) 1993-06-03 1998-02-17 Intel Corporation Metal alloy interconnections for integrated circuits
US5789320A (en) 1996-04-23 1998-08-04 International Business Machines Corporation Plating of noble metal electrodes for DRAM and FRAM
JPH1154713A (en) * 1997-07-29 1999-02-26 Sharp Corp Semiconductor memory element
US6037664A (en) 1997-08-20 2000-03-14 Sematech Inc Dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer
US6037257A (en) 1997-05-08 2000-03-14 Applied Materials, Inc. Sputter deposition and annealing of copper alloy metallization
US6060892A (en) 1996-12-27 2000-05-09 Tokyo Electron Limited Probe card attaching mechanism
US6066892A (en) 1997-05-08 2000-05-23 Applied Materials, Inc. Copper alloy seed layer for copper metallization in an integrated circuit
US6077780A (en) 1997-12-03 2000-06-20 Advanced Micro Devices, Inc. Method for filling high aspect ratio openings of an integrated circuit to minimize electromigration failure
US6147402A (en) 1992-02-26 2000-11-14 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US6157081A (en) 1999-03-10 2000-12-05 Advanced Micro Devices, Inc. High-reliability damascene interconnect formation for semiconductor fabrication
US6174799B1 (en) 1999-01-05 2001-01-16 Advanced Micro Devices, Inc. Graded compound seed layers for semiconductors
US6181012B1 (en) 1998-04-27 2001-01-30 International Business Machines Corporation Copper interconnection structure incorporating a metal seed layer
US6188120B1 (en) * 1997-02-24 2001-02-13 International Business Machines Corporation Method and materials for through-mask electroplating and selective base removal

Patent Citations (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6181012B2 (en)
US4233067A (en) 1978-01-19 1980-11-11 Sumitomo Electric Industries, Ltd. Soft copper alloy conductors
JPS60110868A (en) 1983-11-18 1985-06-17 Mitsubishi Metal Corp Surface hardened au alloy member
US4592891A (en) 1984-06-14 1986-06-03 Nippon Mining Co., Ltd. Corrosion-resistant copper alloy
US4750029A (en) 1984-08-31 1988-06-07 Mitsubishi Shindoh Co., Ltd. Copper base lead material for leads of semiconductor devices
US4732731A (en) 1985-08-29 1988-03-22 The Furukawa Electric Co., Ltd. Copper alloy for electronic instruments and method of manufacturing the same
JPS62127438A (en) 1985-11-26 1987-06-09 Nippon Mining Co Ltd Bonding wire for semiconductor device
JPS62133050A (en) 1985-12-03 1987-06-16 Nippon Mining Co Ltd Manufacture of high strength and high conductivity copper-base alloy
US4908275A (en) 1987-03-04 1990-03-13 Nippon Mining Co., Ltd. Film carrier and method of manufacturing same
US4986856A (en) 1987-06-25 1991-01-22 The Furukawa Electric Co., Ltd. Fine copper wire for electronic instruments and method of manufacturing the same
JPS6428337A (en) 1987-07-24 1989-01-30 Furukawa Electric Co Ltd High-strength and high-conductivity copper alloy
JPS6456842A (en) 1987-08-27 1989-03-03 Nippon Mining Co Copper alloy foil for flexible circuit board
JPH02230756A (en) 1989-03-03 1990-09-13 Seiko Epson Corp Copper electrode wiring material
US5143867A (en) 1991-02-13 1992-09-01 International Business Machines Corporation Method for depositing interconnection metallurgy using low temperature alloy processes
US5130274A (en) 1991-04-05 1992-07-14 International Business Machines Corporation Copper alloy metallurgies for VLSI interconnection structures
US6147402A (en) 1992-02-26 2000-11-14 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5719447A (en) 1993-06-03 1998-02-17 Intel Corporation Metal alloy interconnections for integrated circuits
US5624506A (en) 1993-09-30 1997-04-29 Kabushiki Kaisha Kobe Seiko Sho Copper alloy for use in electrical and electronic parts
US5592024A (en) 1993-10-29 1997-01-07 Kabushiki Kaisha Toshiba Semiconductor device having a wiring layer with a barrier layer
US5694184A (en) 1995-08-01 1997-12-02 Kabushiki Kaisha Toshiba Liquid crystal display device
JPH09157775A (en) 1995-09-27 1997-06-17 Nikko Kinzoku Kk Copper alloy for electronic equipment
US5674787A (en) 1996-01-16 1997-10-07 Sematech, Inc. Selective electroless copper deposited interconnect plugs for ULSI applications
US5789320A (en) 1996-04-23 1998-08-04 International Business Machines Corporation Plating of noble metal electrodes for DRAM and FRAM
JPH108167A (en) 1996-06-18 1998-01-13 Mitsubishi Shindoh Co Ltd Excellent copper alloy hot workability
US6060892A (en) 1996-12-27 2000-05-09 Tokyo Electron Limited Probe card attaching mechanism
US6188120B1 (en) * 1997-02-24 2001-02-13 International Business Machines Corporation Method and materials for through-mask electroplating and selective base removal
US6037257A (en) 1997-05-08 2000-03-14 Applied Materials, Inc. Sputter deposition and annealing of copper alloy metallization
US6066892A (en) 1997-05-08 2000-05-23 Applied Materials, Inc. Copper alloy seed layer for copper metallization in an integrated circuit
JPH1154713A (en) * 1997-07-29 1999-02-26 Sharp Corp Semiconductor memory element
US6201271B1 (en) * 1997-07-29 2001-03-13 Sharp Kabushiki Kaisha Semiconductor memory device prevented from deterioration due to activated hydrogen
US6037664A (en) 1997-08-20 2000-03-14 Sematech Inc Dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer
US6077780A (en) 1997-12-03 2000-06-20 Advanced Micro Devices, Inc. Method for filling high aspect ratio openings of an integrated circuit to minimize electromigration failure
US6181012B1 (en) 1998-04-27 2001-01-30 International Business Machines Corporation Copper interconnection structure incorporating a metal seed layer
US6174799B1 (en) 1999-01-05 2001-01-16 Advanced Micro Devices, Inc. Graded compound seed layers for semiconductors
US6157081A (en) 1999-03-10 2000-12-05 Advanced Micro Devices, Inc. High-reliability damascene interconnect formation for semiconductor fabrication

Cited By (206)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6713377B2 (en) * 1998-07-31 2004-03-30 Industrial Technology Research Institute Method of electroless plating copper on nitride barrier
US6936535B2 (en) * 2000-12-06 2005-08-30 Asm International Nv Copper interconnect structure having stuffed diffusion barrier
US7732331B2 (en) 2000-12-06 2010-06-08 Asm International N.V. Copper interconnect structure having stuffed diffusion barrier
US20050101132A1 (en) * 2000-12-06 2005-05-12 Ki-Bum Kim Copper interconnect structure having stuffed diffusion barrier
US6977224B2 (en) 2000-12-28 2005-12-20 Intel Corporation Method of electroless introduction of interconnect structures
US20020084529A1 (en) * 2000-12-28 2002-07-04 Dubin Valery M. Interconnect structures and a method of electroless introduction of interconnect structures
US20050179138A1 (en) * 2001-10-22 2005-08-18 Lsi Logic Corporation Method for creating barriers for copper diffusion
US7829455B2 (en) 2001-10-22 2010-11-09 Lsi Corporation Method for creating barriers for copper diffusion
US7115991B1 (en) * 2001-10-22 2006-10-03 Lsi Logic Corporation Method for creating barriers for copper diffusion
US6790767B2 (en) 2001-11-28 2004-09-14 Dongbu Electronics Co., Ltd. Method for formation of copper diffusion barrier film using aluminum
US20030190812A1 (en) * 2002-04-03 2003-10-09 Deenesh Padhi Electroless deposition method
US6905622B2 (en) 2002-04-03 2005-06-14 Applied Materials, Inc. Electroless deposition method
US20030190426A1 (en) * 2002-04-03 2003-10-09 Deenesh Padhi Electroless deposition method
US6899816B2 (en) 2002-04-03 2005-05-31 Applied Materials, Inc. Electroless deposition method
US20030189026A1 (en) * 2002-04-03 2003-10-09 Deenesh Padhi Electroless deposition method
US6787912B2 (en) * 2002-04-26 2004-09-07 International Business Machines Corporation Barrier material for copper structures
US6812143B2 (en) * 2002-04-26 2004-11-02 International Business Machines Corporation Process of forming copper structures
US20030203617A1 (en) * 2002-04-26 2003-10-30 Michael Lane Process of forming copper structures
US6958547B2 (en) 2002-05-03 2005-10-25 Intel Corporation Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugs
US7008872B2 (en) * 2002-05-03 2006-03-07 Intel Corporation Use of conductive electrolessly deposited etch stop layers, liner layers and via plugs in interconnect structures
US20030207561A1 (en) * 2002-05-03 2003-11-06 Dubin Valery M. Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugs
US20030207560A1 (en) * 2002-05-03 2003-11-06 Dubin Valery M. Use of conductive electrolessly deposited etch stop layers, liner layers and via plugs in interconnect structures
US7247554B2 (en) 2002-07-02 2007-07-24 University Of North Texas Method of making integrated circuits using ruthenium and its oxides as a Cu diffusion barrier
US20040051117A1 (en) * 2002-07-02 2004-03-18 Oliver Chyan Method of using materials based on Ruthenium and Iridium and their oxides, as a Cu diffusion barrier, and integrated circuits incorporating same
US6821909B2 (en) 2002-10-30 2004-11-23 Applied Materials, Inc. Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application
US20050136185A1 (en) * 2002-10-30 2005-06-23 Sivakami Ramanathan Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application
US20040087141A1 (en) * 2002-10-30 2004-05-06 Applied Materials, Inc. Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application
CN100490114C (en) 2002-10-31 2009-05-20 英特尔公司 Semiconductor structure, and method for forming a copper diffusion barrier
WO2004042815A1 (en) * 2002-10-31 2004-05-21 Intel Corporation Forming a copper diffusion barrier
US7279423B2 (en) 2002-10-31 2007-10-09 Intel Corporation Forming a copper diffusion barrier
US20040084773A1 (en) * 2002-10-31 2004-05-06 Johnston Steven W. Forming a copper diffusion barrier
US20040248403A1 (en) * 2003-06-09 2004-12-09 Dubin Valery M. Method for forming electroless metal low resistivity interconnects
US7087104B2 (en) 2003-06-26 2006-08-08 Intel Corporation Preparation of electroless deposition solutions
US20060076685A1 (en) * 2003-07-03 2006-04-13 International Business Machines Selective capping of copper wiring
US7190079B2 (en) 2003-07-03 2007-03-13 International Business Machines Corporation Selective capping of copper wiring
US20050001325A1 (en) * 2003-07-03 2005-01-06 International Business Machines Corporation Selective capping of copper wiring
US7008871B2 (en) 2003-07-03 2006-03-07 International Business Machines Corporation Selective capping of copper wiring
US6841466B1 (en) 2003-09-26 2005-01-11 Taiwan Semiconductor Manufacturing Company Method of selectively making copper using plating technology
US7654221B2 (en) 2003-10-06 2010-02-02 Applied Materials, Inc. Apparatus for electroless deposition of metals onto semiconductor substrates
US20050260345A1 (en) * 2003-10-06 2005-11-24 Applied Materials, Inc. Apparatus for electroless deposition of metals onto semiconductor substrates
US20050124158A1 (en) * 2003-10-15 2005-06-09 Lopatin Sergey D. Silver under-layers for electroless cobalt alloys
US7341633B2 (en) 2003-10-15 2008-03-11 Applied Materials, Inc. Apparatus for electroless deposition
US20050081785A1 (en) * 2003-10-15 2005-04-21 Applied Materials, Inc. Apparatus for electroless deposition
US20070111519A1 (en) * 2003-10-15 2007-05-17 Applied Materials, Inc. Integrated electroless deposition system
US7064065B2 (en) 2003-10-15 2006-06-20 Applied Materials, Inc. Silver under-layers for electroless cobalt alloys
US20050136193A1 (en) * 2003-10-17 2005-06-23 Applied Materials, Inc. Selective self-initiating electroless capping of copper with cobalt-containing alloys
US6998343B1 (en) 2003-11-24 2006-02-14 Lsi Logic Corporation Method for creating barrier layers for copper diffusion
US20060003570A1 (en) * 2003-12-02 2006-01-05 Arulkumar Shanmugasundram Method and apparatus for electroless capping with vapor drying
US7827930B2 (en) 2004-01-26 2010-11-09 Applied Materials, Inc. Apparatus for electroless deposition of metals onto semiconductor substrates
US20050263066A1 (en) * 2004-01-26 2005-12-01 Dmitry Lubomirsky Apparatus for electroless deposition of metals onto semiconductor substrates
US8846163B2 (en) 2004-02-26 2014-09-30 Applied Materials, Inc. Method for removing oxides
US20090111280A1 (en) * 2004-02-26 2009-04-30 Applied Materials, Inc. Method for removing oxides
US20070280848A1 (en) * 2004-03-24 2007-12-06 Jagdish Narayan Methods Of Forming Alpha And Beta Tantalum Films With Controlled And New Microstructures
US20050274622A1 (en) * 2004-06-10 2005-12-15 Zhi-Wen Sun Plating chemistry and method of single-step electroplating of copper on a barrier metal
US7858483B2 (en) * 2004-12-17 2010-12-28 Hynix Semiconductor Inc. Method for fabricating capacitor of semiconductor device
US20060134855A1 (en) * 2004-12-17 2006-06-22 Hynix Semiconductor, Inc. Method for fabricating capacitor of semiconductor device
US7438949B2 (en) 2005-01-27 2008-10-21 Applied Materials, Inc. Ruthenium containing layer deposition method
US20060162658A1 (en) * 2005-01-27 2006-07-27 Applied Materials, Inc. Ruthenium layer deposition apparatus and method
US20060165892A1 (en) * 2005-01-27 2006-07-27 Applied Materials, Inc. Ruthenium containing layer deposition method
US7265048B2 (en) 2005-03-01 2007-09-04 Applied Materials, Inc. Reduction of copper dewetting by transition metal deposition
US8308858B2 (en) 2005-03-18 2012-11-13 Applied Materials, Inc. Electroless deposition process on a silicon contact
US20100107927A1 (en) * 2005-03-18 2010-05-06 Stewart Michael P Electroless deposition process on a silicon contact
US7659203B2 (en) 2005-03-18 2010-02-09 Applied Materials, Inc. Electroless deposition process on a silicon contact
US7514353B2 (en) 2005-03-18 2009-04-07 Applied Materials, Inc. Contact metallization scheme using a barrier layer over a silicide layer
US7651934B2 (en) 2005-03-18 2010-01-26 Applied Materials, Inc. Process for electroless copper deposition
US20080274369A1 (en) * 2005-04-21 2008-11-06 Lee Eal H Novel Ruthenium-Based Materials and Ruthenium Alloys, Their Use in Vapor Deposition or Atomic Layer Deposition and Films Produced Therefrom
US20070071888A1 (en) * 2005-09-21 2007-03-29 Arulkumar Shanmugasundram Method and apparatus for forming device features in an integrated electroless deposition system
US7498254B2 (en) 2005-10-07 2009-03-03 International Business Machines Corporation Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement
US20090155996A1 (en) * 2005-10-07 2009-06-18 International Business Machines Corporation Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement
WO2007044305A3 (en) * 2005-10-07 2007-12-13 Ibm Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement
CN100576530C (en) 2005-10-07 2009-12-30 国际商业机器公司 Plating seed layer including an oxygen/nitrogen transition region and interconnection structure and forming method
US8003524B2 (en) 2005-10-07 2011-08-23 International Business Machines Corporation Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement
US20070148826A1 (en) * 2005-10-07 2007-06-28 International Business Machines Corporation Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement
US20070090094A1 (en) * 2005-10-26 2007-04-26 Cabot Microelectronics Corporation CMP of copper/ruthenium substrates
US7265055B2 (en) * 2005-10-26 2007-09-04 Cabot Microelectronics Corporation CMP of copper/ruthenium substrates
US7585765B2 (en) * 2006-03-15 2009-09-08 International Business Machines Corporation Formation of oxidation-resistant seed layer for interconnect applications
US20070275557A1 (en) * 2006-03-15 2007-11-29 International Business Machines Corporation Formation of oxidation-resistant seed layer for interconnect applications
US20080242082A1 (en) * 2006-04-25 2008-10-02 Chih-Chao Yang Method for fabricating back end of the line structures with liner and seed materials
US8232195B2 (en) 2006-04-25 2012-07-31 International Business Machines Corporation Method for fabricating back end of the line structures with liner and seed materials
US20070246792A1 (en) * 2006-04-25 2007-10-25 Chih-Chao Yang Method for fabricating back end of the line structures with liner and seed materials
US7402883B2 (en) 2006-04-25 2008-07-22 International Business Machines Corporation, Inc. Back end of the line structures with liner and noble metal layer
US20080142971A1 (en) * 2006-12-14 2008-06-19 Lam Research Corporation Interconnect structure and method of manufacturing a damascene structure
WO2008073245A1 (en) * 2006-12-14 2008-06-19 Lam Research Corporation Interconnect structure and method of manufacturing a damascene structure
US8026605B2 (en) 2006-12-14 2011-09-27 Lam Research Corporation Interconnect structure and method of manufacturing a damascene structure
US20120061840A1 (en) * 2007-01-11 2012-03-15 Huang Chun-Jen Damascene interconnection structure and dual damascene process thereof
US7867900B2 (en) 2007-09-28 2011-01-11 Applied Materials, Inc. Aluminum contact integration on cobalt silicide junction
US8013446B2 (en) 2008-08-12 2011-09-06 International Business Machines Corporation Nitrogen-containing metal cap for interconnect structures
US20100038782A1 (en) * 2008-08-12 2010-02-18 International Business Machines Corporation Nitrogen-containing metal cap for interconnect structures
US7745324B1 (en) 2009-01-09 2010-06-29 International Business Machines Corporation Interconnect with recessed dielectric adjacent a noble metal cap
US20100176514A1 (en) * 2009-01-09 2010-07-15 International Business Machines Corporation Interconnect with recessed dielectric adjacent a noble metal cap
US8242600B2 (en) 2009-05-19 2012-08-14 International Business Machines Corporation Redundant metal barrier structure for interconnect applications
US8592306B2 (en) 2009-05-19 2013-11-26 International Business Machines Corporation Redundant metal barrier structure for interconnect applications
US20100295181A1 (en) * 2009-05-19 2010-11-25 International Business Machines Corporation Redundant metal barrier structure for interconnect applications
US9754800B2 (en) 2010-05-27 2017-09-05 Applied Materials, Inc. Selective etch for silicon films
US9324576B2 (en) 2010-05-27 2016-04-26 Applied Materials, Inc. Selective etch for silicon films
US8293643B2 (en) 2010-06-21 2012-10-23 International Business Machines Corporation Method and structure of forming silicide and diffusion barrier layer with direct deposited film on silicon
US8771539B2 (en) 2011-02-22 2014-07-08 Applied Materials, Inc. Remotely-excited fluorine and water vapor etch
US9064815B2 (en) 2011-03-14 2015-06-23 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US8999856B2 (en) 2011-03-14 2015-04-07 Applied Materials, Inc. Methods for etch of sin films
US9842744B2 (en) 2011-03-14 2017-12-12 Applied Materials, Inc. Methods for etch of SiN films
US9236266B2 (en) 2011-08-01 2016-01-12 Applied Materials, Inc. Dry-etch for silicon-and-carbon-containing films
US8679982B2 (en) 2011-08-26 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and oxygen
US8679983B2 (en) 2011-09-01 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and nitrogen
US8927390B2 (en) 2011-09-26 2015-01-06 Applied Materials, Inc. Intrench profile
US9012302B2 (en) 2011-09-26 2015-04-21 Applied Materials, Inc. Intrench profile
US8808563B2 (en) 2011-10-07 2014-08-19 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
US9418858B2 (en) 2011-10-07 2016-08-16 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
US8975152B2 (en) 2011-11-08 2015-03-10 Applied Materials, Inc. Methods of reducing substrate dislocation during gapfill processing
US9373517B2 (en) 2012-08-02 2016-06-21 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9887096B2 (en) 2012-09-17 2018-02-06 Applied Materials, Inc. Differential silicon oxide etch
US9034770B2 (en) 2012-09-17 2015-05-19 Applied Materials, Inc. Differential silicon oxide etch
US9023734B2 (en) 2012-09-18 2015-05-05 Applied Materials, Inc. Radical-component oxide etch
US9437451B2 (en) 2012-09-18 2016-09-06 Applied Materials, Inc. Radical-component oxide etch
US9390937B2 (en) 2012-09-20 2016-07-12 Applied Materials, Inc. Silicon-carbon-nitride selective etch
US9978564B2 (en) 2012-09-21 2018-05-22 Applied Materials, Inc. Chemical control features in wafer process equipment
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US8765574B2 (en) 2012-11-09 2014-07-01 Applied Materials, Inc. Dry etch process
US9384997B2 (en) 2012-11-20 2016-07-05 Applied Materials, Inc. Dry-etch selectivity
US8969212B2 (en) 2012-11-20 2015-03-03 Applied Materials, Inc. Dry-etch selectivity
US9412608B2 (en) 2012-11-30 2016-08-09 Applied Materials, Inc. Dry-etch for selective tungsten removal
US8980763B2 (en) 2012-11-30 2015-03-17 Applied Materials, Inc. Dry-etch for selective tungsten removal
US9064816B2 (en) 2012-11-30 2015-06-23 Applied Materials, Inc. Dry-etch for selective oxidation removal
US9355863B2 (en) 2012-12-18 2016-05-31 Applied Materials, Inc. Non-local plasma oxide etch
US9111877B2 (en) 2012-12-18 2015-08-18 Applied Materials, Inc. Non-local plasma oxide etch
US9449845B2 (en) 2012-12-21 2016-09-20 Applied Materials, Inc. Selective titanium nitride etching
US8921234B2 (en) 2012-12-21 2014-12-30 Applied Materials, Inc. Selective titanium nitride etching
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9040422B2 (en) 2013-03-05 2015-05-26 Applied Materials, Inc. Selective titanium nitride removal
US9607856B2 (en) 2013-03-05 2017-03-28 Applied Materials, Inc. Selective titanium nitride removal
US8801952B1 (en) 2013-03-07 2014-08-12 Applied Materials, Inc. Conformal oxide dry etch
US9093390B2 (en) 2013-03-07 2015-07-28 Applied Materials, Inc. Conformal oxide dry etch
US9659792B2 (en) 2013-03-15 2017-05-23 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9184055B2 (en) 2013-03-15 2015-11-10 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9093371B2 (en) 2013-03-15 2015-07-28 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9449850B2 (en) 2013-03-15 2016-09-20 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9023732B2 (en) 2013-03-15 2015-05-05 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9704723B2 (en) 2013-03-15 2017-07-11 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9153442B2 (en) 2013-03-15 2015-10-06 Applied Materials, Inc. Processing systems and methods for halide scavenging
US8895449B1 (en) 2013-05-16 2014-11-25 Applied Materials, Inc. Delicate dry clean
US9114438B2 (en) 2013-05-21 2015-08-25 Applied Materials, Inc. Copper residue chamber clean
US9493879B2 (en) 2013-07-12 2016-11-15 Applied Materials, Inc. Selective sputtering for pattern transfer
US9773648B2 (en) 2013-08-30 2017-09-26 Applied Materials, Inc. Dual discharge modes operation for remote plasma
US9209012B2 (en) 2013-09-16 2015-12-08 Applied Materials, Inc. Selective etch of silicon nitride
US8956980B1 (en) 2013-09-16 2015-02-17 Applied Materials, Inc. Selective etch of silicon nitride
US8951429B1 (en) 2013-10-29 2015-02-10 Applied Materials, Inc. Tungsten oxide processing
US9576809B2 (en) 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9236265B2 (en) 2013-11-04 2016-01-12 Applied Materials, Inc. Silicon germanium processing
US9711366B2 (en) 2013-11-12 2017-07-18 Applied Materials, Inc. Selective etch for metal-containing materials
US9520303B2 (en) 2013-11-12 2016-12-13 Applied Materials, Inc. Aluminum selective etch
US9472417B2 (en) 2013-11-12 2016-10-18 Applied Materials, Inc. Plasma-free metal etch
US9299582B2 (en) 2013-11-12 2016-03-29 Applied Materials, Inc. Selective etch for metal-containing materials
US9472412B2 (en) 2013-12-02 2016-10-18 Applied Materials, Inc. Procedure for etch rate consistency
US9245762B2 (en) 2013-12-02 2016-01-26 Applied Materials, Inc. Procedure for etch rate consistency
US9117855B2 (en) 2013-12-04 2015-08-25 Applied Materials, Inc. Polarity control for remote plasma
US9263278B2 (en) 2013-12-17 2016-02-16 Applied Materials, Inc. Dopant etch selectivity control
US9287095B2 (en) 2013-12-17 2016-03-15 Applied Materials, Inc. Semiconductor system assemblies and methods of operation
US9190293B2 (en) 2013-12-18 2015-11-17 Applied Materials, Inc. Even tungsten etch for high aspect ratio trenches
US9530856B2 (en) 2013-12-26 2016-12-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US9287134B2 (en) 2014-01-17 2016-03-15 Applied Materials, Inc. Titanium oxide etch
US9293568B2 (en) 2014-01-27 2016-03-22 Applied Materials, Inc. Method of fin patterning
US9396989B2 (en) 2014-01-27 2016-07-19 Applied Materials, Inc. Air gaps between copper lines
US9385028B2 (en) 2014-02-03 2016-07-05 Applied Materials, Inc. Air gap process
US9499898B2 (en) 2014-03-03 2016-11-22 Applied Materials, Inc. Layered thin film heater and method of fabrication
US9299575B2 (en) 2014-03-17 2016-03-29 Applied Materials, Inc. Gas-phase tungsten etch
US9299537B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9299538B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9837249B2 (en) 2014-03-20 2017-12-05 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9564296B2 (en) 2014-03-20 2017-02-07 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9136273B1 (en) 2014-03-21 2015-09-15 Applied Materials, Inc. Flash gate air gap
US9885117B2 (en) 2014-03-31 2018-02-06 Applied Materials, Inc. Conditioned semiconductor system parts
US9903020B2 (en) 2014-03-31 2018-02-27 Applied Materials, Inc. Generation of compact alumina passivation layers on aluminum plasma equipment components
US9269590B2 (en) 2014-04-07 2016-02-23 Applied Materials, Inc. Spacer formation
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9847289B2 (en) 2014-05-30 2017-12-19 Applied Materials, Inc. Protective via cap for improved interconnect performance
US9378969B2 (en) 2014-06-19 2016-06-28 Applied Materials, Inc. Low temperature gas-phase carbon removal
US9406523B2 (en) 2014-06-19 2016-08-02 Applied Materials, Inc. Highly selective doped oxide removal method
US9425058B2 (en) 2014-07-24 2016-08-23 Applied Materials, Inc. Simplified litho-etch-litho-etch process
US9773695B2 (en) 2014-07-31 2017-09-26 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9159606B1 (en) 2014-07-31 2015-10-13 Applied Materials, Inc. Metal air gap
US9496167B2 (en) 2014-07-31 2016-11-15 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9378978B2 (en) 2014-07-31 2016-06-28 Applied Materials, Inc. Integrated oxide recess and floating gate fin trimming
US9165786B1 (en) 2014-08-05 2015-10-20 Applied Materials, Inc. Integrated oxide and nitride recess for better channel contact in 3D architectures
US9659753B2 (en) 2014-08-07 2017-05-23 Applied Materials, Inc. Grooved insulator to reduce leakage current
US9553102B2 (en) 2014-08-19 2017-01-24 Applied Materials, Inc. Tungsten separation
US9355856B2 (en) 2014-09-12 2016-05-31 Applied Materials, Inc. V trench dry etch
US9368364B2 (en) 2014-09-24 2016-06-14 Applied Materials, Inc. Silicon etch process with tunable selectivity to SiO2 and other materials
US9355862B2 (en) 2014-09-24 2016-05-31 Applied Materials, Inc. Fluorine-based hardmask removal
US9478434B2 (en) 2014-09-24 2016-10-25 Applied Materials, Inc. Chlorine-based hardmask removal
US9478432B2 (en) 2014-09-25 2016-10-25 Applied Materials, Inc. Silicon oxide selective removal
US9613822B2 (en) 2014-09-25 2017-04-04 Applied Materials, Inc. Oxide etch selectivity enhancement
US9837284B2 (en) 2014-09-25 2017-12-05 Applied Materials, Inc. Oxide etch selectivity enhancement
US9299583B1 (en) 2014-12-05 2016-03-29 Applied Materials, Inc. Aluminum oxide selective etch
US9502258B2 (en) 2014-12-23 2016-11-22 Applied Materials, Inc. Anisotropic gap etch
US9343272B1 (en) 2015-01-08 2016-05-17 Applied Materials, Inc. Self-aligned process
US9373522B1 (en) 2015-01-22 2016-06-21 Applied Mateials, Inc. Titanium nitride removal
US9449846B2 (en) 2015-01-28 2016-09-20 Applied Materials, Inc. Vertical gate separation
US9728437B2 (en) 2015-02-03 2017-08-08 Applied Materials, Inc. High temperature chuck for plasma processing systems
US9881805B2 (en) 2015-03-02 2018-01-30 Applied Materials, Inc. Silicon selective removal
US9691645B2 (en) 2015-08-06 2017-06-27 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US9741593B2 (en) 2015-08-06 2017-08-22 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US9349605B1 (en) 2015-08-07 2016-05-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US9865484B1 (en) 2016-06-29 2018-01-09 Applied Materials, Inc. Selective etch using material modification and RF pulsing
US9721789B1 (en) 2016-10-04 2017-08-01 Applied Materials, Inc. Saving ion-damaged spacers
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US9947549B1 (en) 2016-10-10 2018-04-17 Applied Materials, Inc. Cobalt-containing material removal
US9768034B1 (en) 2016-11-11 2017-09-19 Applied Materials, Inc. Removal methods for high aspect ratio structures

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