TW201624641A - 半導體封裝體 - Google Patents

半導體封裝體 Download PDF

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Publication number
TW201624641A
TW201624641A TW104141252A TW104141252A TW201624641A TW 201624641 A TW201624641 A TW 201624641A TW 104141252 A TW104141252 A TW 104141252A TW 104141252 A TW104141252 A TW 104141252A TW 201624641 A TW201624641 A TW 201624641A
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semiconductor package
interposer
wafer
semiconductor
bonding surface
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TW104141252A
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許文松
林世欽
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聯發科技股份有限公司
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Publication of TW201624641A publication Critical patent/TW201624641A/zh

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    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L23/00—Details of semiconductor or other solid state devices
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Abstract

本揭露提供一種半導體封裝體，包括：基板結構，具有凹口，其中凹口之底表面係作為基板結構之晶片貼合面；半導體晶片，設於凹口中，且設於晶片貼合面上，其中凹口之側壁與半導體晶片隔開；及中介層，設於基板結構上，且覆蓋凹口。

Description

半導體封裝體
本揭露係有關於半導體封裝體，且特別係有關於一種層疊封裝之半導體封裝體。
層疊封裝之封裝體係為用以垂直結合分離之系統晶片(system-on-chip)及記憶體封裝結構之積體電路封裝方法。兩個或更多個封裝安裝在彼此頂上，亦即堆疊，且在兩個或多個封裝之間具有路由信號的標準介面。這使得在諸如行動電話、個人數位助理(PDA)和數位照相機的裝置中可實現更高的元件密度。
由於在底部之系統晶片封裝體之輸入/輸出連接之數量增加，很難減少上部之記憶體封裝體與底部之系統晶片封裝體之間的高度。
因此，業界仍須一種新穎之半導體封裝體。
本揭露提供一種半導體封裝體，包括：基板結構，具有凹口(cavity)，其中凹口之底表面係作為基板結構之晶片貼合面(die-attach surface)；半導體晶片，設於凹口中，且設於晶片貼合面上，其中凹口之側壁與半導體晶片隔開；及中介層(interposer)，設於基板結構上，且覆蓋凹口。
本揭露更提供一種半導體封裝體，包括：基板結 構，具有晶片貼合面(die-attach surface)、中介層貼合面(interposer-attach surface)及凸塊貼合面(bump-attach surface)，其中晶片貼合面及中介層貼合面係分別與凸塊貼合面為相反面；中介層(interposer)，設於基板結構之中介層貼合面上，其中基板結構與中介層共同形成容納空間(accommodation space)；及半導體晶片，設於容納空間中，且設於晶片貼合面上。
本揭露又提供一種半導體封裝體，包括：基板結構，具有晶片貼合面(die-attach surface)、中介層貼合面(interposer-attach surface)及凸塊貼合面(bump-attach surface)，其中晶片貼合面及中介層貼合面係分別與凸塊貼合面為相反面；中介層(interposer)，設於基板結構之中介層貼合面上，其中基板結構與中介層共同形成複合結構，此複合結構於剖面圖中具有圓環型(ring shape)；及半導體晶片，設於複合結構之中空空間(hollow space)中，且設於晶片貼合面上。
為讓本揭露之特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下。
200‧‧‧基材
202‧‧‧封裝表面
300‧‧‧半導體晶片
302‧‧‧頂表面
304‧‧‧底表面
306‧‧‧基板結構
308‧‧‧支撐部
310‧‧‧介電層
311‧‧‧側壁
312‧‧‧導電線路
314‧‧‧導孔
316‧‧‧導電墊
318‧‧‧導電墊
320‧‧‧底板部
322‧‧‧導電結構
324‧‧‧導電結構
326‧‧‧導電墊
328‧‧‧導電凸塊
330‧‧‧介電層
331‧‧‧外壁
332‧‧‧底表面
334‧‧‧中介層貼合面
340‧‧‧中介層
341‧‧‧側壁
342‧‧‧晶片貼合面
344‧‧‧凸塊貼合面
346‧‧‧導電電路
348‧‧‧介電層
350a‧‧‧系統晶片封裝結構
351‧‧‧背表面
352‧‧‧導電凸塊
354‧‧‧底部填充材料
360‧‧‧凹口
361‧‧‧底表面
362‧‧‧空間
364‧‧‧側壁
370‧‧‧鑄模化合物
371‧‧‧頂表面
380‧‧‧複合結構
400‧‧‧記憶體晶片
402‧‧‧導電墊
404‧‧‧接線
406‧‧‧鑄模材料
410‧‧‧記憶體封裝結構
500a‧‧‧半導體封裝體
500b‧‧‧半導體封裝體
500c‧‧‧半導體封裝體
第1圖係本揭露一些實施例之半導體封裝體之剖面圖。
第2圖係本揭露另一些實施例之半導體封裝體之剖面圖。
第3圖係本揭露另一些實施例之半導體封裝體之剖面圖。
第4A圖係顯示根據本揭露一些實施例所述之半導體封裝 體之製造方法其中一步驟之半導體封裝體之剖面圖。
第4B圖係顯示根據本揭露一些實施例所述之半導體封裝體之製造方法其中一步驟之半導體封裝體之剖面圖。
第4C圖係顯示根據本揭露一些實施例所述之半導體封裝體之製造方法其中一步驟之半導體封裝體之剖面圖。
以下描述用以實施本揭露之最佳實施例。然而，此描述僅是用以說明本揭露之原理，且並非用以限制本揭露之範圍。本揭露之範圍係以申請專利範圍決定。
以下的揭露內容提供許多不同的實施例或範例以及圖式，然而，這些僅是用以說明本揭露之原理，且並非用以限制本揭露之範圍。本揭露之範圍係以申請專利範圍決定。本揭露之圖式僅為說明之用，且並非用以限定本揭露之範圍。在圖式中，為了清楚說明本揭露，部分元件之尺寸可能被放大且並未照實際比例繪製。此尺寸以及相對之尺寸並未對應實施本揭露時之實際尺寸。
本揭露之一些實施例提供一具有層疊封裝結構(package-on-package structure)之半導體封裝體。此半導體封裝體包括一凹口基板以及設於其上之中介層。此凹口基板係用以將系統晶片(system on chip die)設於其凹口中。而上述中介層係用以將記憶體晶片接合於其上。使用此凹口基板之半導體封裝體可達到低成本、高帶寬(high bandwidth)、低功率及快速轉換之需求。
第1圖係本揭露一些實施例之半導體封裝體500a 之剖面圖。在本揭露一些實施例中，此半導體封裝體500a包括系統晶片(system-on-chip)封裝結構350a及堆疊於其上之記憶體封裝結構410。在本揭露一些實施例中，此半導體封裝體500a為層疊封裝半導體封裝體。此半導體封裝體500a包括至少兩個垂直堆疊且設於基材200上之晶圓級(wafer-level)半導體封裝體。
如第1圖所示，例如為印刷電路板之基材200可包括聚丙烯(polypropylene)。應注意的是，基材200可為單層結構或多層結構。多個導電墊(未繪示)及/或導電線路(conductive trace)(未繪示)設於基材200之封裝表面202上。在本揭露一些實施例中，導電線路可包括電源線路部分、訊號線路部分、或接地線路部分，此導電線路係用作系統晶片封裝結構350a及記憶體封裝結構410之輸入/輸出連接。此外，系統晶片封裝結構350a可直接設於導電線路上。在本揭露其它一些實施例中，導電墊係設於封裝表面202上，並連接至導電線不同的末端。系統晶片封裝結構350a可直接設於此導電墊上。
如第1圖所示，系統晶片封裝結構350a係藉由接合步驟設於基材200之封裝表面202上。此系統晶片封裝結構350a係藉由導電結構322設於基材200上。此系統晶片封裝結構350a包括基板結構306與接合於基板結構306上之半導體晶片300。在本揭露一些實施例中，此半導體晶片300為系統晶片。
如第1圖所示，基板結構306具有中介層貼合面(interposer-attach surface)334及與此中介層貼合面334互為相反面之凸塊貼合面(bump-attach surface)304。基板結構306 具有凹口(cavity)360，此凹口360係自中介層貼合面334向下延伸至部分基板結構306中。此凹口360係大抵位於此基板結構306之中間部分。此凹口360之底表面361亦作為基板結構306之晶片貼合面。
如第1圖所示，基板結構306包括底板部(plate portion)320及支撐部308。此底板部320具有平坦之頂表面302及平坦之底表面。此底板部320之底表面亦為基板結構306之凸塊貼合面304。底表面361為底板部320之頂表面302之一部分。在本揭露一些實施例中，底板部320可包括核心基板(core substrate)或無核心基板(coreless substrate)。在本揭露一些實施例中，如第1圖所示，底板部320為無核心基板。此底板部320包括額外之電路結構，此額外之電路結構包括一或多個介電層310、導電線路312(conductive trace)、導孔314及導電墊316及318。在本揭露一些實施例中，介電層310係以包括預浸漬材料(”預浸漬”複合纖維)(prepreg("pre-impregnated" composite fibers)、聚亞醯胺、味之素组成薄膜(Ajinomoto build-up film，ABF)、聚對苯撐苯並雙噁唑(poly-p-phenylenebenzobisthiazole，PBO)、聚丙烯(polypropylene，PP)或鑄模化合物的材料形成。上述導電線路312及導孔314係藉由雷射沖孔步驟(laser drilling process)、鍍膜步驟及微影蝕刻步驟設於介電層310中。導電墊316及318係藉由鍍膜步驟及微影蝕刻步驟分別設於鄰近頂表面302與底表面304之部分。此導電墊316及318電性連接至上述導電線路312及導孔314。此外，鄰近底表面304之導電墊318電性連接至 導電結構322。在本揭露一些實施例中，導電線路312、導孔314及導電墊316及318係由包括銅之金屬形成。
如第1圖所示，支撐部308係設於底板部320之頂表面302上。支撐部308具有一頂表面，此頂表面亦為基板結構306之中介層貼合面334。支撐部308亦具有一底表面332，此底表面332接觸底板部320之頂表面302。因此，底表面361(頂表面302之一部分)與基板結構306之中介層貼合面334並不共平面。此支撐部308環繞底板部320之周邊區以形成穿過此支撐部308之凹口360。底表面332接觸此底板部320之頂表面302的周邊區。易言之，支撐部308並未覆蓋底板部320之頂表面302對應底表面361之部分。此外，支撐部308之外壁331與底板部320之側壁311對齊。此外，支撐部308之內壁364係作為凹口360之側壁364。
如第1圖所示，支撐部308包括介電層330以及至少一個穿過介電層330之導電結構324。在本揭露一些實施例中，介電層330為單層結構。此外，介電層330係以包括預浸漬材料(”預浸漬”複合纖維)(prepreg("pre-impregnated" composite fibers)、聚亞醯胺、味之素组成薄膜(Ajinomoto build-up film，ABF)、聚對苯撐苯並雙噁唑(poly-p-phenylenebenzobisthiazole，PBO)、聚丙烯(polypropylene，PP)或鑄模化合物的材料形成。在本揭露一些實施例中，底板部320之介電層310及支撐部308之介電層330可由相同材料形成。導電結構324係電性連接至底板部320之導電墊316。在本揭露一些實施例中，導電結構324包括導孔、導電柱、或焊接球。在本揭露一些實施例中， 導電結構324係由包括銅或焊材之金屬形成。在本揭露一些實施例中，如第1圖所示，當導電結構324為銅導孔時，支撐部308更包括導電墊326及設於此導電墊326上之導電凸塊328。此導電墊326及導電凸塊328係設於支撐部308之頂表面上(亦即基板結構306之中介層貼合面334)，且此導電墊326及導電凸塊328係電性連接至導電結構324。在本揭露一些實施例中，導電凸塊328包括預焊材料(pre-solder)、導電柱、或焊接球。
如第1圖所示，半導體晶片300係設於凹口360中，且設於基板結構306之底表面361上。於第1圖所示之剖面圖中，此半導體晶片300之寬度可設計為小於凹口360之寬度。在本揭露一些實施例中，凹口360之側壁364與半導體晶片300隔開。此外，於第1圖所示之剖面圖中，基板結構306之中介層貼合面334與半導體晶片300橫向隔開(laterally separate)。在本揭露一些實施例中，半導體晶片300為包括邏輯晶片之半導體晶片300。此邏輯晶片包括中央處理單元(CPU)、圖形處理單元(GPU)、動態隨機存取記憶體(DRAM)控制器、或上述之組合。應注意的事，半導體晶片300之數量並不限於所述之實施例。在本揭露一些實施例中，此半導體晶片300可由矽穿孔技術或覆晶技術製得。在此實施例中，半導體晶片300係由覆晶技術製得。因此，半導體晶片300具有遠離底表面361之背表面351。在本揭露一些實施例中，半導體晶片300之背表面351係與基板結構306之中介層貼合面334齊平，或低於基板結構306之中介層貼合面334。此半導體晶片300藉由導電凸塊352電性連接至基板結構306之導電墊316。導電凸塊352係設於半導體 晶片300與導電墊316之間。在本揭露一些實施例中，導電凸塊352可包括銅凸塊或焊材凸塊。
如第1圖所示，系統晶片封裝結構350a更包括填入半導體晶片300與基板結構306之間的間隙之底部填充材料354。此底部填充材料354覆蓋基板結構306之底表面361的一部分。在本揭露一些實施例中，底部填充材料354可包括毛細底部填充材料(capillary underfill，CUF)、封模底部填充材料(molded underfill，MUF)、或上述之組合。
如第1圖所示，半導體封裝體500a更包括堆疊於系統晶片封裝結構350a上之記憶體封裝結構410。在本揭露一些實施例中，記憶體封裝結構410包括引線接合封裝(wire bonding package)、貫孔導孔(矽穿孔)封裝(through hole via(TSV)package)或覆晶封裝。在此實施例中，記憶體封裝結構410為引線接合封裝。或者，記憶體封裝結構410可包括由多個記憶體晶片垂直堆疊形成之三維半導體封裝結構。此記憶體封裝結構410包括中介層340以及至少一個接合於此中介層340上之記憶體晶片400。此中介層340係接合於基板結構306之支撐部308。此外，中介層340完全覆蓋凹口360與基板結構306之中介層貼合面334。此中介層340具有晶片貼合面342及凸塊貼合面344，此晶片貼合面342及凸塊貼合面344互為相反面。此晶片貼合面342係用以貼合記憶體晶片400。此凸塊貼合面344係用以將導電結構322接合至基板結構306之中介層貼合面334。
在本揭露一些實施例中，中介層340可包括核心基 板(core substrate)或無核心基板(coreless substrate)。中介層340之側壁341大抵與支撐部308之外壁331及底板部320之側壁311對齊。在本揭露一實施例中，如第1圖所示，中介層340為無核心基板。中介層340包括額外之電路結構(circuit structure)，此額外之電路結構包括一或多個介電層348以及設於此介電層348中之導電電路346(conductive circuit)。在本揭露一些實施例中，導電電路346可包括導電線路(conductive trace)、導孔及導電墊。在本揭露一些實施例中，中介層340之組成(composition)與底板部320之組成相似。例如，中介層340之介電層348可與底板部320之介電層310相似。此中介層340之導電電路346可包括導電線路、導孔及導電墊，其與底板部320之導電線路312、導孔314及導電墊316及318相似。在本揭露一些實施例中，如第1圖所示，中介層340之導電電路346電性連接至其對應之導電凸塊328，此導電凸塊328設於支撐部308上且具有一高度。因此，可於中介層340與基板結構306之間形成一空間362。此外，此空間362可形成於多個導電凸塊328之間。
在本揭露一些實施例中，如第1圖所示，基板結構306與中介層340共同形成容納空間(accommodation space)，此容納空間包括上述位於基板結構306之中央部的凹口360。半導體晶片300係設於包括凹口360之容納空間中，且設於基板結構306之底表面361上。易言之，基板結構306與接合於其上之中介層340共同形成複合結構380。於第1圖所示之剖面圖中，此複合結構380大抵具有圓環型(ring shape)。在本揭露一些 實施例中，如第1圖所示，複合結構380可具有中空空間(hollow space)，此中空空間包括上述位於基板結構306之中央部的凹口360。半導體晶片300係設於包括凹口360之中空空間中，且設於基板結構306之底表面361上。
在本揭露一些實施例中，記憶體晶片400可包括遵守特定引腳分配規則(例如JEDEC低功率雙數據速率輸入/輸出記憶體標準，JEDEC LPDDR I/O Memory specification)之低功率雙數據速率動態隨機存取記憶體封裝體(low-power double data rate DRAM)、或遵守另一特定引腳分配規則(例如JEDEC寬輸入輸出記憶體標準，JEDEC Wide I/O Memory specification)之寬輸入輸出動態隨機存取記憶體。此記憶體晶片400係藉由一黏膠(未繪示)貼合至晶片貼合面342上。此記憶體晶片400藉由接線404偶接至中介層340。接線404之末端電性連接至記憶體晶片400之導電墊402以及對應之中介層340之導電電路346。此記憶體晶片400更包括鑄模材料(molding material)406，此鑄模材料406覆蓋中介層340之晶片貼合面342，且封裝記憶體晶片400及接線404。
第2圖係本揭露另一些實施例之半導體封裝體500b之剖面圖。應注意的是，後文中與前文相同或相似的元件或膜層將以相同或相似於第1圖之標號表示，其材料、製造方法與功能皆與前文所述相同或相似，故此部分在後文中將不再贅述。半導體封裝體500a與半導體封裝體500b之差異在於半導體封裝體500b包括鑄模化合物370(molding compound)，此鑄模化合物370填入凹口360且填入半導體晶片300與基板結構 306之間的間隙。鑄模化合物370與半導體晶片300、凹口360之側壁364及基板結構306之底表面361直接接觸。此鑄模化合物370與中介層340之凸塊貼合面344隔開。在此實施例中，半導體晶片300遠離底表面361之背表面351係自鑄模化合物370暴露出來。半導體晶片300之背表面351可對齊鑄模化合物370遠離底表面361之頂表面371。此外，鑄模化合物370之頂表面371可對齊基板結構306之中介層貼合面334。
第3圖係本揭露另一些實施例之半導體封裝體500c之剖面圖。應注意的是，後文中與前文相同或相似的元件或膜層將以相同或相似於第1-2圖之標號表示，其材料、製造方法與功能皆與前文所述相同或相似，故此部分在後文中將不再贅述。半導體封裝體500a與半導體封裝體500c之差異在於半導體封裝體500c包括鑄模化合物372，此鑄模化合物372填入凹口360且填入半導體晶片300與基板結構306之間的間隙。鑄模化合物372與半導體晶片300、凹口360之側壁364、基板結構306之底表面361及中介層340之凸塊貼合面344直接接觸。在此實施例中，鑄模化合物372完全覆蓋半導體晶片300。因此，半導體晶片300遠離底表面361之背表面351係被模化合物372完全覆蓋。此外，鑄模化合物372填入中介層340與基板結構306之間的空間362。在此實施例中，鑄模化合物372亦圍繞導電墊326上之導電凸塊328。
半導體封裝體500a-500c使用具有凹口之基板結構，並將半導體晶片設於此凹口中。此具有凹口之基板結構可提供較小的垂直高度。基板結構之支撐部可提供系統晶片封裝結構 與記憶體封裝結構之間的額外的內連線。此外，基板結構之底板部可由無核心基板形成，以更進一步減少垂直高度以及製程成本。使用此凹口基板之半導體封裝體可達到低成本、高帶寬(high bandwidth)、低功率及快速轉換之需求。
第4A-4C圖係本揭露實施例之半導體封裝體500a-500c在其製造方法中各階段的剖面圖。應注意的是，後文中與前文相同或相似的元件或膜層將以相同或相似之標號表示，其材料、製造方法與功能皆與前文所述相同或相似，故此部分在後文中將不再贅述。
如第4A圖所示，提供一載板(未繪示)，並使基板結構306形成於其上。接著，進行一層疊步驟以將底板部320之一或多層介電層310形成於載板上。接著，進行一沖孔步驟以形成貫穿介電層310之開口(未繪示)，以定義後續之導孔314形成之位置。在本揭露一些實施例中，沖孔步驟可包括雷射沖孔步驟(laser drilling process)、蝕刻沖孔步驟或機械沖孔步驟。接著，進行鍍膜步驟、微影蝕刻步驟及非等向性蝕刻步驟以將導電材料填入開口中以形成底板部320之導電線路312、導孔314及導電墊316及318。在本揭露一些實施例中，鍍膜步驟可包括電鍍步驟。
接著，如第4A圖所示，將支撐部308形成於底板部320之頂表面302上。形成支撐部308之步驟可與形成底板部320之步驟相似。在本揭露一些實施例中，支撐部308與底板部320可各自獨立地形成，接著再將支撐部308設於底板部320上，以藉由此層疊步驟形成基板結構306。
然而，在其它一些實施例中，如第4A圖所示，包括介電層330、導電結構324及/或導電墊326的一塊基板係藉由層疊步驟設於底板部320上。接著，進行微影蝕刻步驟以及非等向性蝕刻步驟以移除此塊基板之中間部分，並形成設於底板部320上之支撐部308。於前述步驟之後，便形成具有凹口360之基板結構306。
接著，如第4B圖所示，翻轉半導體晶片300並將其設於凹口360中。此半導體晶片300係藉由接合步驟設於基板結構306之底表面361上。半導體晶片300係透過導電凸塊352電性連接至基板結構306之導電墊316。
接著，如第4B圖所示，將中介層340接合至基板結構306之支撐部308上。形成中介層340之步驟可與形成底板部320與支撐部308之步驟相似。在本揭露一些實施例中，於接合中介層340之前，導電凸塊328可形成於對應之基板結構306之導電墊326上。中介層340之導電電路346可電性連接至對應之導電凸塊328。
接著，進行後續之步驟以形成第1-3圖所示之半導體封裝體500a-500c。在本揭露一些實施例中，如第1圖所示，於接合中介層340後，底部填充材料354可填入半導體晶片300與基板結構306之間的間隙。或者，可進行一塗佈步驟以將鑄模化合物370或371填入凹口360且填入半導體晶片300與基板結構306之間的間隙，如第2-3圖所示。於進行前述步驟之後，便形成系統晶片封裝結構350a。
於形成第1圖所示之底部填充材料354或第2-3圖所 示之鑄模化合物370或371，可藉由焊接球製造步驟或銅柱製造步驟形成導電結構322於基板結構306之凸塊貼合面304上，如第1-3圖所示。在本揭露一些實施例中，如第1-3圖所示，導電結構322電性連接至對應之導電墊318。
於形成導電結構322於基板結構306之凸塊貼合面304上後，如第1-3圖所示，記憶體晶片400係藉由黏膠(未繪示)貼附於晶片貼合面342上。接著，進行一接合步驟，記憶體晶片400藉由接線404偶接至中介層340，如第1-3圖所示。接著，進行鑄模步驟以形成鑄模材料406，此鑄模材料406覆蓋中介層340之晶片貼合面342，且封裝記憶體晶片400及接線404，如第1-3圖所示。在本揭露一些實施例中，鑄模步驟可包括轉印成模步驟(transfer molding process)、片狀成模步驟(sheet molding process)、或模壓成模步驟(compression molding process)。於進行鑄模步驟後，便形成記憶體封裝結構410。
本揭露之一些實施例提供一具有層疊封裝結構(package-on-package structure)之半導體封裝體及其製造方法。此半導體封裝體包括一凹口基板以及設於其上之中介層。此凹口基板係用以將系統晶片(system on chip die)設於其凹口中，故可減小此半導體封裝體的垂直高度。基板結構之支撐部可提供系統晶片封裝結構與記憶體封裝結構之間的額外的內連線。而中介層係接合於基板結構之中介層貼合面上，且此中介層係用以將記憶體晶片接合於其上。基板結構與接合於其上之中介層共同形成複合結構，此複合結構之剖面圖大抵具有圓環型，如第1-3圖所示。易言之，複合結構可具有中空空間 (hollow space)，此中空空間包括上述位於基板結構之中央部的凹口。半導體晶片係設於包括凹口之中空空間中。因此，晶片貼合面與基板結構之中介層貼合面並不共平面。使用此凹口基板之半導體封裝體可達到低成本、高帶寬(high bandwidth)、低功率及快速轉換之需求。
雖然本揭露的實施例及其優點已揭露如上，但應該瞭解的是，任何所屬技術領域中具有通常知識者，在不脫離本揭露之精神和範圍內，當可作更動、替代與潤飾。此外，本揭露之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本揭露揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大抵相同功能或獲得大抵相同結果皆可根據本揭露使用。因此，本揭露之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本揭露之保護範圍也包括各個申請專利範圍及實施例的組合。
200‧‧‧基材
202‧‧‧封裝表面
300‧‧‧半導體晶片
302‧‧‧頂表面
304‧‧‧底表面
306‧‧‧基板結構
308‧‧‧支撐部
310‧‧‧介電層
311‧‧‧側壁
312‧‧‧導電線路
314‧‧‧導孔
316‧‧‧導電墊
318‧‧‧導電墊
320‧‧‧底板部
322‧‧‧導電結構
324‧‧‧導電結構
326‧‧‧導電墊
328‧‧‧導電凸塊
330‧‧‧介電層
331‧‧‧外壁
332‧‧‧底表面
334‧‧‧中介層貼合面
340‧‧‧中介層
341‧‧‧側壁
342‧‧‧晶片貼合面
344‧‧‧凸塊貼合面
346‧‧‧導電電路
348‧‧‧介電層
350a‧‧‧系統晶片封裝結構
351‧‧‧背表面
352‧‧‧導電凸塊
354‧‧‧底部填充材料
360‧‧‧凹口
361‧‧‧底表面
362‧‧‧空間
364‧‧‧側壁
380‧‧‧複合結構
400‧‧‧記憶體晶片
402‧‧‧導電墊
404‧‧‧接線
406‧‧‧鑄模材料
410‧‧‧記憶體封裝結構
500a‧‧‧半導體封裝體

Claims (29)

  1. 一種半導體封裝體，包括：一基板結構，具有一凹口(cavity)，其中該凹口之底表面係作為該基板結構之一晶片貼合面(die-attach surface)；一半導體晶片，設於該凹口中，且設於該晶片貼合面上，其中該凹口之側壁與該半導體晶片隔開；及一中介層(interposer)，設於該基板結構上，且覆蓋該凹口。
  2. 如申請專利範圍第1項所述之半導體封裝體，其中該基板結構包括：一底板部(plate portion)，具有一頂表面及一底表面，其中該晶片貼合面為該底板部之該頂表面之一部分；及一支撐部，設於該底板部之該頂表面上，且圍繞該半導體晶片，其中該支撐部之內壁為該凹口之側壁。
  3. 如申請專利範圍第2項所述之半導體封裝體，更包括：一底部填充材料，填入該半導體晶片與該基板結構之間的一間隙。
  4. 如申請專利範圍第2項所述之半導體封裝體，更包括：一鑄模化合物(molding compound)，填入該凹口，且與該半導體晶片直接接觸。
  5. 如申請專利範圍第4項所述之半導體封裝體，其中該半導體晶片遠離該晶片貼合面之一表面係自該鑄模化合物暴露出來。
  6. 如申請專利範圍第4項所述之半導體封裝體，其中該鑄模 化合物完全覆蓋該半導體晶片。
  7. 如申請專利範圍第6項所述之半導體封裝體，其中該鑄模化合物填入該中介層與該基板結構之間的空間。
  8. 如申請專利範圍第2項所述之半導體封裝體，其中該半導體晶片遠離該晶片貼合面之一表面係與該支撐部遠離該晶片貼合面之一表面齊平，或低於該支撐部遠離該晶片貼合面之該表面。
  9. 如申請專利範圍第2項所述之半導體封裝體，其中該底板部及該中介層包括一核心基板(core substrate)或一無核心基板(coreless substrate)。
  10. 如申請專利範圍第2項所述之半導體封裝體，其中該底板部包括一額外之電路結構，該額外之電路結構包括一介電層以及設於該介電層中之一導電線路(conductive trace)。
  11. 如申請專利範圍第10項所述之半導體封裝體，其中該支撐部包括一介電層以及穿過該介電層之一導電結構。
  12. 如申請專利範圍第11項所述之半導體封裝體，其中該底板部之該介電層及該支撐部之該介電層係以包括預浸漬材料(”預浸漬”複合纖維)(prepreg("pre-impregnated" composite fibers)、聚亞醯胺、味之素组成薄膜(Ajinomoto build-up film，ABF)、聚對苯撐苯並雙噁唑(poly-p-phenylenebenzobisthiazole)、聚丙烯(polypropylene)或鑄模化合物的材料形成。
  13. 如申請專利範圍第11項所述之半導體封裝體，其中該導電結構包括一導孔、一導電柱、或一焊接球。
  14. 如申請專利範圍第2項所述之半導體封裝體，其中該中介層係接合於該支撐部上。
  15. 如申請專利範圍第2項所述之半導體封裝體，其中該支撐部之外壁與該底板部之側壁及該中介層之側壁對齊。
  16. 一種半導體封裝體，包括：一基板結構，具有一晶片貼合面(die-attach surface)、一中介層貼合面(interposer-attach surface)及一凸塊貼合面(bump-attach surface)，其中該晶片貼合面及該中介層貼合面係分別與該凸塊貼合面為相反面；一中介層(interposer)，設於該基板結構之該中介層貼合面上，其中該基板結構與該中介層共同形成一容納空間(accommodation space)；及一半導體晶片，設於該容納空間中，且設於該晶片貼合面上。
  17. 如申請專利範圍第16項所述之半導體封裝體，其中該晶片貼合面與該中介層貼合面並不共平面。
  18. 如申請專利範圍第16項所述之半導體封裝體，其中該中介層貼合面與該半導體晶片橫向隔開(laterally separate)。
  19. 如申請專利範圍第16項所述之半導體封裝體，其中該基板結構包括：一底板部(plate portion)，具有一頂表面及一底表面，其中該晶片貼合面為該底板部之該頂表面之一部分；及一支撐部，具有一頂表面及一底表面分別連接該中介層及該底板部之底表面，其中該支撐部之該頂表面為該中介層 貼合面。
  20. 如申請專利範圍第19項所述之半導體封裝體，更包括：一底部填充材料，填入該半導體晶片與該基板結構之間的一間隙。
  21. 如申請專利範圍第19項所述之半導體封裝體，更包括：一鑄模化合物(molding compound)，填入該凹口，且與該半導體晶片直接接觸。
  22. 如申請專利範圍第21項所述之半導體封裝體，其中該半導體晶片遠離該晶片貼合面之一表面係自該鑄模化合物暴露出來。
  23. 如申請專利範圍第21項所述之半導體封裝體，其中該鑄模化合物完全覆蓋該半導體晶片。
  24. 如申請專利範圍第23項所述之半導體封裝體，其中該鑄模化合物填入該中介層與該基板結構之間的空間。
  25. 如申請專利範圍第19項所述之半導體封裝體，其中該底板部與該支撐部各自分別包括一介電層。
  26. 如申請專利範圍第25項所述之半導體封裝體，其中該介電層係以包括預浸漬材料(”預浸漬”複合纖維)(prepreg ("pre-impregnated" composite fibers)、聚亞醯胺、味之素组成薄膜(Ajinomoto build-up film，ABF)、聚對苯撐苯並雙噁唑(poly-p-phenylenebenzobisthiazole)、聚丙烯(polypropylene)或鑄模化合物的材料形成。
  27. 如申請專利範圍第25項所述之半導體封裝體，其中該支撐部包括穿過該介電層之一導電結構，其中該導電結構包括 一導孔、一導電柱、或一焊接球。
  28. 如申請專利範圍第19項所述之半導體封裝體，其中該支撐部之內壁係與該半導體晶片之側壁隔開。
  29. 如申請專利範圍第19項所述之半導體封裝體，其中該支撐部之外壁與該底板部之側壁及該中介層之側壁對齊。
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