TWI778560B - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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Publication number
TWI778560B
TWI778560B TW110111436A TW110111436A TWI778560B TW I778560 B TWI778560 B TW I778560B TW 110111436 A TW110111436 A TW 110111436A TW 110111436 A TW110111436 A TW 110111436A TW I778560 B TWI778560 B TW I778560B
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Taiwan
Prior art keywords
substrate
chip
groove
control element
package structure
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TW110111436A
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English (en)
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TW202238859A (zh
Inventor
周佩勲
廖克綸
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力成科技股份有限公司
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Priority to TW110111436A priority Critical patent/TWI778560B/zh
Priority to US17/407,174 priority patent/US11848318B2/en
Application granted granted Critical
Publication of TWI778560B publication Critical patent/TWI778560B/zh
Publication of TW202238859A publication Critical patent/TW202238859A/zh

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Abstract

本發明提供一種封裝結構及其製造方法。封裝結構包括基底、晶片、控制元件以及底部填充材料。晶片設置於基底上，其中晶片包括一凹槽，且凹槽具有底面以及側壁。控制元件設置於基底與晶片之間且設置在凹槽的底面，其中控制元件與凹槽的側壁之間存在一間隙。底部填充材料設置在凹槽中。其中晶片與控制元件分別電連接基底。

Description

封裝結構及其製造方法
本發明涉及一種封裝結構及其製造方法，特別是涉及一種包含凹槽的封裝結構及其製造方法。
近年來，隨著電子裝置中的電子元件逐漸趨向小型化與高密集化，為此發展出整合多個電子元件或積體電路的多重封裝體(hybrid package)之封裝技術。
在現行多重封裝體的製造過程中，往往會透過設置數個支撐體(spacer)支撐電子元件，以增加封裝體整體的結構穩定性。然而，由於此方式需設置並黏接支撐體，使得製程站點(例如黏晶製程)的次數增加，導致製程耗費較多時間、用料成本較高。此外，隨著站點的增加，亦使得製程問題產生的機率提高。
本發明的目的之一在於提供一種封裝結構及其製造方法，其可達到簡化製造流程、提升生產效率以及降低製造成本的功效，同時可減少製程問題 產生並提升元件散熱效果。
為達上述目的，本發明提供一種封裝結構，包括基底、晶片、控制元件以及底部填充材料。晶片設置於基底上，其中晶片包括一凹槽，且凹槽具有底面以及側壁。控制元件設置於基底與晶片之間且設置在凹槽的底面，其中控制元件與凹槽的側壁之間存在一間隙。底部填充材料設置在凹槽中。其中晶片與控制元件分別電連接基底。
為達上述目的，本發明提供一種封裝結構的製造方法，包括：在一晶圓形成複數個溝槽；將複數個控制元件貼附於各溝槽的底面，其中各控制元件與對應的各溝槽的側壁之間存在一間隙；對晶圓進行一切割製程以形成複數個封裝單元，其中各封裝單元包括晶片以及一個控制元件，其中晶片包括一凹槽，且凹槽為該等溝槽的其中一個的一部分；將該等封裝單元的其中一個設置在基底上，其中封裝單元的控制元件位於基底與封裝單元的晶片之間；以及在凹槽中填入底部填充材料。
根據本發明的封裝結構及其製造方法，透過將控制元件設置在晶片的凹槽以及將晶片連同控制元件設置在基底上，可增加封裝結構的穩定性，並達到簡化製造流程、提升生產效率以及降低製造成本的功效，且可進一步減少製程問題產生。並且，透過先將控制元件設置在晶片的凹槽中，再將晶片連同控制元件設置在基底上，可保護控制元件，以避免其在設置至基底時因外力而造成損壞。此外，透過使控制元件與晶片之間存在間隙，並填入底部填充材料，可提升元件散熱效果，且在凹槽中填入底部填充材料，可避免結構內部殘留氣體，進而提升結構的機械強度與可靠度。
100,100’,100”:封裝結構
100U,100U’:封裝單元
110:晶圓
1101:第一表面
1102:第二表面
112:溝槽
112B,142B:底面
112S,142S:側壁
114,144:主動層
120:控制元件
122:焊球
130:黏接層
130a:熱固型高分子膠
140:晶片
142:凹槽
146:本體部
148:突出部
148S:表面
150:基底
152:金屬層
154:絕緣層
156:導電墊
158:導電端子
160:導線
170:底部填充材料
180,130b:晶片黏結膜層
190,190a:封膠材料
BS:交界面
C:切割製程
CL:切割線
D:間距
D1:第一方向
D2:第二方向
D3:第三方向
G:間隙
T:厚度
第1A圖、第1B圖以及第2圖至第5圖為本發明一實施例的封裝結構的製造方法的製程示意圖。
第6圖為本發明變化實施例的封裝單元的剖面示意圖。
第7圖為本發明另一實施例的封裝結構的剖視示意圖。
第8圖為本發明另一實施例的封裝結構的製造方法的製程示意圖。
透過參考以下的詳細描述並同時結合圖式可以理解本發明，須注意的是，為了使讀者能容易瞭解及圖式的簡潔，本發明的圖式只繪出封裝結構的至少一部分或製造封裝結構的步驟中的至少一部分，且圖式中的特定元件並非依照實際比例繪圖。此外，圖式中各元件的數量及尺寸僅作為示意，並非用來限制本發明的範圍。
本發明通篇說明書與所附的申請專利範圍中會使用某些術語來指稱特定元件。本領域技術人員應理解，電子設備製造商可能會以不同的名稱來指稱相同的元件。本文並不意在區分那些功能相同但名稱不同的元件。在下文說明書與申請專利範圍中，「含有」與「包括」等詞為開放式詞語，因此其應被解釋為「含有但不限定為…」之意。當在本說明書中使用術語「包含」、「包括」及/或「具有」時，其指定了所述特徵、區域、步驟、操作和/或元件的存在，但並不排除一個或多個其他特徵、區域、步驟、操作、元件及/或其組合的存在或增加。
當元件或膜層被稱為在另一個元件或膜層「上」或「連接到」另一個元件或膜層時，它可以直接在此另一元件或膜層上或直接連接到此另一元件或膜層，或者兩者之間存在有插入的元件或膜層。相反地，當元件被稱為「直接」在另一個元件或膜層「上」或「直接連接到」另一個元件或膜層時，兩者之間不存在有插入的元件或膜層。
須知悉的是，以下所舉實施例可以在不脫離本發明的精神下，將數個不同實施例中的技術特徵進行替換、重組、混合以完成其他實施例。
第1A圖、第1B圖以及第2圖至第5圖為本發明一實施例的封裝結構的製造方法的製程示意圖。本發明一實施例的封裝結構100的製造方法將搭配第1A圖、第1B圖以及第2圖至第5圖描述於下文中，但不以此為限。在一些實施例中，可根據需求增加或刪除步驟。
如第1A圖及第1B圖所示，首先提供一晶圓110，在晶圓110表面形成複數個溝槽112，其中第1A圖為晶圓110的俯視示意圖，第1B圖為晶圓110的部分側視示意圖，可例如透過蝕刻製程、微影製程、雷射製程或其他合適的製程於晶圓110形成複數個溝槽112。晶圓110可包括位在相對兩側的第一表面1101以及第二表面1102，其中第二表面1102係為設有主動層(active layer)114的表面，主動層114例如包括導線、連接元件等，但不以此為限。根據本發明，可在與第二表面1102相對的第一表面1101(例如為晶圓110的晶背)形成複數個溝槽112，其中複數個溝槽112可沿第一方向D1彼此間隔排列，各溝槽112可在晶圓110的第一表面1101上沿第二方向D2延伸，且各溝槽112在垂直於第一表面1101的第三方 向D3上可具有一深度d。在一些實施例中，第一方向D1、第二方向D2與第三方向D3可彼此互相垂直，但不以此為限。如第1B圖所示，各溝槽112分別具有底面112B與側壁112S。
接著，如第2圖所示，將複數個控制元件120貼附於各溝槽112的底面112B，其中各控制元件120與對應的各溝槽112的側壁112S之間存在一間隙G。舉例而言，在一個溝槽112中，可將多個控制元件120沿著第一方向D1與第二方向D2彼此間隔地貼附在溝槽112的底面112B，例如此些控制元件120在溝槽112中可沿第一方向D1與第二方向D2排列成陣列，亦即一溝槽112內可容置多個控制元件120，但並不以此為限。在本實施例中，可透過一黏接層130將各控制元件120貼附於各溝槽112的底面112B，其中黏接層130可例如為熱固型高分子膠(thermosetting polymer adhesive)、晶片黏結膜層(die attach film,DAF)或其他合適的材料，但不以此為限。本實施例是以黏接層130為熱固型高分子膠130a為例。在將控制元件120貼附於溝槽112的底面112B的步驟中，可先將熱固型高分子膠130a形成在溝槽112的底面112B以及控制元件120之間，而後再經由自然烘乾或加熱硬化等方式使熱固型高分子膠130a固化，以透過熱固型高分子膠130a將控制元件120貼附固定於溝槽112的底面112B，但不以此為限。
然後，如第2圖與第3圖所示，對晶圓110進行一切割製程C以形成複數個封裝單元100U，各封裝單元100U包括晶片140以及一個控制元件120，其中晶片140包括凹槽142，且凹槽142為該等溝槽112的其中一個的一部分。舉例而言，可沿數條切割線CL進行切割製程C以形成複數個封裝單元100U，其中切割製程C舉例為(但不限於)機械切割製程、雷射切割製程或其他合適的切割製程。如第3圖所示，封裝單元100U包括晶片140以及控制元件120，其中晶片140可為 晶圓110的一部分且包括主動層144，其中主動層144為晶圓110的主動層114的一部分。晶片140還包括本體部146以及二個突出部148，且二個突出部148分別由本體部146的兩側延伸而出，以定義出凹槽142。因此，凹槽142的側壁142S亦即突出部148的側壁。
接著，如第4圖所示，將該等封裝單元100U的其中一個設置在基底150上，其中封裝單元100U的控制元件120位於基底150與封裝單元100U的晶片140之間。將包含晶片140與控制元件120的封裝單元100U作為一體翻轉設置在基底150上，亦即晶片140的凹槽142的開口朝下設置，以使控制元件120位於基底150與晶片140之間，此設計可保護控制元件120，以避免其在設置時因外力而造成損壞。基底150可為任何可用來承載或設置電子元件的基底，例如基底150可包括金屬層152、絕緣層154以及導電墊156，其中金屬層152和導電墊156可分別包括例如鋁、銅、錫、鎳、金、銀、其他合適的導電材料或上述材料的組合，絕緣層154可例如包括二氧化矽(silicon dioxide)、氮化矽(silicon nitride)、氮氧化矽(silicon oxynitride)、氧化鉭(tantalum pentoxide)、氧化鋁(aluminum oxide)、環氧樹脂(epoxy)或其他適合的絕緣材料，但本發明不以上述材料為限。金屬層152與絕緣層154可形成一線路重分佈層(redistribution layer,RDL)，以使線路重佈，但不以此為限。在其他實施例中，基底150可為包含矽、陶瓷、塑膠等材料的基板、可撓性基板、導電基板、導線架、銅箔基板或其他合適的基板，但不限於此。此外，基底150的底部還可包括複數個導電端子158，其電連接於金屬層152，導電端子158可例如為焊球(solder ball)或凸塊(bump)等，可包括銅、錫、鎳、金、鉛或其他適合的導電材料，但不限於此。在本實施例中，封裝單元100U可例如透過覆晶技術(flip chip)設置於基底150上，使控制元件120與晶片140分別電連接於基底150。舉例而言，可在控制元件120的底部形成焊球 122並覆晶於基底150上，以將焊球122電連接於基底150的導電墊156，並且將晶片140透過打線接合(wire bonding)製程電連接於基底150，例如以導線160將晶片140電連接於基底150，但不以此為限。
在一些實施例中，如第4圖所示，將該等封裝單元100U的其中一個設置在基底150上的步驟還包括透過晶片黏結膜層180將晶片140黏接至基底150上，也就是說，是透過晶片黏結膜層180將晶片140黏接至基底150上，以實現將封裝單元100U設置在基底150上。詳細而言，可先將晶片黏結膜層180分別對應設置在各突出部148的表面148S，再將封裝單元100U黏接至基底150上，使得晶片黏結膜層180設置在晶片140的各突出部148與基底150之間，但不以此為限。其中，在將封裝單元100U設置在基底150上之後，晶片140的外側與基底150之間具有一間距D。詳細而言，晶片140的各突出部148的表面148S與基底150之間可具有間距D，其中間距D為20微米至120微米，但不以此為限。並且，晶片黏結膜層180的厚度T係與各突出部148的表面148S與基底150之間的間距D相等(即厚度T=間距D)。此外，間距D及/或厚度T不宜過大或過小，若間距D及/或厚度T過大，會造成結構整體厚度增加，且晶片140與基底150相距太遠會使得結構較為不穩定；而若間距D及/或厚度T過小，會導致晶片140與基底150與之間的黏接不穩固，使得結構較為不穩定。因此，晶片黏結膜層180的厚度T的範圍較佳地為20微米至120微米，藉此可使封裝單元100U設置於基底150上的結構較為穩定。
然後，如第5圖所示，在凹槽142中填入底部填充材料170，以避免結構內部殘留氣體，進而提升結構的機械強度與可靠度，其中底部填充材料170可包括例如環氧樹脂或其他合適的材料，但不以此為限。由於在將封裝單元100U設置在基底150上之後，控制元件120與基底150之間尚存在空隙，且控制元件120 與凹槽142的側壁142S之間亦存在間隙G(如第4圖所示)，因此可將底部填充膠170形成在間隙G以及控制元件120與基底150之間，以避免結構內部殘留氣體。在本實施例中，黏接層130的材料不同於底部填充材料170，因此在黏接層130與底部填充材料170之間會形成一交界面BS(如第5圖所示)，但不以此為限。在一些實施例中，底部填充材料170可包括散熱材料，透過使控制元件120與凹槽142的側壁142S存在間隙G，且再將有助於散熱的底部填充材料170填入間隙G，可提升元件的散熱效果，但不以此為限。此外，底部填充材料170還可具有低熱膨脹係數(coefficient of thermal expansion,CTE)，以降低結構中翹曲的產生，但不限於此。
換言之，透過如前所述的製造方法以製造封裝結構，本發明一實施例的封裝結構100可包括基底150、晶片140、控制元件120以及底部填充材料170。晶片140設置於基底150上，其中晶片140包括凹槽142，且凹槽142具有底面142B以及側壁142S。控制元件120設置於基底150與晶片140之間且設置在凹槽142的底面142B，其中控制元件120與凹槽142的側壁142S之間存在一間隙G。底部填充材料170設置在凹槽142中。其中，晶片140與控制元件120分別電連接基底150。在一些實施例中，晶片140還包括本體部146以及二個突出部148，二個突出部148分別由本體部146的兩側延伸而出，以定義出凹槽142。在一些實施例中，在各突出部148與基底150之間還分別設有晶片黏結膜層180，用以將晶片140黏接至基底150上。在一些實施例中，各突出部148的表面148S與基底150之間具有一間距D，且間距D為20微米至120微米。在一些實施例中，封裝結構100還包括黏接層130，設置於控制元件120與晶片140之間，以將控制元件120貼附於凹槽142的底面142B。在一些實施例中，底部填充材料170設置在間隙G以及控制元件120與基底150之間。
透過前述實施例中封裝結構100及其製造方法的元件設置與結構設計，可增加封裝結構100的穩定性，且不需再另外設置支撐結構或支撐材料，因此可減少製程站點次數，以達到簡化製造流程、提升生產效率以及降低製造成本的功效。並且，由於製程站點次數減少且製造流程簡化，可進一步減少製程問題產生。
第6圖為本發明變化實施例的封裝單元100U’的剖面示意圖。如第6圖所示，於封裝單元100U’中透過晶片黏結膜層130b將控制元件120貼附於凹槽142的底面142B，亦即以晶片黏結膜層130b取代前述的熱固型高分子膠130a。詳細而言，在切割如第1A圖的晶圓110之前，在將控制元件120貼附於溝槽112的底面112B的步驟中，可先將晶片黏結膜層130b的一側貼附在控制元件120上，而後再將晶片黏結膜層130b的另一側貼附至晶圓110，以透過晶片黏結膜層130b將控制元件120貼附於溝槽112的底面112B，但不以此為限。
第7圖為本發明另一實施例的封裝結構的剖視示意圖。如第1A圖、第1B圖、第2圖至第5圖以及第7圖所示，在一些實施例中，在凹槽142中填入底部填充材料170之後，可再進行一封膠製程(molding)，在基底150上形成一封膠材料190，以覆蓋晶片140與基底150，藉此可形成本發明另一實施例的封裝結構100’。也就是說，相較於前述實施例的封裝結構100，本實施例的封裝結構100’還包括封膠材料190，設置在基底150上且覆蓋晶片140與基底150。其中，封膠材料190可例如為環氧成型模料(epoxy molding compound,EMC)，或者封膠材料190可例如包括環氧樹脂、陶瓷粉、炭黑、其他合適的材料或上述材料的組合，但不限於此。透過形成封膠材料190以覆蓋晶片140與基底150，可避免元件受外 在物質汙染而影響功能。
第8圖為本發明另一實施例的封裝結構的製造方法的製程示意圖。如第8圖所示，並配合第1A圖、第1B圖以及第2圖至第4圖，在本實施例中，在透過晶片黏結膜層180將晶片140黏接至基底150上，以使封裝單元100U設置在基底150上之後，進行一封膠(molding)製程，在基底150上形成一封膠材料190a，以覆蓋晶片140與基底150，且此封膠材料190a可經由凹槽142填入間隙G以及控制元件120與基底150之間的空隙，藉此可形成本發明另一實施例的封裝結構100”。其中封膠材料190a可例如包括環氧樹脂、陶瓷粉、炭黑、其他合適的材料或上述材料的組合，且封膠材料190a中填充顆粒的大小平均為0.6微米，以使封膠材料190a在封膠製程時得以通過凹槽142填入間隙G以及控制元件120與基底150之間的空隙，但不以此為限。在變化實施例中，第8圖中的封裝單元100U也可以更換為第6圖所示的封裝單元100U’。
綜上所述，本發明的封裝結構及其製造方法透過將控制元件設置在晶片的凹槽以及將晶片連同控制元件設置在基底上，可增加封裝結構的穩定性，並達到簡化製造流程、提升生產效率以及降低製造成本的功效，且可進一步減少製程問題產生。並且，透過先將控制元件設置在晶片的凹槽中，再將晶片與控制元件作為一體的封裝單元設置在基底上，可保護控制元件，以避免其在設置至基底時因外力而造成損壞。此外，透過使控制元件與晶片之間存在間隙，並填入底部填充材料，可提升元件散熱效果，且在凹槽中填入底部填充材料，可避免結構內部殘留氣體，進而提升結構的機械強度與可靠度。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等 變化與修飾，皆應屬本發明之涵蓋範圍。
100:封裝結構
120:控制元件
122:焊球
130:黏接層
140:晶片
146:本體部
148:突出部
150:基底
152:金屬層
154:絕緣層
156:導電墊
158:導電端子
160:導線
170:底部填充材料
180:晶片黏結膜層
BS:交界面

Claims (10)

  1. 一種封裝結構，包括：一基底；一晶片，設置於該基底上，其中該晶片包括一凹槽、一本體部以及二個突出部，且該凹槽具有一底面以及一側壁，該二個突出部分別由該本體部的兩側延伸而出，以定義出該凹槽，其中各該突出部的一表面與該基底之間具有一間距，且該間距為20微米至120微米；一控制元件，設置於該基底與該晶片之間且設置在該凹槽的該底面，其中該控制元件與該凹槽的該側壁之間存在一間隙；以及一底部填充材料，設置在該凹槽中；其中該晶片與該控制元件分別電連接該基底。
  2. 如請求項1所述的封裝結構，其中在各該突出部與該基底之間還分別設有一晶片黏結膜層，用以將該晶片黏接至該基底上。
  3. 如請求項1所述的封裝結構，還包括一黏接層，設置於該控制元件與該晶片之間，以將該控制元件貼附於該凹槽的該底面。
  4. 如請求項1所述的封裝結構，其中該底部填充材料設置在該間隙以及該控制元件與該基底之間。
  5. 如請求項1所述的封裝結構，還包括一封膠材料，設置在該基底上且覆蓋該晶片與該基底。
  6. 一種封裝結構的製造方法，包括：在一晶圓形成複數個溝槽；將複數個控制元件貼附於各該溝槽的一底面，其中各該控制元件與對應的各該溝槽的一側壁之間存在一間隙；對該晶圓進行一切割製程以形成複數個封裝單元，其中各該封裝單元包括一晶片以及一個該控制元件，其中該晶片包括一凹槽，且該凹槽為該等溝槽的其中一個的一部分；將該等封裝單元的其中一個設置在一基底上，其中該封裝單元的該控制元件位於該基底與該封裝單元的該晶片之間；以及在該凹槽中填入一底部填充材料，其中將該等封裝單元的其中一個設置在該基底上的步驟包括透過一晶片黏結膜層將該晶片黏接至該基底上，且該晶片黏結膜層的厚度範圍為20微米至120微米。
  7. 如請求項6所述的封裝結構的製造方法，其中係透過一黏接層將各該控制元件貼附於各該溝槽的該底面，且該黏接層的材料不同於該底部填充材料。
  8. 如請求項7所述的封裝結構的製造方法，其中該黏接層為一熱固型高分子膠或一晶片黏結膜層。
  9. 如請求項6所述的封裝結構的製造方法，其中在該凹槽中填入該底部填充材料的步驟包括將該底部填充膠形成在該間隙以及該控制元件與該基底之間。
  10. 如請求項6所述的封裝結構的製造方法，還包括在該基底上形成一封膠材料，以覆蓋該晶片與該基底。
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US11804416B2 (en) * 2020-09-08 2023-10-31 UTAC Headquarters Pte. Ltd. Semiconductor device and method of forming protective layer around cavity of semiconductor die
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