TW201603235A - 具有加強框的積體電路組件及製造方法 - Google Patents

具有加強框的積體電路組件及製造方法 Download PDF

Info

Publication number
TW201603235A
TW201603235A TW104117091A TW104117091A TW201603235A TW 201603235 A TW201603235 A TW 201603235A TW 104117091 A TW104117091 A TW 104117091A TW 104117091 A TW104117091 A TW 104117091A TW 201603235 A TW201603235 A TW 201603235A
Authority
TW
Taiwan
Prior art keywords
substrate
module
attached
reinforcing frame
reinforcing
Prior art date
Application number
TW104117091A
Other languages
English (en)
Other versions
TWI588966B (zh
Inventor
雷傑許 卡克爾
蘿拉 威爾斯 莫卡利米
阿爾卡爾古德Ｒ 斯塔拉姆
查爾斯Ｇ 渥奇克
Original Assignee
英凡薩斯公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 英凡薩斯公司 filed Critical 英凡薩斯公司
Publication of TW201603235A publication Critical patent/TW201603235A/zh
Application granted granted Critical
Publication of TWI588966B publication Critical patent/TWI588966B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/782—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
    • H01L21/784—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92225—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06596—Structural arrangements for testing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H01L2924/16153—Cap enclosing a plurality of side-by-side cavities [e.g. E-shaped cap]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H01L2924/1617—Cavity coating
    • H01L2924/16171—Material
    • H01L2924/16176—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
    • H01L2924/1632—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
    • H01L2924/164—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/166—Material
    • H01L2924/167—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/166—Material
    • H01L2924/16786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/16788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/166—Material
    • H01L2924/1679—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Mounting Of Printed Circuit Boards And The Like (AREA)

Abstract

本案為一種組件，係藉由一或更多個加強框(410)來加強，其具有含有積體電路並且附接至佈線基板(120)的模組(110、1310)。模組位於加強框中的開孔(例如，空腔及/或通孔414)中，並提供其他的功能。

Description

具有加強框的積體電路組件及製造方法 【相關申請案之交互參照】
本申請案為美國專利申請案序號第14/214,365號的部分連續案，其由Shen等人申請於2014年3月14日，標題為「INTEGRATED CIRCUITS PROTECTED BY SUBSTRATES WITH CAVITIES,AND METHODS OF MANUFACTURE(由具有空腔的基板保護之積體電路與製造方法)」，在此以引用之方式將其併入，其主張2014年3月12日申請之美國先行申請案序號第61/952,066號的優先權，標題為「INTEGRATED CIRCUITS PROTECTED BY SUBSTRATES WITH CAVITIES,AND METHODS OF MANUFACTURE(由具有空腔的基板保護之積體電路與製造方法)」，在此以引用之方式將其併入。本申請案也主張前述先行申請案序號第61/952,066號的優先權。
本案係關於積體電路，且更具體地，係關於具有包含半導體積體電路的晶粒之組件。
在積體電路的製造中，一或更多個電路製造在半導體晶圓中，且然後在所謂的「單分」或「切割」的處理中分離成「晶粒」(也稱為「晶片」)。晶粒(例如第1圖的110所示)附接至佈線基板(WS,wiring substrate，例如印刷佈線板)120，其具有導線130來連接晶粒至彼此且至系統的其他元件。更具體地，晶粒具有連接至晶粒的電路(未圖示)之接觸墊110C，且這些接觸墊附接至WS 120的接觸墊120C。墊120C藉由導線130而互連。藉由可包含焊料、導電環氧樹脂、或其他種類的連接140，來執行墊110C至墊120C的附接。
封裝劑150(例如，具有二氧化矽或其他粒子的環氧樹脂)保護晶粒110與連接140免於濕氣與其他污染物、紫外線、α粒子、以及其他可能的有害元素。封裝劑也強化了晶粒至WS的附接，來抵抗力學應力，且封裝劑協助將熱傳導遠離晶粒(至選擇性的散熱器160，或直接至周圍(例如，空氣))。然而，封裝劑會造成翹曲，如果封裝劑的熱膨脹係數(CTE)不匹配晶粒或WS的CTE。
佈線基板可為中介層，亦即，中間基板，用於調節晶粒製造技術與印刷佈線基板(PWS,printed wiring substrates)之間的失配。更具體地，晶粒的接觸墊110C可放置得遠遠較靠近彼此(以較小的間距)，相較於PWS墊120C來說。因此(第2圖)，中間基板120.1可使用在晶粒120與PWS(以120.2顯示)之間。中介層120.1包含基板120.1S(例如，半導體或其他材料)、基板120.1S的頂部上的再分佈層(RDL,redistribution layer)210.T、以及基板120.1S的底部上的另一再分佈層210.B。每一RDL 210.T、210.B包含互連線216，互連線216藉由RDL的介電質220而絕緣於彼此與基板120.1S。線216連接至中介層的頂部上的接觸墊120.1C.T以及底部上的接觸墊120.1C.B。RDL 210.T的線216藉由導電(例如，金屬化的)通孔224而連接至RDL 210.B的線216。墊120.1C.T藉由連接140.1而附接至晶粒的墊110C，如同第1圖中。墊120.1C.B利用連接140.2而附接至PWS 120.2的墊120.2C。墊120.1C.B比墊120.1C.T有較大的間距，以調節PWS接點120.2C的間距。
中介層基板120.1S應盡可能地薄，以縮短晶粒110與PWS120.2之間的信號路徑，且因此使系統更快且耗電更少。此外，如果中介層為薄的，可促進金屬化的通孔224的製造。然而，薄的中介層難以處理：它們為易碎的、易翹曲的、且在製造期間不吸收或散熱。因此，一般的製造處理在製造期間將中介層附接至暫時基板(「支撐晶圓」)。支撐晶圓稍後移除。附接與分離暫時的支撐晶圓為沉重的負擔，且如果可能的話應該極力避免。參見2005年10月25日頒發給Siniaguine的美國專利第6,958,285號。
所欲的是，提供晶粒免於力學應力、熱、以及有害元素的改良保護，以及用於薄的中介層的改良調適。
此章節總結了本發明的一些範例性實施。
在一些實施例中，晶粒由加強框保護，加強框為附接至佈線基板之分離的基板。晶粒位於加強框中的開孔中。每一開孔可為空腔、 通孔、或兩者(亦即，具有一或更多個通孔的空腔)。在一些空腔的實施例中，加強框類似於用於保護MEMS部件(Micro-Electro-Mechanical Structures，微機電結構)的覆蓋晶圓(cap wafer)；參見K.Zoschke等人所寫的「Hermetic Wafer Level Packaging of MEMS Components Using Through Silicon Via and Wafer to Wafer Bonding Technologies(使用矽通孔與晶圓至晶圓接合技術之MEMS部件的全封閉晶圓級封裝)」(2013年電子元件與技術會議，IEEE，1500-1507頁)；也參見2005年10月25日頒發給Siniaguine的美國專利第6,958,285號。然而，在一些實施例中，加強框改良從晶粒的散熱，並且可減少或消除對於封裝劑的需求。在一些實施例中(例如，具有通孔的那些)，加強框允許在製造期間對於製造順序與中間測試的更大彈性。加強框可或可不具有連接至晶粒或至佈線基板之其自身的電路。
在一些實施例中，一開孔包含多個晶粒。
本發明不限於上述的特徵與優點，並且包含下述的其他特徵。
110‧‧‧晶粒
110C‧‧‧接觸墊
120‧‧‧佈線基板(WS)
120.1‧‧‧中間基板(中介層)
120.1C.B‧‧‧接觸墊
120.1C.T‧‧‧接觸墊
120.1S‧‧‧基板
120.2‧‧‧PWS(印刷佈線基板)
120.2C‧‧‧墊
120C‧‧‧接觸墊
130‧‧‧導線
140、140.1、140.2‧‧‧連接
140L‧‧‧腿部
150‧‧‧封裝劑
150.2‧‧‧封裝劑
160‧‧‧散熱器
210.B‧‧‧再分佈層(RDL)
210.T‧‧‧再分佈層
216‧‧‧互連線
220‧‧‧介電質
224、224B‧‧‧通孔
224M‧‧‧金屬
310‧‧‧層
320‧‧‧光阻
324‧‧‧介電質
410‧‧‧加強框(保護基板)
410S‧‧‧基板
410L‧‧‧腿部
414‧‧‧空腔
420‧‧‧輔助層
430‧‧‧光阻
504‧‧‧組件
504S‧‧‧堆(晶粒)
525‧‧‧溫度界面材料(TIM)
610‧‧‧黏合劑
610G‧‧‧區域
810、820‧‧‧接合層
910‧‧‧接觸墊
920‧‧‧介電質
930‧‧‧介電質
1110C‧‧‧接觸墊
1210‧‧‧結構
1310、1310.1、1310.2‧‧‧模組
1410、1420、1430、1440、1450‧‧‧步驟
1610‧‧‧測試墊
1810‧‧‧突伸部
1910‧‧‧突伸部
2230‧‧‧層
2310、2320、2330、2340、2350、2360、2370、2374、2380、2384、2390‧‧‧步驟
Cd‧‧‧空腔深度
第1與2圖為習用技術所建構並且包含積體電路的組件的垂直橫剖面圖。
第3A、3B、3C、3D、3E、4A、4B、4C、5A、5B、5C、5D、5E.1圖為本案實施例的結構的垂直橫剖面圖。
第5E.2與5E.3圖為本案實施例的水平橫剖面的底視圖。
第6.1、6.2、7、8A、8B、8C、9A、9B、9C、9D、10、11、12、13A、13B圖為本案實施例的結構的垂直橫剖面圖。
第14圖為本案實施例之設計與製造方法的流程圖，用於製造組件。
第15A、15B、16、17、18、19、20.1圖為本案實施例的結構的垂直橫剖面圖。
第20.2、21圖為本案實施例的組件的頂視圖。
第22.1圖為本案實施例的組件的垂直橫剖面圖。
第22.2圖為本案實施例的組件的頂視圖。
第23圖為本案實施例之製造方法的流程圖，用於製造組件。
第24、25、26圖為本案實施例的組件的垂直橫剖面圖。
此章節中敘述的實施例不限制本發明。具體地，本發明不限於特定的材料、處理、尺寸或其他細節，除了如同由所附申請專利範圍所界定的之外。
根據本發明的一些實施例，第3A圖為中介層120.1的製造的開始階段。中介層基板120.1S最初選擇為足夠厚，以提供在製造中易於處理與充分散熱。在一些實施例中，基板120.1S為200mm或300mm直徑與650微米或更大厚度的單晶矽晶圓。這些材料與尺寸為範例性的，且不限制本發明。例如，基板120.1S可由其他半導體材料(例如砷化鎵)、或玻璃、或藍寶石、或金屬、或可能的其他材料製成。可能的材料包含NbTaN與LiTaN。基板稍後將薄化；例如，在矽的實例中，最終的厚度可為5至50 微米。另外，這些尺寸並非限制。
基板120.1S受到圖案化，以形成盲通孔224B(第3B圖)。「盲」指的是通孔不穿過基板120.1S。例如在矽基板進行。首先，選擇性的層310(第3A圖)形成在基板120.1S上，以保護基板及/或改良隨後形成的光阻320的附著。例如，層310可為熱氧化、化學氣相沉積(CVD)或濺射所形成的二氧化矽。然後，沉積並且光微影圖案化光阻320，以界定通孔。在光阻320曝露的區域中蝕刻層310與基板120.1S，以形成盲通孔。通孔深度等於或稍微大於基板120.1S的最終深度，例如針對一些矽基板的實施例為5至51微米。通孔可藉由乾式蝕刻來形成，例如乾式反應離子蝕刻(DRIE,dry reactive ion etching)。每一通孔的範例性直徑可為60微米或更小，但是其他尺寸也可能。通孔可為垂直的(如圖所示)，或者可具有傾斜的側壁。如同上述，特定的尺寸、處理與其他特徵為例示性，而非限制。例如，通孔可為雷射鑽孔的或藉由一些其他處理而製成。
通孔之後金屬化。如果基板120.1S為矽，這可如同以下進行。移除光阻320與保護層310，且介電質層324(第3C圖)形成於基板120.1S的整個頂表面上。介電質324使用作為通孔表面的襯裡。在一些實施例中，介電質324藉由矽基板的熱氧化或藉由CVD或物理氣相沉積(PVD)而形成。介電質324將基板電性絕緣於隨後形成在通孔224B中的金屬。介電質厚度取決於所欲的處理參數，且在範例性熱氧化物實施例中為1微米(熱氧化物為藉由熱氧化所形成的二氧化矽)。其他的尺寸與材料可用來替代。如果基板120.1S本身為介電質，介電質324可省略。
然後，金屬224M(第3D圖)形成於通孔224B中、介電質 324之上。在所示的實施例中，金屬224M填滿通孔，但是在其他實施例中，金屬為通孔表面上的襯裡。在範例性實施例中，金屬224M為電鍍銅。例如，阻障層(金屬或介電質，未單獨繪出)先形成於介電質324上，以協助銅附著並且防止銅擴散至介電質324或基板120.1S中。合適的阻障層可包含一層鈦-鎢(參見Kosenko等人於2012年9月13日公開之美國早期公開專利第2012/0228778號，在此以引用之方式將其併入)，及/或含有鎳的層(Uzoh等人於2013年1月17日公開之US 2013/0014978，在此以引用之方式將其併入)。然後，種子層(例如銅)藉由物理氣相沉積(例如，PVD，可能為濺射)形成於阻障層上。然後，電鍍銅於種子層上，以填充通孔224B且覆蓋整個基板120.1S。然後，藉由化學機械研磨(CMP)，從通孔之間的區域移除銅。選擇性地，CMP也可從這些區域移除阻障層(如果存在的話)，並且可停止於介電質324上。因此，銅與阻障層僅保留在通孔224B中與之上。
為了便於敘述，我們將稱通孔224為「金屬化的」，但是也可使用非金屬的導電材料(例如，摻雜的多晶矽)。
如果層224M並未填充通孔，但是僅作為通孔表面上的襯裡，一些其他材料(未圖示)可形成在層224M上作為填料，以填充通孔且提供平坦的頂表面給晶圓。這種填料材料可為聚酰亞胺，例如藉由旋塗法來沉積。
選擇性地，RDL 210.T(第3E圖)形成在基板120.1S的頂部上，以提供接觸墊120.1C.T在特定的位置。RDL 210.T可藉由例如相關於第1與2圖之上述先前技術的技術來形成。如果接觸墊120.1C.T由金屬224M的 頂部區域提供，則省略RDL 210.T。在此種實例中，如果基板120.1S並非介電質，則介電質層可形成在基板上並且受到光微影圖案化來曝露接觸墊120.1C.T。
中介層120.1可包含在基板120.1S與再分佈層210.T中的電晶體、電阻器、電容器與其他裝置(未圖示)。可在通孔224與RDL 210.T的製造之前、期間及/或之後，使用上述的處理步驟及/或額外的處理步驟來形成這些裝置。此種製造技術為熟知的。參見例如前述的美國專利第6,958,285號以及早期公開的專利公開案2012/0228778，兩者在此以引用之方式將其併入。
可能使用相關於第1與2圖之上述先前技術的方法或其他方法(例如，擴散接合；在此種實例中，連接140.1並非額外的元件，但是為接觸墊110C及/或120.1C.T的部分)，利用連接140.1將晶粒110附接至接觸墊120.1C.T。
選擇性地，可能藉由先前技術的技術(例如，包含模製及/或用於底部填充的毛細作用)，將封裝劑(未圖示)形成於晶粒之下(作為底部填充)及/或晶粒的周圍(以完全或部分覆蓋晶粒的側壁)以及可能在晶粒之上(以完全覆蓋晶粒的頂部與側壁表面)。封裝劑可為任何合適的材料(例如，具有二氧化矽或其他粒子的環氧樹脂)。在一些實施例中並未使用封裝劑。其他實施例使用封裝劑，但是對於封裝劑的要求是寬鬆的，因為晶粒將由額外的保護基板410(第5A圖)的形式之加強框來保護，如同下述。在一些實施例中，封裝劑僅設置於晶粒的下方(作為底部填充)，亦即，僅在晶粒與基板120.1S之間(圍繞著連接140.1)。
第4A-4C圖為保護基板410的製造。許多變化型都可能。基板410應該具有足夠的剛性，以促進組件的後續處理，如同下面解釋的。在所示的實施例中，基板410包含厚度為650微米或更大的單晶矽基板410S。其他材料(例如，玻璃、金屬、聚合物塑膠、與其他)與厚度都可能，取決於任何可能為重要的因素(包含材料與處理的可用性)。一個可能的因素為減少基板410與120.1S之間的熱膨脹係數(CTE)的不匹配：如果基板120.1S為矽，則基板410S可為矽或具有類似的CTE的另一種材料。另一個因素為減少基板410與晶粒110之間的CTE不匹配(特別是如果晶粒可實體接觸於基板410或可附接至基板410)。在一些實施例中，基板410S將不具有任何電路，但是如果想要在基板410S中或上有電路，則這會影響材料的選擇。在下述的步驟之前、及/或期間、及/或之後，可製造電路。
另一個可能的因素為高的熱傳導性，以促成基板410作用為散熱器。例如，金屬可為合適的。
開孔414(第4C圖)為形成在基板410中的空腔，以匹配晶粒110的尺寸與位置。範例性處理如下(此處理適合於矽基板410S，且可能不適合於其他材料；已知的處理可用於矽或其他材料)。首先，形成輔助層420(第4A圖)，以覆蓋基板410S，來保護隨後形成的光阻430或改良隨後形成的光阻430的附著。然後，沉積光阻430且光微影圖案化光阻430，以界定空腔414。蝕刻掉光阻開孔所曝露的輔助層420。然後(第4B圖)，在這些開孔中蝕刻基板410S，以形成具有傾斜、向上擴張的側壁之空腔414(例如，藉由濕式蝕刻)。空腔深度取決於晶粒414的厚度與連接140.1，如同下面解釋的。例如藉由各向異性乾式蝕刻，也可獲得非傾斜 (垂直)的側壁。逆行的側壁或其他側壁輪廓也可能。
然後，移除光阻430(第4C圖)。在所示的範例中，也移除輔助層420，但是在其他實施例中，層420保留在最終結構中。
如同第5A圖所示，基板410附接至中介層120.1，使得一或更多個晶粒110配接至對應的空腔414中。更具體地，保護基板410的腿部410L附接至中介層120.1的頂表面(例如，至RDL 210.T(如果RDL存在的話)；腿部410L為保護基板410圍繞空腔的那些部分)。基板至中介層的附接係為直接接合，但是其他類型的附接(例如，藉由黏合劑)也可使用，如同下面進一步敘述的。整個組件以元件符號504來標示。
在第5A圖中，晶粒的頂表面實體接觸於空腔414的頂表面。在一些實施例中，每一晶粒的頂表面接合至空腔的頂表面(直接或以某種其他方式，例如，藉由黏合劑)。此接合增加了兩個基板之間的接合強度，並且改良了從晶粒至保護基板的熱路徑的熱傳導性。在其他實施例中，晶粒並未接合至基板410，並且可間隔於基板410。空氣或熱界面材料(TIM，thermal interface material，可能為凝膠狀)可至少部分填充晶粒與空腔的頂表面之間的空間；例如，TIM可實體接觸於晶粒與空腔頂表面，以改良對於離開晶粒的熱傳導。
在其他實施例中，晶粒並未接合至空腔的頂表面，且因此晶粒的頂表面在熱運動中可沿著空腔的頂表面橫向滑動。這可降低熱應力，例如，如果晶粒與中介層的CTE匹配較優於中介層與保護基板410之間的匹配。
如同上述，在一些實施例中，晶粒係底部填充及/或由合適 的保護材料(在第5A圖中未圖示)(例如，與第1圖相同的材料)從上方封裝。在從上方封裝的實例中，已固化的封裝劑可為實體接觸於空腔414的頂表面之固體材料(可能為熱固的)。封裝劑可或可不接合至空腔表面，如同上述，其中益處類似於針對無封裝劑的實施例所上述的那些。
為了確保晶粒(或封裝劑)與空腔之間的實體接觸，晶粒(或封裝劑)的頂表面應該具有一致的高度。為了改良高度一致性，在基板410接合至中介層120.1之前，可研磨晶粒(或封裝劑)。合適的研磨處理包含精研、研磨與化學機械研磨(CMP)。另外，在將晶粒插入空腔之前，空腔表面及/或晶粒可設有合適的溫度界面材料(TIM，在此未圖示，但是示於下面討論的第5E.2與5E.3圖中的525)，以改良晶粒與基板410之間的熱轉移。TIM的熱傳導性通常可較高於空氣的熱傳導性。範例性的TIM為那些在預期的操作溫度範圍內(例如針對一些組件，0℃至200℃)以半固體、凝膠狀(潤滑脂狀)的狀態存在或者至少當溫度高時使晶粒冷卻得特別令人滿意的(例如針對一些組件，20℃至200℃)之材料。凝膠狀材料填充晶粒與基板410之間的自由空間，以提供遠離晶粒的導熱路徑。範例性TIM材料為可從銀北極公司((其在美國加州具有辦公室)取得的熱潤滑脂；該潤滑脂的熱傳導性為1W/mK。
在接合基板410至中介層120.1之後，從底部將中介層薄化，以曝露金屬224M(第5B圖)。薄化包含部分移除基板120.1S與介電質324(如果介電質存在的話)。薄化可藉由已知技術來執行(例如，在基板120.1S與介電質324的乾式或濕式、遮罩或未遮罩蝕刻之後，基板120.1S的機械研磨或精研；基板與介電質在一些實施例中為同時蝕刻)。在一些實 施例中，介電質324在薄化操作結束時突伸出金屬224M周圍的基板120.1S之外，且金屬224M突伸出介電質。參見例如前述的美國專利第6,958,285號。如同上述，本發明不限於特定的處理。
有利的是，中介層120.1藉由基板410來保持平坦，所以促進組件504的處理。基板410也改良機械的整合性(例如，增加剛性與重量)，以進一步促進組件的處理。另外，基板410有助於吸收且散去在此製造階段與隨後的製造階段期間以及組件504的後續操作中所產生的熱。基板120.1S的最終厚度因此可非常小，例如50微米或甚至5微米或更小。因此，盲通孔224B(第3B圖)可為淺的。淺的深度可促進金屬化的通孔的製造(亦即，促進通孔的蝕刻以及後續沉積介電質與金屬進入通孔中)。淺的深度也縮短通過通孔的信號路徑。此外，如果通孔為淺的，每一通孔可較窄，同時仍然允許可靠的介電質與金屬的沉積。可因此減小通孔間距。
如果需要的話，保護基板410可從頂部薄化(這未示出於第5B圖中)。基板120.1S與410的組合厚度由所欲的特性界定，例如剛性、耐翹曲、散熱、以及組件尺寸。在一些實施例中，基板410薄化，以移除晶粒110之上的基板部分並且只留下腿部410L，因此獲得相關於第20.1圖所下述的結構類型。
隨後的處理步驟取決於特定的應用。在一些實施例中(第5C圖)，可能使用先前技術的技術(例如如同第2圖中)，將RDL 210.B形成在基板120.1S的底部上。RDL提供接觸墊120.1C.B且連接接觸墊120.1C.B至金屬224M。(如果省略RDL，則由金屬224M提供接觸墊)。如果需要的話，組件504可切割成堆504S(第5D圖)。然後，該等堆(或整個組件 504，如果省略切割的話)附接至其他結構，例如第5E.1圖中的佈線基板120.2(例如，印刷佈線基板)。在第5E.1圖的範例中，堆504S附接至PWS 120.2，且更具體地，堆的接點120.1C.B附接至PWS接點120.2C，可能係藉由如同第1或2圖中的相同技術。PWS 120.2的導線130連接接觸墊120.2C至彼此或其他元件。這些細節並非限制。
第5E.2圖為沿著第5E.1圖中的線5E.2-5E.2之水平橫剖面的可能底視圖。在第5E.2圖的範例中，晶粒由溫度界面材料(TIM)525圍繞。腿部410L形成完全圍繞每一空腔的區域，且接合至腿部的中介層區域也完全圍繞每一空腔。
第5E.3圖為相同水平橫剖面的另一可能的底視圖，也具有TIM 525。在此範例中，腿部410L僅設置在每一空腔的兩相對側上(左側與右側)，但是並未設置在空腔的上方與下方。每一空腔414為基板410S中的水平凹槽，包含多個晶粒(凹槽也可僅具有一個晶粒)。凹槽可運行通過整個基板。其他空腔形狀也可能。
如同上述，保護基板410與中介層120.1可藉由黏合劑來接合，且第6.1圖之黏合劑610為此種接合。黏合劑610設置在腿部140L或中介層120.1的對應區域或兩者上。該結構顯示於第5A圖的階段(在中介層薄化之前)。在一些實施例中，黏合劑為彈性的，具有低彈性係數(例如，具有50MPa的彈性模數的矽橡膠)，以協助吸收晶粒110及/或基板410及/或中介層120.1的熱膨脹的任何不匹配(例如，使得來自膨脹的晶粒110的壓力將不會損壞保護基板410或晶粒)。在一些實施例中，如果晶粒的CTE等於或大於保護基板410或基板410S的CTE，這是有益的。黏合劑的彈性也 吸收晶粒110的頂表面或空腔414的頂表面的高度不一致性。另外，為了吸收晶粒的膨脹，黏合劑可具有等於或大於晶粒的CTE之CTE。範例性的黏合劑為環氧樹脂型的底部填充。
在一些實施例中，黏合劑610為沖壓的膠帶。
第6.2圖為類似的實施例，其中黏合劑不存在於該結構將被切割的區域610G中。
第7圖為類似的實施例，但是黏合劑610覆蓋保護基板410S的整個底表面。黏合劑接合晶粒(或封裝劑)的頂表面至空腔的頂表面。黏合劑的CTE可等於、或大於、或小於晶粒的CTE。
第8A-8C圖為使用單獨的接合層810、820來直接接合保護基板410至中介層120.1。在一些實施例中，接合層為二氧化矽，但是也可使用其他材料(例如，用於共熔接合的金屬)。參見第8A圖，晶粒附接至中介層120.1(如同第3E圖中)；晶粒之後選擇性地底部填充及/或從上方封裝(在第8A圖中，封裝劑150封裝且底部填充晶粒)。藉由任何合適的技術(例如，濺射)，形成接合層810(例如，二氧化矽或金屬)來覆蓋中介層與晶粒(以及封裝劑，如果存在的話)。
參見第8B圖，保護基板410設有空腔，如同第4C圖中。然後，藉由任何合適的技術(例如，濺射，或熱氧化(如果基板410S為矽))，形成接合層820(例如，二氧化矽或金屬)來覆蓋基板表面。
參見第8C圖，中介層接合至基板410，使得層810、820實體接觸於彼此。然後，加熱該結構，以將層820接合至層810，其中兩層接觸，亦即，在腿部410L處與在空腔的頂表面處。然而，在一些實施例中， 在接合之前，層820在空腔的頂表面處移除，並未接合晶粒至空腔的頂表面。
第6.1-8A圖的結構的後續處理(中介層薄化，可能的切割等)可如同上述的其他實施例。
上述處理步驟的順序並非限制；例如，通孔224可在中介層薄化之後形成。第9A-9D圖為範例性處理。中介層120.1基本上如同在第3E或6.1或6.2或8A圖中所製造，但是沒有通孔224(通孔將在稍後形成)。具體地，介電質324為中介層基板120.1S上的平坦層。然後，接觸墊910在未來通孔224的位置處形成於基板120.1S上。RDL 210.T選擇性地製造在中介層的頂部上，以連接接觸墊910至中介層的頂部上的墊120.1C.T。(替代地，墊120.1C.T可由墊910提供。)晶粒110附接至墊120.1C.T，且選擇性地底部填充與封裝。接合層810(如圖所示)選擇性地沉積，如同第8A圖中，以接合至保護基板(替代地，該接合可藉由第6.1或6.2或7圖中的黏合劑，或藉由相關於第5A圖所上述的直接接合處理)。
具有晶粒附接的中介層120.1然後接合至保護基板410(第9B圖)，如同上述的任何實施例中。然後，中介層薄化(第9C圖)。晶粒在後續步驟期間將由基板410保護。基板410可在任何所欲的階段薄化。
然後，金屬化的通孔224從中介層底部形成。範例性處理如下：
1.介電質920(例如，二氧化矽或氮化矽)沉積(例如，藉由濺射或CVD)，以覆蓋中介層基板120.1S的底表面。
2.通孔(貫通孔)從底部形成通過介電質920與基板 120.1S(藉由遮罩蝕刻或雷射鑽孔或一些其他的處理)。通孔終止於接觸墊910處。
3.介電質930(例如，二氧化矽或氮化矽)沉積(例如，藉由濺射或CVD)，以覆蓋中介層基板120.1S的底表面並且作為通孔的襯裡。介電質930從底部覆蓋接觸墊910。
4.蝕刻介電質930，以曝露接觸墊910。此可為遮罩蝕刻。替代地，可使用毯覆各向異性(垂直)蝕刻從每一接觸墊910的至少一部分之上移除介電質930，同時使介電質留在通孔側壁上。垂直蝕刻可或可不移除通孔外部的介電質930。
5.形成導電材料224M(例如，金屬)於通孔中，可能藉由上述相同的技術(例如，銅電鍍)。導電材料不存在於通孔外部(例如，它可藉由CMP研磨掉)。導電材料可填充通孔或僅作為通孔表面的襯裡。每一通孔中的導電材料實體接觸於對應的墊910。
隨後的處理步驟可如同相關於第5C-5E.3圖所上述的。具體地，底部的RDL 210.B(第5C圖)與連接140.2可如同上述地形成。如果需要，可切割該結構(第5D圖)，並且附接至另一結構(例如，第5E.1圖中的PWS 120.2)。
通孔224為選擇性的，且進一步，基板120.1可為任何佈線基板，例如第10圖的120所示。此圖式顯示在腿部410L處與空腔頂表面處使用黏合劑610來接合保護基板410至WS 120之實施例，但是可使用上述的任何其他接合方法。並未顯示底部填充或其他封裝劑，但是整個晶粒可存在有或沒有封裝劑的底部填充。
在一些實施例中，通孔224部分在中介層薄化之前形成且部分在中介層薄化之後形成。例如，在一些實施例中，中介層受到處理至第3C圖的階段(介電質324形成，可能藉由高溫處理，例如矽的熱氧化)，但是取代金屬，通孔填充有暫時填充，例如聚酰亞胺。然後，其他處理步驟則如同相關於第3E-5B圖所上述地執行，且具體地，當中介層薄化時，暫時填充係曝露於中介層底部處。移除暫時填充，且將金屬或其他導電材料224M置於通孔中，如同相關於第9D圖所上述的。這會是有利的，如果因為與後續處理步驟的不相容而需要避免金屬太早沉積至通孔中(在第3D圖的階段)，且同時，不希望將介電質324的沉積延遲至第9D圖的階段(例如如果介電質324藉由高溫處理而形成)。其他變化也可能。
相關於第5A-10圖之上述技術可用於附接任何數量的單獨的保護基板410至相同的中介層120.1或WS 120；不同的保護基板410可附接至基板120.1或120的相同側，其中不同的晶粒在相同或不同的保護基板410的不同空腔中；參見第16圖，下面更詳細地敘述。其他保護基板410可附接至基板120.1或120的相對側。一些晶粒可不具有保護基板410來保護它們。每一基板120.1S或410S可為晶圓，且兩個基板在給定的組件504中可為相同的尺寸；但是在相同組件中也可能有不同的尺寸。
晶粒也可在相同的空腔中堆疊於彼此之上(參見第11圖，顯示如同第6.1圖的相同製造階段中的結構)，其中每一堆疊僅頂部晶粒實體接觸於對應的空腔的頂表面(一堆疊可具有多個晶粒附接至下方晶粒的頂表面；多個晶粒的一或更多者可使其頂表面接觸於空腔的頂表面)。每一堆疊中的晶粒可具有它們各自的電路透過其接觸墊1110C與各自的連接 140(其可為上述的任何類型)而互連。在第11圖中，基板120.1S、410S藉由腿部410L上的黏合劑610接合在一起，如同第6.1圖中，但是也可使用上述的其他接合方法。堆疊的晶粒也可用於上述的其他變化型，例如，當保護基板直接接合至PWS時。晶粒堆疊可由任何積體電路封裝來取代。
在一些實施例中，基板410S具有電路，可能連接至晶粒及/或中介層120.1S或PWS中的電路。參見第12圖，藉由結構1210連接至基板410S的頂部晶粒；每一結構1210包含基板410S中的接觸墊、頂部晶粒110上的對應接觸墊、以及接合兩接觸墊至彼此的連接(例如，焊料或上述的任何其他類型)。在第12圖的範例中，封裝劑150底部填充且完全圍繞每一晶粒，接觸於空腔的頂表面。如同上述，封裝及/或底部填充為選擇性的。
本發明不限於上述或下述的實施例。例如，通孔224可在RDL之後形成，並且可蝕刻通過一或兩個RDL。上述或下述的不同的特徵可結合。例如，在下述的第13A與13B圖中，基板410藉由黏合劑610而接合至中介層120.1，但是可使用上述的其他接合方法。此外，在第13A與13B圖中，通孔224在中介層薄化之前形成，但是它們可在中介層薄化之後形成，如同第9C-9D圖中。顯示的細節僅用於例示的目的，且不限制本發明。
空腔414可包含晶粒、堆疊、或其他不同高度的封裝(例如，如同在第13A圖中)，且較短模組的高度可增加，以改良力學強度及/或散熱--參見第13B圖。第13A與13B圖顯示在第11圖的階段的組件(在中介層薄化之前)。每一空腔414包含兩個模組1310.1、1310.2；模組1310.1包含堆疊的兩個晶粒，且模組1310.2包含單個晶粒(一模組可為包含堆疊或 其他封裝的任何晶粒或組件)。模組1310.2的晶粒110可做得較薄(第13A圖)，但是空腔深度Cd必須容納模組1310.1，所以模組1310.2的晶粒110的厚度增加(第13B圖)，以利用高Cd值。
第14圖為處理的流程圖，其可用來決定每一晶粒在設計階段的厚度。在步驟1410，決定每一模組1310的最小厚度。(Tmin可包含互連相同模組中的不同晶粒之連接140的高度，及/或連接該模組至中介層之連接140的高度；此外，如果任何模組的頂部將連接至保護基板410(如同第12圖中)，則在一些實施例中，Tmin包含對應的連接的高度。)在第13B圖的範例中，模組1310.1的Tmin較大於模組1310.2的Tmin。
在步驟1420，決定最大的Tmin值(此值在第14圖中以M表示)。在第13B圖的範例中，M為模組1310.1的Tmin值。
在步驟1430，M值係用於決定空腔深度Cd。例如，Cd可設定為M值加上一值，該值可根據下述來決定：可用的製造容忍度(亦即，可能的製造誤差)及/或所欲的散熱性能及/或接合技術(例如，層610或810或820的厚度)，及/或其他可能的參數。
在步驟1440，針對其Tmin小於最大值(M)的每一模組，模組的厚度如同所欲地增加。在第13B圖的範例中，針對模組1310.2，Tmin值小於M，所以如果增加晶粒厚度將促進晶粒製造或改良晶粒的散熱或者如果增加晶粒厚度將存在有其他益處，則增加模組1310.2的晶粒的厚度。在步驟1450，使用步驟1410-1440中所獲得的厚度參數來製造晶粒，空腔製造成在步驟1430中所獲得的厚度，使用任何上述方法，將保護基板410與晶粒附接至中介層。
步驟1420、1430、1440在一些實施例中自動執行，例如藉由包含電腦處理器的電腦或藉由一些其他電路，電腦處理器執行儲存在電腦儲存器(例如，記憶體)中的軟體指令。
此外，如同第15A圖中所示，空腔414可具有不同的深度：空腔在較短的模組(例如1310.2)之上可較淺於在較高的模組(例如1310.1)之上。有利的，在一些實施例中，減小較短的模組與頂部空腔表面之間的熱阻。例如，在一些實施例中，模組具有不同的高度，但是每一模組的頂表面與上方的空腔表面之間的間隙為相同，及/或具有相同的熱阻。除了熱阻的考量之外，如果任何模組的頂表面連接至晶圓410(如同第12圖中)，模組的頂部晶粒的頂表面與上方的空腔表面之間的間隙係做成等於該等連接的所欲高度。
在一些實施例中，即使針對相同高度的模組，可提供具有不同深度的空腔。
另外(第15B圖)，不同的空腔可具有在相同加強框中的不同深度。可選擇不同的深度，以適應於不同的模組高度，及/或針對其他原因。例如，產生較多熱的模組可置於淺空腔中，以減少模組與加強框之間的熱阻，但是產生較少熱的另一模組可置於較深的空腔中，以增加對於模組高度變化的容忍度。
如同上述，多個保護基板410可附接至相同的中介層。一範例顯示於第16圖中：每一加強框410具有一或更多個空腔，並且覆蓋一或更多個晶粒110(在上述與下述的所有範例中，晶粒110可由相關於第13B圖所上述的任何類型的模組1310來取代)。在所有其他態樣中，第16圖的 結構可如同上述的任何實施例。具體地，晶粒可封裝及/或底部填充，並且可藉由空氣或其他氣體或TIM潤滑脂或其他材料而分隔於頂部空腔表面，或者晶粒可實體接觸於空腔頂部表面或可接觸於可接觸空腔頂部表面的固體材料(例如，TIM)。上述的其他變化型也可存在於第16圖的結構類型中(例如，加強框可藉由黏合劑(例如，610)(例如，沖壓的膠帶或其他類型)而接合至中介層，黏合劑可或可不存在於加強框之間；也可使用其他的接合技術)。
這種結構可提供多個優點。具體地，加強框410之間的中介層區域為可使用的，並且可用於測試墊1610：測試墊可連接至RDL 210.T中的其他接觸墊及/或至金屬化的通孔224M。測試墊促進在切割之前及/或之後組件的測試(切割在一些實施例中省略)。在一些實施例中，測試墊位於切割線上，亦即，測試墊在切割期間可被切割通過，且可因此被破壞或可僅分成多個測試墊，其在切割之後可用於測試每一晶粒。
另外，切割之前可能存在的熱應力較小於晶圓尺寸的(連續的)加強框。
另外，因為每一加強框410覆蓋小於所有晶粒110，當每一加強框410放置在中介層上時，每一加強框410較容易對準(因為每一加強框必須僅對準於該加強框所覆蓋的模組)。此外，中介層可具有在加強框410的位置之間的頂表面中的對準標記(未圖示)，以促進每一加強框的對準。
第17圖例示在中介層薄化以及第5D圖中的連接140.2與底部RDL 210.B形成之後，從第16圖的結構獲得的範例性晶粒。(如同上述，不 同特徵可用任何合適的方式結合，且具體地，連接140.2及/或RDL 210.B可省略。)在第17圖中，切割線置於加強框410之間，所以加強框410並未被切割。切割因此簡化。
針對對準的目的，加強框410可具有突伸部或狹縫，其匹配於中介層上的狹縫或突伸部。參見第18與19圖，其顯示在第17圖的階段的結構。在第18圖中，加強框410具有突伸部1810係匹配於中介層上的狹縫(突伸部1810可延伸至中介層基板120.1中或僅進入RDL 210.T中)。在第19圖中，加強框410具有狹縫係匹配於中介層的突伸部1910(中介層的突伸部可為中介層基板的延伸，或者可為RDL 210.T的部分)。此種對準特徵可結合(突伸部可存在於中介層與加強框410兩者上，具有匹配的狹縫在加強框410與中介層上)。此種對準特徵可上述的任何實施例中，包含具有單個加強框410的實施例(參見第5C圖)。
如同上述，開孔410可為如同上面所示的空腔，或者可為通孔，或者可為具有通孔的空腔。第20.1、20.2圖分別為通孔實施例的垂直橫剖面與頂視圖；第20.1圖的垂直橫剖面在第20.2圖中標示為「20.1」。此實施例類似於第17圖，但是開孔414為加強框410中的通孔；加強框410橫向圍繞晶粒。通孔促進加強框對準與附接至中介層(因為在加強框的放置與附接期間，晶粒區域為可見且可使用的)。此外，測試墊1610可置於通孔414內(例如，在RDL 210.T的頂部或晶粒110處)；測試墊可連接至彼此及/或晶粒與中介層中的其他電路，且可經由通孔414來使用。
類似於第16圖，在開孔414為通孔的實施例中，在附接至中介層之前，每一加強框410可提供作為單獨的結構。優點包含相關於第16 圖所上述的那些。或者，加強框410可為第5A圖的單個晶圓的部分；參見第21圖，其為具有四個孔414的晶圓尺寸的加強框410的一部分的範例性頂視圖；加強框與中介層將沿著切割線2110被切割。如同上述的其他方案，在一些實施例中省略切割。
雖然通孔型加強框410(例如第20.1、20.2圖中)並不像空腔型加強框(例如第5D圖中)那樣強固，但是通孔型加強框可具有優點。具體地，如同上述，它們允許測試墊1610的更多位置，且它們可較容易對準與接合至中介層。此外，它們可具有較小的力學應力。此外，它們可支撐直接接合至晶粒的散熱器：參見例如第22.1圖(垂直橫剖面圖)與第22.2圖(頂視圖)中的散熱器(傳熱器)160：這些圖式如同第20.1、20.2圖的相同結構與相同視圖，但是其中散熱器160係支撐於加強框410的兩相對側部上。散熱器可由加強框410的所有側部、三個側部、或以一些其他方式來支撐(注意到，通孔414可具有多於四個側部並且在頂視圖中不必是矩形，例如，通孔可為圓形或任何其他形狀)。在第22.1與22.2圖中，散熱器藉由接合層2230而接合至晶粒110。層2230可為黏合劑及/或TIM及/或金屬及/或適於接合的其他類型的層。散熱器可接合至少於所有晶粒110。如果使用直接接合，層2230可省略。此接合為選擇性的：取代地或額外地，散熱器可藉由接合層或藉由直接接合而接合至加強框410。散熱器可覆蓋在相同或多個加強框中的多個通孔或由該多個通孔支撐；此種散熱器可接合至在相同或不同通孔中的多個加強框及/或多個晶粒。
通孔方案增加了製造的彈性，因為晶粒110與加強框410可用任何順序附接至中介層120.1。範例性的製造順序例示於第23圖的流程圖 中。在此實施例中，步驟2310例示製造中介層120(亦即，120.1)、加強框或多個加強框410、與模組1310(例如，晶粒110)。中介層可或可不包含金屬化的通孔224M(通孔稍後可如同相關於第9D圖所上述地形成)。在步驟2320，加強框或多個加強框410附接至中介層。在步驟2330，晶粒110(或模組)附接至中介層，並且在所有側部上被底部填充及/或封裝(橫向地、從上方與下方)，例如如同第1圖中。(晶粒可在步驟2320之後製造，或者可在步驟2320之前製造與附接)。在步驟2340，中介層薄化。在步驟2350中，金屬化的通孔224M形成在中介層中(如同上述，在步驟2310可形成一些或全部的這些通孔，並且在步驟2340曝露於中介層背側上)。在步驟2360，測試該組件(使用測試墊1610)。在步驟2370，一或更多個散熱器160附接於孔414之上。在步驟1374，可分配封裝劑(例如，第1圖中的150)來封裝中介層之上的晶粒。封裝劑為選擇性的，且封裝可在散熱器附接之前執行或可在散熱器附接之後執行(如果散熱器未完全覆蓋孔414)。或者，一些封裝(或晶粒110的至少底部填充)可在散熱器附接之前執行(取代步驟2330的底部填充，或除了步驟2330的底部填充之外)，且額外的封裝可在散熱器附接之後執行。注意到，封裝劑的數量可基於中介層的翹曲來控制。封裝劑的類型也可基於翹曲來控制。例如，如果中介層向上彎曲(亦即，中間部分較高於邊緣)，且封裝劑引致壓縮應力，則可分配更多的封裝劑來抵消翹曲，及/或可選擇封裝劑材料，以提供更多的壓縮應力來抵消翹曲。在這些後期階段的封裝(可能包含散熱器附接之後)允許封裝劑材料與數量可基於封裝之前對組件執行的翹曲測量來選擇。
切割執行於步驟2380。如果需要的話(步驟2384)，步驟2380所獲得的每一晶粒(亦即，每一堆疊)504S附接至另一基板，例如PWS 120.2(示於第24圖中，針對第22.1圖的組件；第23圖的處理也可執行於上面討論的其他類型的組件)。然後，如同步驟2390所指示的，整個晶粒504S(包含中介層)可被封裝。例如，在第24圖中，封裝劑層150.1(底部填充)與150.2(例如，環氧樹脂)已經被分配且固化，以從下方與側部上封裝(覆蓋)晶粒504S，來保護晶粒或僅減小翹曲：封裝劑所引致的應力可抵消組件中及/或PWS中的其他翹曲應力。在一些實施例中，翹曲減小至100微米以下。在第24圖的範例中，封裝劑不會到達晶粒504S的頂部，但是僅從下方與側部上覆蓋晶粒，部分分道至散熱器160。封裝劑150.2也填充包含晶粒110的空腔。封裝劑150.2的部分可已經形成於上述的步驟2330及/或2374時。在其他實施例中，封裝劑可升高至高於或低於第24圖所示的位準之任何位準；例如，封裝劑可在側部與頂部上完全覆蓋散熱器，如同例如第25-26圖所示。
許多變化都可能。第25圖例示如同第24圖的相同組件，但是晶粒504S為如同第20.1圖中(無散熱器160)。另外，在此範例中，封裝劑層150.2完全覆蓋晶粒504S，但是封裝劑可形成至較低的位準(例如，如同第24圖中)，如果適於補償翹曲或用於任何其他的目的。封裝劑可如同第24圖所上述地形成。
第26圖為相同組件，但是晶粒504S為如同第17圖中。同樣地，封裝劑層150.2完全覆蓋晶粒504S，但是封裝劑可形成至較低的位準。可使用其他類型的晶粒504S。
一些實施例的一些態樣藉由以下的條款來敘述：
條款1敘述一種製品，包含：一第一基板(例如，中介層120或120.1，或中介層基板120.1S)，其包含一或更多個第一接觸墊(例如，頂部接觸墊120.1C.T)；複數個模組(例如，晶粒110或其他組件/封裝，例如，模組1310)，其附接至該第一基板，至少一模組包含一半導體積體電路，該模組包含一或更多個接觸墊，每一接觸墊係附接至一個別的第一接觸墊(注意到，也可有虛擬模組，例如，虛擬晶粒，如果組件最初設計成容納針對特定實施例所需的更多的模組)；一加強框(例如，410或410S)，其包含一或更多個空腔，該加強框係附接至該第一基板，其中每一模組的至少部分係位於該加強框中的一對應空腔中(參見例如第13A圖)，其中至少兩模組具有不同的高度並且係至少部分位於該加強框中的該相同空腔中。
注意到，用語「空腔」在本文使用時涵蓋具有通孔的空腔。然而，用語「空腔」在本文使用時具有深度，其為限制可放置在空腔中的模組的高度之參數。因此，如果開孔414具有垂直的壁部且無「頂部」(例如如同第20.1圖中)，則開孔並非空腔，因為開孔不限制可放置在開孔中的任何模組的高度。
條款2敘述一種製品，包含：一第一基板(例如，中介層120或120.1，或中介層基板120.1S)，其包含一或更多個第一接觸墊；複數個模組，其附接至該第一基板，每一模組包含一半導 體積體電路，每一模組包含一或更多個接觸墊，每一接觸墊係附接至一個別的第一接觸墊；一加強框，其包含一或更多個空腔，該加強框附接至該第一基板，其中每一模組的至少部分係位於該加強框中的一對應空腔中(注意到，多個模組可位於相同的空腔中)；其中，複數個模組包含一第一模組與一第二模組，其至少部分位於相同的空腔中，該空腔在第一模組之上比在第二模組之上更深(例如如同第15A圖中)。
條款3敘述一種製品，包含：一第一基板，其包含一或更多個第一接觸墊；複數個模組，其附接至該第一基板，每一模組包含一半導體積體電路，每一模組包含一或更多個接觸墊，每一接觸墊係附接至一個別的第一接觸墊；一加強框，其包含複數個空腔，該加強框附接至該第一基板，其中每一模組的至少部分係位於該加強框中的一對應空腔中；其中，複數個模組包含一第一模組與一第二模組，第二模組高於第一模組，且對應於第二模組的空腔係較深於對應於第一模組的空腔(例如如同第15B圖中)。
條款4敘述一種方法(例如，如同第14圖中)，用於設計一製品，該製品包含附接至一第一基板且由一加強框覆蓋的複數個模組，該加強框包含一第一空腔，該第一空腔覆蓋複數個模組，每一模組包含一半導體積體電路(例如如同第13B圖中)，該方法包含： (a)決定每一模組的一最小厚度Tmin；(b)決定該等模組的該等最小厚度的一最大值M；(c)藉由使用該最大值M的一程序，決定該第一空腔的一深度；(d)如果任何模組的最小厚度Tmin小於M，則針對最小厚度Tmin小於M的至少一模組決定是否該模組的厚度將增加，且如果該模組的厚度將增加，則增加該模組的厚度。
條款5敘述條款4的該方法另包含：基於該等模組的厚度來製造該等模組。
條款6敘述條款4或5的該方法，其中至少一模組的厚度在操作(d)中增加，且增加該模組的厚度包含：增加該模組中的至少一半導體積體電路的一厚度。
條款7敘述一種製品，包含：一第一基板，其包含一第一側與在該第一側處的一或更多個第一接觸墊；一或更多個模組，其附接至該第一基板，每一模組包含一半導體積體電路，每一模組包含一或更多個接觸墊，每一接觸墊係附接至一個別的第一接觸墊；及複數個加強框，其附接至該第一基板(例如如同第16圖中)，每一加強框包含一或更多個開孔，每一模組的至少部分係位於一對應加強框中的一對應開孔中。
在一些實施例中，至少一開孔為圓柱形通孔。「圓柱形」不 限於「圓形」；例如，在第22.2圖中，在頂視圖中通孔414可為矩形、或橢圓形、或任何其他形狀。另外，「圓柱形」不限於「直的圓柱」；換句話說，通孔414的壁部不必是垂直的，但是相對於加強框410或中介層120.1可有一些其他的(非90°)角度。
條款8敘述條款7的該製品，其中該等加強框彼此間隔。
條款9敘述條款7或8的該製品，其中該第一基板包含一或更多個測試墊(例如，1610)，用於測試位於該等加強框之外的該製品。
條款10敘述條款9的該製品，其中至少一測試墊位於至少兩加強框之間。
條款11敘述一種方法，用於製造一製品，該方法包含：獲得一第一基板，其包含一第一側與在該第一側處的一或更多個第一接觸墊；獲得一或更多個模組，其附接至該第一基板，每一模組包含一半導體積體電路，每一模組包含一或更多個接觸墊，每一接觸墊係附接至一個別的第一接觸墊；及附接複數個加強框至該第一基板，每一加強框包含一或更多個開孔，每一模組的至少部分係位於一對應加強框中的一對應開孔中。參見例如第16圖。
條款12敘述條款11的該方法，其中該等加強框係彼此間隔。
條款13敘述條款11或12的該方法，另包含：切割在至少兩加強框之間的該第一基板，以形成複數個晶粒，每一加強框係在該等晶粒 的一者中。第17圖為實施例中的一種晶粒。
條款14敘述條款11、12或13的該方法，其中該第一基板包含一或更多個測試墊，用於測試位於該等加強框之外的該製品。
條款15敘述條款14的該方法，其中至少一測試墊位於至少兩加強框之間。
條款16敘述一種製品，包含：一第一基板，其包含一第一側與在該第一側處的一或更多個第一接觸墊；一或更多個模組，其附接至該第一基板，每一模組包含一半導體積體電路，每一模組包含一或更多個接觸墊，每一接觸墊係附接至一個別的第一接觸墊；及一或更多個加強框，其附接至該第一基板，每一加強框包含一或更多個開孔，每一模組的至少部分係位於一對應加強框中的一對應開孔中；其中，該第一基板包含橫向圍繞該一或更多個加強框的一部分。例如，在第17圖中，中介層包含橫向圍繞該加強框410的一部分(包含測試墊1610)。
條款17敘述條款16的該製品，其中橫向圍繞該一或更多個加強框的該部分包含用於測試該製品的一或更多個測試墊。
條款18敘述條款17的該製品，其中至少一測試墊電連接至該至少一模組(例如，藉由第17圖中的RDL 210.T中的互連線)。
條款19敘述一種製品，包含： 一第一基板，其包含一第一側與在該第一側處的一或更多個第一接觸墊；一或更多個模組，其附接至該第一基板，每一模組包含一半導體積體電路，每一模組包含一或更多個接觸墊，每一接觸墊係附接至一個別的第一接觸墊；及一或更多個加強框，其附接至該第一基板，每一加強框包含一或更多個開孔，每一模組的至少部分係位於一對應加強框中的一對應開孔中；其中在至少一加強框中，至少一開孔包含一通孔。參見例如第20.1圖。注意到，通孔的側壁不需要為垂直的，且該開孔可為具有通孔(可能為多個通孔)的空腔。
條款20敘述條款19的該製品，其中該製品包含一或更多個測試墊，用於測試該製品，該製品可通過該通孔來使用並且由該至少一加強框橫向圍繞。參見例如第20.1圖中的測試墊1610。
條款21敘述條款20的該製品，其中至少一測試墊為該第一基板的部分。(例如，作為測試墊1610，其為第20.1圖中的RDL 210.T的部分)。
條款22敘述條款20或21的該製品，其中至少一測試墊為至少部分位於該至少一開孔中之一模組的部分(例如，第20.1圖中的晶粒110的頂部上的測試墊)。
條款23敘述一種方法，用於製造一製品(例如如同第23圖中)，該方法包含： 獲得一第一基板，其包含一第一側與在該第一側處的一或更多個第一接觸墊；獲得一或更多個模組，其附接至該第一基板，每一模組包含一半導體積體電路，每一模組包含一或更多個接觸墊，每一接觸墊係附接至一個別的第一接觸墊；及附接一或更多個加強框至該第一基板，每一加強框包含一或更多個開孔，每一模組的至少部分係位於一對應加強框中的一對應開孔中；其中在至少一加強框中，至少一開孔包含一通孔。
條款24敘述條款23的該方法，其中在該至少一模組的至少部分係部分位於該通孔中之前，該至少一加強框係附接至該第一基板。
條款25敘述條款19的該製品，另包含一或更多個散熱器(例如，160)，每一散熱器位於一或更多個加強框中的一或更多個通孔之上，其中位於至少一加強框中的至少一通孔之上的至少一散熱器係附接至該加強框及/或至少部分位於該通孔中的至少一模組，每一散熱器具有高於每一加強框的一熱傳導性。
條款26敘述條款25的該製品，其中位於至少一加強框中的至少一通孔之上的至少一散熱器係附接至該加強框。
條款27敘述條款25的該製品，位於至少一通孔之上的至少一散熱器係附接至至少部分位於該通孔中的至少一模組。
條款28敘述條款19的該製品，其中該第一基板包含一第一對準特徵，且至少一加強框包含一第二對準特徵，且該第一與第二對準特 徵之一者為一凹槽，該第一與第二對準特徵之另一者為一突伸部，該突伸部不具有電性功能並且至少部分位於該凹槽中。
本發明並不限於上述範例。其他實施例與變化例都在本發明的範圍內，如同由所附申請專利範圍所界定的。
110‧‧‧晶粒
110C‧‧‧接觸墊
120.1‧‧‧中介層
140‧‧‧連接
210.T‧‧‧再分佈層
224‧‧‧通孔
324‧‧‧介電質
410‧‧‧加強框(保護基板)
410L‧‧‧腿部
410S‧‧‧基板
610‧‧‧黏合劑
1110C‧‧‧接觸墊
1310.1‧‧‧模組
1310.2‧‧‧模組

Claims (19)

  1. 一種組件，包含：一第一基板，其包含一或更多個第一接觸墊；複數個模組，其附接至該第一基板，至少一模組包含一半導體積體電路，該模組包含一或更多個接觸墊，每一接觸墊係附接至一個別的第一接觸墊；一加強框，其包含一或更多個空腔，該加強框係附接至該第一基板，其中每一模組的至少部分係位於該加強框中的一對應空腔中，其中至少兩模組的高度不同，並且係至少部分位於該加強框中的該相同空腔中。
  2. 一種組件，包含：一第一基板，其包含一第一側與在該第一側處的一或更多個第一接觸墊；一或更多個模組，其附接至該第一基板，每一模組包含一半導體積體電路，每一模組包含一或更多個接觸墊，每一接觸墊係附接至一個別的第一接觸墊；及複數個加強框，其附接至該第一基板，每一加強框包含一或更多個開孔，每一模組的至少部分係位於一對應加強框中的一對應開孔中。
  3. 如申請專利範圍第2項之組件，其中至少一開孔為一圓柱形通孔。
  4. 如申請專利範圍第2項之組件，其中該等加強框係彼此間隔。
  5. 如申請專利範圍第2項之組件，其中該第一基板包含一或更多個測試墊，用於測試位於該等加強框之外的該組件。
  6. 如申請專利範圍第5項之組件，其中至少一測試墊位於至少兩加強框之間。
  7. 一種方法，用於製造一組件，該方法包含：獲得一第一基板，其包含一第一側，而該第一側具有一或更多個第一接觸墊；獲得一或更多個模組，其附接至該第一基板，每一模組包含一半導體積體電路，每一模組包含一或更多個接觸墊，每一接觸墊係附接至一個別的第一接觸墊；及附接複數個加強框至該第一基板，每一加強框包含一或更多個開孔，每一模組的至少部分係位於一對應加強框中的一對應開孔中。
  8. 如申請專利範圍第7項之方法，其中該等加強框係彼此間隔。
  9. 如申請專利範圍第7項之方法，另包含切割在至少兩加強框之間的該第一基板，以形成複數個晶粒，每一加強框係在該等晶粒的一者中。
  10. 如申請專利範圍第7項之方法，其中該第一基板包含一或更多個測試墊， 用於測試位於該等加強框之外的該組件。
  11. 如申請專利範圍第10項之方法，其中至少一測試墊位於至少兩加強框之間。
  12. 一種組件，包含：一第一基板，其包含一第一側，而該第一側具有一或更多個第一接觸墊；一或更多個模組，其附接至該第一基板，每一模組包含一半導體積體電路，每一模組包含一或更多個接觸墊，每一接觸墊係附接至一個別的第一接觸墊；及一或更多個加強框，其附接至該第一基板，每一加強框包含一或更多個開孔，每一模組的至少部分係位於一對應加強框中的一對應開孔中；其中在至少一加強框中，至少一開孔包含一通孔。
  13. 如申請專利範圍第12項之組件，其中該組件包含一或更多個測試墊，用於測試該組件，該組件可通過該通孔來使用，並且由該至少一加強框橫向圍繞。
  14. 如申請專利範圍第13項之組件，其中至少一測試墊為該第一基板的部分。
  15. 如申請專利範圍第13項之組件，其中至少一測試墊為至少部分位於該至 少一開孔中之一模組的部分。
  16. 如申請專利範圍第12項之組件，另包含一或更多個散熱器(Heat sinks)，每一散熱器位於一或更多個加強框中的一或更多個通孔之上，其中位於至少一加強框中的至少一通孔之上的至少一散熱器係附接至該加強框及/或至少部分位於該通孔中的至少一模組，每一散熱器具有高於各自之加強框的一熱傳導性。
  17. 如申請專利範圍第16項之組件，其中位於至少一加強框中的至少一通孔之上的至少一散熱器係附接至該加強框。
  18. 如申請專利範圍第16項之組件，其中位於至少一通孔之上的至少一散熱器係附接至至少部分位於該通孔中的至少一模組。
  19. 如申請專利範圍第12項之組件，其中該第一基板包含一第一對準機構(Alignment feature)，且至少一加強框包含一第二對準機構，且該第一與第二對準機構之一者為一凹槽，且該第一與第二對準機構之另一者為一突伸部，該突伸部不具有電性功能並且至少部分位於該凹槽中。
TW104117091A 2014-05-27 2015-05-27 具有加強框的積體電路組件及製造方法 TWI588966B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/288,064 US9355997B2 (en) 2014-03-12 2014-05-27 Integrated circuit assemblies with reinforcement frames, and methods of manufacture

Publications (2)

Publication Number Publication Date
TW201603235A true TW201603235A (zh) 2016-01-16
TWI588966B TWI588966B (zh) 2017-06-21

Family

ID=53373631

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104117091A TWI588966B (zh) 2014-05-27 2015-05-27 具有加強框的積體電路組件及製造方法

Country Status (4)

Country Link
US (2) US9355997B2 (zh)
KR (1) KR102275890B1 (zh)
TW (1) TWI588966B (zh)
WO (1) WO2015183884A2 (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109427699A (zh) * 2017-08-22 2019-03-05 矽品精密工业股份有限公司 电子封装件及其制法
US11171090B2 (en) 2018-08-30 2021-11-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
CN114038836A (zh) * 2021-11-24 2022-02-11 苏州科阳半导体有限公司 一种半导体芯片的封装结构及封装方法
TWI764172B (zh) * 2019-12-31 2022-05-11 力成科技股份有限公司 封裝結構及其製造方法
TWI778560B (zh) * 2021-03-30 2022-09-21 力成科技股份有限公司 封裝結構及其製造方法
US11984381B2 (en) 2021-05-13 2024-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package structure and method for forming the same

Families Citing this family (78)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10026720B2 (en) * 2015-05-20 2018-07-17 Broadpak Corporation Semiconductor structure and a method of making thereof
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9355997B2 (en) 2014-03-12 2016-05-31 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
DE112015000141B4 (de) * 2014-03-31 2021-11-11 Fuji Electric Co., Ltd. Stromrichtvorrichtung
US9214454B2 (en) * 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US9165793B1 (en) * 2014-05-02 2015-10-20 Invensas Corporation Making electrical components in handle wafers of integrated circuit packages
US9741649B2 (en) 2014-06-04 2017-08-22 Invensas Corporation Integrated interposer solutions for 2D and 3D IC packaging
US9691726B2 (en) * 2014-07-08 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming fan-out package structure
US9252127B1 (en) 2014-07-10 2016-02-02 Invensas Corporation Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture
KR102274742B1 (ko) * 2014-10-06 2021-07-07 삼성전자주식회사 패키지 온 패키지와 이를 포함하는 컴퓨팅 장치
TWI566305B (zh) * 2014-10-29 2017-01-11 巨擘科技股份有限公司 製造三維積體電路的方法
US10685904B2 (en) 2014-11-21 2020-06-16 Delta Electronics, Inc. Packaging device and manufacturing method thereof
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
CN104465418B (zh) * 2014-12-24 2017-12-19 通富微电子股份有限公司 一种扇出晶圆级封装方法
US9472484B2 (en) * 2015-02-17 2016-10-18 Avago Technologies General Ip (Singapore) Pte. Ltd. Semiconductor structure having thermal backside core
US9543384B2 (en) * 2015-02-26 2017-01-10 SK Hynix Inc. Semiconductor package
US20160329312A1 (en) * 2015-05-05 2016-11-10 Sean M. O'Mullan Semiconductor chip with offloaded logic
US9768149B2 (en) * 2015-05-19 2017-09-19 Micron Technology, Inc. Semiconductor device assembly with heat transfer structure formed from semiconductor material
KR102327738B1 (ko) * 2015-06-18 2021-11-17 삼성전기주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
US9478504B1 (en) 2015-06-19 2016-10-25 Invensas Corporation Microelectronic assemblies with cavities, and methods of fabrication
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US9806014B2 (en) * 2016-01-27 2017-10-31 Advanced Micro Devices, Inc. Interposer with beyond reticle field conductor pads
US20170256514A1 (en) * 2016-03-02 2017-09-07 Stmicroelectronics (Grenoble 2) Sas Optical electronic device and method of fabrication
EP3240027B1 (en) * 2016-04-25 2021-03-17 Technische Hochschule Ingolstadt Semiconductor package
EP3246941A1 (de) * 2016-05-18 2017-11-22 Siemens Aktiengesellschaft Elektronische baugruppe mit einem zwischen zwei schaltungsträgern angeordneten bauelement und verfahren zum fügen einer solchen baugruppe
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10411946B2 (en) * 2016-06-14 2019-09-10 TUPL, Inc. Fixed line resource management
US11081371B2 (en) * 2016-08-29 2021-08-03 Via Alliance Semiconductor Co., Ltd. Chip package process
US9922964B1 (en) * 2016-09-19 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with dummy die
KR20240036154A (ko) * 2016-10-07 2024-03-19 엑셀시스 코포레이션 직접-접합된 네이티브 상호접속부 및 능동 베이스 다이
CN108022905A (zh) * 2016-11-04 2018-05-11 超威半导体公司 使用多个金属层的转接板传输线
US10629519B2 (en) * 2016-11-29 2020-04-21 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
KR102653763B1 (ko) * 2016-12-31 2024-04-03 인텔 코포레이션 보강재를 가진 전자 패키지 조립체
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10410940B2 (en) * 2017-06-30 2019-09-10 Intel Corporation Semiconductor package with cavity
WO2019066848A1 (en) * 2017-09-28 2019-04-04 Intel Corporation POWER DISTRIBUTION FOR INTEGRATED BRIDGE CHIP USING TRENCH STRUCTURES
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
CN111448653B (zh) * 2017-12-13 2024-05-24 三菱电机株式会社 半导体装置及电力转换装置
US10991660B2 (en) * 2017-12-20 2021-04-27 Alpha Anc Omega Semiconductor (Cayman) Ltd. Semiconductor package having high mechanical strength
CN109950214A (zh) * 2017-12-20 2019-06-28 安世有限公司 芯片级封装半导体器件及其制造方法
KR102404058B1 (ko) * 2017-12-28 2022-05-31 삼성전자주식회사 반도체 패키지
DE112018006757T5 (de) * 2018-01-03 2020-10-01 Intel Corporation Gestapelte Halbleiter-Die-Architektur mit mehreren Disaggregationsschichten
DE102018102144A1 (de) * 2018-01-31 2019-08-01 Tdk Electronics Ag Elektronisches Bauelement
CN110197793A (zh) * 2018-02-24 2019-09-03 华为技术有限公司 一种芯片及封装方法
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
CN111651020A (zh) * 2018-05-24 2020-09-11 华为技术有限公司 散热装置及其制造方法、服务器
WO2020010136A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US11621208B2 (en) 2018-07-20 2023-04-04 Intel Corporation Thermal management solutions that reduce inductive coupling between stacked integrated circuit devices
US11823972B2 (en) * 2018-07-20 2023-11-21 Intel Corporation Thermal management solutions that reduce inductive coupling between stacked integrated circuit devices
JP7035920B2 (ja) * 2018-09-06 2022-03-15 三菱電機株式会社 半導体装置および電力変換装置
US10741534B2 (en) * 2018-09-28 2020-08-11 Intel Corporation Multi-die microelectronic device with integral heat spreader
US10770398B2 (en) * 2018-11-05 2020-09-08 Micron Technology, Inc. Graphics processing unit and high bandwidth memory integration using integrated interface and silicon interposer
US10700018B2 (en) * 2018-11-06 2020-06-30 Semiconductor Components Industries, Llc Reinforced semiconductor die and related methods
CN111211059B (zh) * 2018-11-22 2023-07-04 矽品精密工业股份有限公司 电子封装件及其制法与散热件
US11264332B2 (en) 2018-11-28 2022-03-01 Micron Technology, Inc. Interposers for microelectronic devices
CN113330557A (zh) 2019-01-14 2021-08-31 伊文萨思粘合技术公司 键合结构
KR102618460B1 (ko) * 2019-03-26 2023-12-29 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US11088086B2 (en) * 2019-04-26 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US12080672B2 (en) 2019-09-26 2024-09-03 Adeia Semiconductor Bonding Technologies Inc. Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive
US11901333B2 (en) * 2019-10-08 2024-02-13 Intel Corporation No mold shelf package design and process flow for advanced package architectures
US11018056B1 (en) 2019-11-01 2021-05-25 Micron Technology, Inc. Encapsulated solder TSV insertion interconnect
US10998271B1 (en) 2019-11-01 2021-05-04 Micron Technology, Inc. High density pillar interconnect conversion with stack to substrate connection
US11088114B2 (en) * 2019-11-01 2021-08-10 Micron Technology, Inc. High density pillar interconnect conversion with stack to substrate connection
KR20210075270A (ko) 2019-12-12 2021-06-23 삼성전자주식회사 반도체 모듈
US11145639B2 (en) * 2019-12-17 2021-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US20210272885A1 (en) * 2020-02-27 2021-09-02 Intel Corporation Interposer heat spreader
US11282825B2 (en) 2020-05-19 2022-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure
US11393763B2 (en) * 2020-05-28 2022-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out (info) package structure and method
JP7528557B2 (ja) * 2020-06-19 2024-08-06 日本電気株式会社 量子デバイス及びその製造方法
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11646255B2 (en) 2021-03-18 2023-05-09 Taiwan Semiconductor Manufacturing Company Limited Chip package structure including a silicon substrate interposer and methods for forming the same
US11955405B2 (en) * 2021-07-09 2024-04-09 Taiwan Semiconductor Manufacturing Company Limited Semiconductor package including thermal interface structures and methods of forming the same
US20230077877A1 (en) * 2021-09-10 2023-03-16 Advanced Semiconductor Engineering, Inc. Photonic package and method of manufacturing the same

Family Cites Families (155)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5567653A (en) 1994-09-14 1996-10-22 International Business Machines Corporation Process for aligning etch masks on an integrated circuit surface using electromagnetic energy
US5701233A (en) 1995-01-23 1997-12-23 Irvine Sensors Corporation Stackable modules and multimodular assemblies
US6008536A (en) 1997-06-23 1999-12-28 Lsi Logic Corporation Grid array device package including advanced heat transfer mechanisms
US6157076A (en) 1997-06-30 2000-12-05 Intersil Corporation Hermetic thin pack semiconductor device
US6624505B2 (en) 1998-02-06 2003-09-23 Shellcase, Ltd. Packaged integrated circuits and methods of producing thereof
JP3630551B2 (ja) 1998-04-02 2005-03-16 株式会社東芝 半導体記憶装置及びその製造方法
TW426931B (en) 1999-07-29 2001-03-21 Mosel Vitelic Inc Manufacturing method and structure of trench type capacitor having a cylindrical conductive plate
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
IL133453A0 (en) 1999-12-10 2001-04-30 Shellcase Ltd Methods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby
US6251796B1 (en) 2000-02-24 2001-06-26 Conexant Systems, Inc. Method for fabrication of ceramic tantalum nitride and improved structures based thereon
US6384473B1 (en) 2000-05-16 2002-05-07 Sandia Corporation Microelectronic device package with an integral window
US6492726B1 (en) 2000-09-22 2002-12-10 Chartered Semiconductor Manufacturing Ltd. Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
US6717254B2 (en) 2001-02-22 2004-04-06 Tru-Si Technologies, Inc. Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture
US6451650B1 (en) 2001-04-20 2002-09-17 Taiwan Semiconductor Manufacturing Company Low thermal budget method for forming MIM capacitor
US7061102B2 (en) 2001-06-11 2006-06-13 Xilinx, Inc. High performance flipchip package that incorporates heat removal with minimal thermal mismatch
US6856007B2 (en) 2001-08-28 2005-02-15 Tessera, Inc. High-frequency chip packages
US6787916B2 (en) 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
US6620701B2 (en) 2001-10-12 2003-09-16 Infineon Technologies Ag Method of fabricating a metal-insulator-metal (MIM) capacitor
US7633765B1 (en) 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
JP2004014714A (ja) 2002-06-05 2004-01-15 Mitsubishi Electric Corp キャパシタの製造方法
GB0221439D0 (en) 2002-09-16 2002-10-23 Enpar Technologies Inc Ion-exchange/electrochemical treatment of ammonia in waste-water
JP4056854B2 (ja) 2002-11-05 2008-03-05 新光電気工業株式会社 半導体装置の製造方法
US6919508B2 (en) 2002-11-08 2005-07-19 Flipchip International, Llc Build-up structures with multi-angle vias for chip to chip interconnects and optical bussing
US7400036B2 (en) 2002-12-16 2008-07-15 Avago Technologies General Ip Pte Ltd Semiconductor chip package with a package substrate and a lid cover
JP4390541B2 (ja) 2003-02-03 2009-12-24 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
TWI278975B (en) * 2003-03-04 2007-04-11 Siliconware Precision Industries Co Ltd Semiconductor package with heatsink
SG137651A1 (en) 2003-03-14 2007-12-28 Micron Technology Inc Microelectronic devices and methods for packaging microelectronic devices
JP2004281830A (ja) 2003-03-17 2004-10-07 Shinko Electric Ind Co Ltd 半導体装置用基板及び基板の製造方法及び半導体装置
US7102217B2 (en) 2003-04-09 2006-09-05 Micron Technology, Inc. Interposer substrates with reinforced interconnect slots, and semiconductor die packages including same
US7012326B1 (en) 2003-08-25 2006-03-14 Xilinx, Inc. Lid and method of employing a lid on an integrated circuit
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
TWI251916B (en) 2003-08-28 2006-03-21 Phoenix Prec Technology Corp Semiconductor assembled heat sink structure for embedding electronic components
US7031162B2 (en) 2003-09-26 2006-04-18 International Business Machines Corporation Method and structure for cooling a dual chip module with one high power chip
US7183643B2 (en) 2003-11-04 2007-02-27 Tessera, Inc. Stacked packages and systems incorporating the same
US7049170B2 (en) 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
US7115988B1 (en) 2004-01-21 2006-10-03 Altera Corporation Bypass capacitor embedded flip chip package lid and stiffener
KR20050076742A (ko) 2004-01-22 2005-07-27 마츠시타 덴끼 산교 가부시키가이샤 광전송로 기판의 제조방법, 광전송로 기판, 광전송로내장기판, 광전송로 내장기판의 제조방법 및 데이터처리장치
JP4441328B2 (ja) 2004-05-25 2010-03-31 株式会社ルネサステクノロジ 半導体装置及びその製造方法
JP3972209B2 (ja) 2004-05-26 2007-09-05 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
US7786591B2 (en) 2004-09-29 2010-08-31 Broadcom Corporation Die down ball grid array package
US6947275B1 (en) 2004-10-18 2005-09-20 International Business Machines Corporation Fin capacitor
WO2006059556A1 (ja) 2004-12-02 2006-06-08 Murata Manufacturing Co., Ltd. 電子部品及びその製造方法
KR100594952B1 (ko) 2005-02-04 2006-06-30 삼성전자주식회사 웨이퍼 레벨 패키징 캡 및 그 제조방법
US7897503B2 (en) 2005-05-12 2011-03-01 The Board Of Trustees Of The University Of Arkansas Infinitely stackable interconnect device and method
US7215032B2 (en) 2005-06-14 2007-05-08 Cubic Wafer, Inc. Triaxial through-chip connection
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
JP2007042719A (ja) 2005-08-01 2007-02-15 Nec Electronics Corp 半導体装置
JP4889974B2 (ja) 2005-08-01 2012-03-07 新光電気工業株式会社 電子部品実装構造体及びその製造方法
US7906803B2 (en) 2005-12-06 2011-03-15 Canon Kabushiki Kaisha Nano-wire capacitor and circuit device therewith
US7344954B2 (en) 2006-01-03 2008-03-18 United Microelectonics Corp. Method of manufacturing a capacitor deep trench and of etching a deep trench opening
US7560761B2 (en) 2006-01-09 2009-07-14 International Business Machines Corporation Semiconductor structure including trench capacitor and trench resistor
US7977579B2 (en) 2006-03-30 2011-07-12 Stats Chippac Ltd. Multiple flip-chip integrated circuit package system
US7390700B2 (en) 2006-04-07 2008-06-24 Texas Instruments Incorporated Packaged system of semiconductor chips having a semiconductor interposer
US7510928B2 (en) 2006-05-05 2009-03-31 Tru-Si Technologies, Inc. Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques
US7513035B2 (en) 2006-06-07 2009-04-07 Advanced Micro Devices, Inc. Method of integrated circuit packaging
JP5107539B2 (ja) 2006-08-03 2012-12-26 新光電気工業株式会社 半導体装置および半導体装置の製造方法
TWI367557B (en) 2006-08-11 2012-07-01 Sanyo Electric Co Semiconductor device and manufaturing method thereof
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US7550857B1 (en) 2006-11-16 2009-06-23 Amkor Technology, Inc. Stacked redistribution layer (RDL) die assembly package
US20080128897A1 (en) 2006-12-05 2008-06-05 Tong Wa Chao Heat spreader for a multi-chip package
US7670921B2 (en) 2006-12-28 2010-03-02 International Business Machines Corporation Structure and method for self aligned vertical plate capacitor
US7800916B2 (en) 2007-04-09 2010-09-21 Endicott Interconnect Technologies, Inc. Circuitized substrate with internal stacked semiconductor chips, method of making same, electrical assembly utilizing same and information handling system utilizing same
US8039309B2 (en) 2007-05-10 2011-10-18 Texas Instruments Incorporated Systems and methods for post-circuitization assembly
KR100909322B1 (ko) 2007-07-02 2009-07-24 주식회사 네패스 초박형 반도체 패키지 및 그 제조방법
KR101572600B1 (ko) 2007-10-10 2015-11-27 테세라, 인코포레이티드 다층 배선 요소와 마이크로전자 요소가 실장된 어셈블리
CN101878527B (zh) 2007-11-30 2012-09-26 斯盖沃克斯瑟路申斯公司 使用倒装芯片安装的晶片级封装
US7928548B2 (en) 2008-01-07 2011-04-19 International Business Machines Corporation Silicon heat spreader mounted in-plane with a heat source and method therefor
US8787060B2 (en) 2010-11-03 2014-07-22 Netlist, Inc. Method and apparatus for optimizing driver load in a memory package
SG142321A1 (en) 2008-04-24 2009-11-26 Micron Technology Inc Pre-encapsulated cavity interposer
US8008764B2 (en) 2008-04-28 2011-08-30 International Business Machines Corporation Bridges for interconnecting interposers in multi-chip integrated circuits
US7863096B2 (en) * 2008-07-17 2011-01-04 Fairchild Semiconductor Corporation Embedded die package and process flow using a pre-molded carrier
JP2010034403A (ja) 2008-07-30 2010-02-12 Shinko Electric Ind Co Ltd 配線基板及び電子部品装置
US8101494B2 (en) 2008-08-14 2012-01-24 International Business Machines Corporation Structure, design structure and method of manufacturing a structure having VIAS and high density capacitors
US8257985B2 (en) * 2008-09-25 2012-09-04 Texas Instruments Incorporated MEMS device and fabrication method
JP5284235B2 (ja) * 2008-09-29 2013-09-11 日本特殊陶業株式会社 半導体パッケージ
KR20100037300A (ko) 2008-10-01 2010-04-09 삼성전자주식회사 내장형 인터포저를 갖는 반도체장치의 형성방법
JP2010092977A (ja) 2008-10-06 2010-04-22 Panasonic Corp 半導体装置及びその製造方法
MY149251A (en) 2008-10-23 2013-07-31 Carsem M Sdn Bhd Wafer-level package using stud bump coated with solder
KR101015704B1 (ko) 2008-12-01 2011-02-22 삼성전기주식회사 칩 내장 인쇄회로기판 및 그 제조방법
US8354304B2 (en) 2008-12-05 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant
US7858441B2 (en) 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
JP5308145B2 (ja) 2008-12-19 2013-10-09 ルネサスエレクトロニクス株式会社 半導体装置
US8343806B2 (en) 2009-03-05 2013-01-01 Raytheon Company Hermetic packaging of integrated circuit components
US7989270B2 (en) 2009-03-13 2011-08-02 Stats Chippac, Ltd. Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors
US8216887B2 (en) 2009-05-04 2012-07-10 Advanced Micro Devices, Inc. Semiconductor chip package with stiffener frame and configured lid
EP2273545B1 (en) 2009-07-08 2016-08-31 Imec Method for insertion bonding and kit of parts for use in said method
US8143097B2 (en) 2009-09-23 2012-03-27 Stats Chippac, Ltd. Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
JP5330184B2 (ja) 2009-10-06 2013-10-30 新光電気工業株式会社 電子部品装置
US8531012B2 (en) 2009-10-23 2013-09-10 Stats Chippac, Ltd. Semiconductor device and method of forming a shielding layer over a semiconductor die disposed in a cavity of an interconnect structure and grounded through the die TSV
JP5295932B2 (ja) * 2009-11-02 2013-09-18 新光電気工業株式会社 半導体パッケージ及びその評価方法、並びにその製造方法
US8519537B2 (en) 2010-02-26 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US8378480B2 (en) 2010-03-04 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy wafers in 3DIC package assemblies
US8541886B2 (en) 2010-03-09 2013-09-24 Stats Chippac Ltd. Integrated circuit packaging system with via and method of manufacture thereof
US8183696B2 (en) 2010-03-31 2012-05-22 Infineon Technologies Ag Packaged semiconductor device with encapsulant embedding semiconductor chip that includes contact pads
FR2960339B1 (fr) 2010-05-18 2012-05-18 Commissariat Energie Atomique Procede de realisation d'elements a puce munis de rainures d'insertion de fils
US8349653B2 (en) 2010-06-02 2013-01-08 Maxim Integrated Products, Inc. Use of device assembly for a generalization of three-dimensional metal interconnect technologies
KR101394205B1 (ko) 2010-06-09 2014-05-14 에스케이하이닉스 주식회사 반도체 패키지
US8426961B2 (en) 2010-06-25 2013-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded 3D interposer structure
US20120001339A1 (en) 2010-06-30 2012-01-05 Pramod Malatkar Bumpless build-up layer package design with an interposer
KR101129909B1 (ko) 2010-07-20 2012-03-23 주식회사 하이닉스반도체 반도체 소자의 필라형 캐패시터 및 그 형성방법
US8598695B2 (en) 2010-07-23 2013-12-03 Tessera, Inc. Active chip on carrier or laminated chip having microelectronic element embedded therein
US8847376B2 (en) 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
TWI445104B (zh) 2010-08-25 2014-07-11 Advanced Semiconductor Eng 半導體封裝結構及其製程
US9343436B2 (en) 2010-09-09 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked package and method of manufacturing the same
US8617926B2 (en) 2010-09-09 2013-12-31 Advanced Micro Devices, Inc. Semiconductor chip device with polymeric filler trench
US8830689B2 (en) 2010-09-16 2014-09-09 Samsung Electro-Mechanics Co., Ltd. Interposer-embedded printed circuit board
WO2012037536A2 (en) 2010-09-18 2012-03-22 Fairchild Semiconductor Corporation Packaging to reduce stress on microelectromechanical systems
WO2012048137A2 (en) 2010-10-06 2012-04-12 The Charles Stark Draper Laboratory, Inc. Flexible circuits and methods for making the same
US8666505B2 (en) * 2010-10-26 2014-03-04 Medtronic, Inc. Wafer-scale package including power source
US8525318B1 (en) 2010-11-10 2013-09-03 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8502340B2 (en) 2010-12-09 2013-08-06 Tessera, Inc. High density three-dimensional integrated capacitors
US8575493B1 (en) 2011-02-24 2013-11-05 Maxim Integrated Products, Inc. Integrated circuit device having extended under ball metallization
US9018094B2 (en) 2011-03-07 2015-04-28 Invensas Corporation Substrates with through vias with conductive features for connection to integrated circuit elements, and methods for forming through vias in substrates
JP2012231096A (ja) 2011-04-27 2012-11-22 Elpida Memory Inc 半導体装置及びその製造方法
JP2012256846A (ja) 2011-05-16 2012-12-27 Elpida Memory Inc 半導体装置の製造方法
JP5994776B2 (ja) 2011-06-06 2016-09-21 住友ベークライト株式会社 半導体パッケージ、半導体装置、半導体パッケージの製造方法
US8409923B2 (en) 2011-06-15 2013-04-02 Stats Chippac Ltd. Integrated circuit packaging system with underfill and method of manufacture thereof
US8497558B2 (en) 2011-07-14 2013-07-30 Infineon Technologies Ag System and method for wafer level packaging
US9125333B2 (en) 2011-07-15 2015-09-01 Tessera, Inc. Electrical barrier layers
EP2555239A3 (en) 2011-08-04 2013-06-05 Sony Mobile Communications AB Thermal package with heat slug for die stacks
TWI492680B (zh) 2011-08-05 2015-07-11 Unimicron Technology Corp 嵌埋有中介層之封裝基板及其製法
US8816404B2 (en) 2011-09-16 2014-08-26 Stats Chippac, Ltd. Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant
US20130082383A1 (en) 2011-10-03 2013-04-04 Texas Instruments Incorporated Electronic assembly having mixed interface including tsv die
KR101906408B1 (ko) 2011-10-04 2018-10-11 삼성전자주식회사 반도체 패키지 및 그 제조 방법
KR101932665B1 (ko) 2011-10-10 2018-12-27 삼성전자 주식회사 반도체 패키지
US9287191B2 (en) 2011-10-12 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device package and method
KR20130042936A (ko) 2011-10-19 2013-04-29 에스케이하이닉스 주식회사 칩 캐리어, 이를 이용한 반도체 칩, 반도체 패키지, 및 그 제조방법들
WO2013062533A1 (en) 2011-10-25 2013-05-02 Intel Corporation Interposer for hermetic sealing of sensor chips and for their integration with integrated circuit chips
US9269646B2 (en) 2011-11-14 2016-02-23 Micron Technology, Inc. Semiconductor die assemblies with enhanced thermal management and semiconductor devices including same
US8518753B2 (en) 2011-11-15 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Assembly method for three dimensional integrated circuit
JP5970078B2 (ja) 2011-12-02 2016-08-17 インテル・コーポレーション デバイス相互接続の変化を可能にする積層メモリ
US8975711B2 (en) 2011-12-08 2015-03-10 Infineon Technologies Ag Device including two power semiconductor chips and manufacturing thereof
US9548251B2 (en) 2012-01-12 2017-01-17 Broadcom Corporation Semiconductor interposer having a cavity for intra-interposer die
US8686570B2 (en) 2012-01-20 2014-04-01 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-dimensional integrated circuit structures and methods of forming the same
JP2013183120A (ja) 2012-03-05 2013-09-12 Elpida Memory Inc 半導体装置
US9000557B2 (en) 2012-03-17 2015-04-07 Zvi Or-Bach Semiconductor device and structure
US8557632B1 (en) 2012-04-09 2013-10-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8872349B2 (en) 2012-09-11 2014-10-28 Intel Corporation Bridge interconnect with air gap in package assembly
US20140091461A1 (en) 2012-09-30 2014-04-03 Yuci Shen Die cap for use with flip chip package
US9136159B2 (en) 2012-11-15 2015-09-15 Amkor Technology, Inc. Method and system for a semiconductor for device package with a die-to-packaging substrate first bond
US8796072B2 (en) 2012-11-15 2014-08-05 Amkor Technology, Inc. Method and system for a semiconductor device package with a die-to-die first bond
US9040349B2 (en) 2012-11-15 2015-05-26 Amkor Technology, Inc. Method and system for a semiconductor device package with a die to interposer wafer first bond
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9257355B2 (en) 2013-02-11 2016-02-09 The Charles Stark Draper Laboratory, Inc. Method for embedding a chipset having an intermediary interposer in high density electronic modules
US20140246227A1 (en) 2013-03-01 2014-09-04 Bridge Semiconductor Corporation Method of making cavity substrate with built-in stiffener and cavity substrate manufactured thereby
US9704809B2 (en) * 2013-03-05 2017-07-11 Maxim Integrated Products, Inc. Fan-out and heterogeneous packaging of electronic components
US9111930B2 (en) 2013-03-12 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package on-package with cavity in interposer
JP6110734B2 (ja) 2013-06-06 2017-04-05 ルネサスエレクトロニクス株式会社 半導体装置
US9685414B2 (en) 2013-06-26 2017-06-20 Intel Corporation Package assembly for embedded die and associated techniques and configurations
US9355997B2 (en) 2014-03-12 2016-05-31 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9165793B1 (en) 2014-05-02 2015-10-20 Invensas Corporation Making electrical components in handle wafers of integrated circuit packages
US9524883B2 (en) 2014-05-13 2016-12-20 Invensas Corporation Holding of interposers and other microelectronic workpieces in position during assembly and other processing
US9252127B1 (en) 2014-07-10 2016-02-02 Invensas Corporation Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109427699A (zh) * 2017-08-22 2019-03-05 矽品精密工业股份有限公司 电子封装件及其制法
US11171090B2 (en) 2018-08-30 2021-11-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
TWI772674B (zh) * 2018-08-30 2022-08-01 台灣積體電路製造股份有限公司 封裝體及其製造方法
TWI764172B (zh) * 2019-12-31 2022-05-11 力成科技股份有限公司 封裝結構及其製造方法
US11367678B2 (en) 2019-12-31 2022-06-21 Powertech Technology Inc. Package structure and manufacturing method thereof
TWI778560B (zh) * 2021-03-30 2022-09-21 力成科技股份有限公司 封裝結構及其製造方法
US11848318B2 (en) 2021-03-30 2023-12-19 Powertech Technology Inc. Package structure and manufacturing method thereof
US11984381B2 (en) 2021-05-13 2024-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package structure and method for forming the same
CN114038836A (zh) * 2021-11-24 2022-02-11 苏州科阳半导体有限公司 一种半导体芯片的封装结构及封装方法

Also Published As

Publication number Publication date
WO2015183884A2 (en) 2015-12-03
WO2015183884A3 (en) 2016-01-21
US9887166B2 (en) 2018-02-06
KR20170013310A (ko) 2017-02-06
US20150262972A1 (en) 2015-09-17
TWI588966B (zh) 2017-06-21
KR102275890B1 (ko) 2021-07-08
US9355997B2 (en) 2016-05-31
US20160276294A1 (en) 2016-09-22

Similar Documents

Publication Publication Date Title
TWI588966B (zh) 具有加強框的積體電路組件及製造方法
US11205600B2 (en) Integrated circuits protected by substrates with cavities, and methods of manufacture
US9536862B2 (en) Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture
US11302616B2 (en) Integrated interposer solutions for 2D and 3D IC packaging
KR101765966B1 (ko) 윈도우 삽입된 다이 패키징
TWI514542B (zh) 具有圍繞矽穿封裝孔（ＴＰＶ）的末端部分之開口的晶粒封裝及使用該晶粒封裝之層疊封裝（ＰｏＰ）
CN110660675A (zh) 半导体装置及形成方法
KR102524244B1 (ko) 반도체 패키지들에서의 방열 및 그 형성 방법
KR102618919B1 (ko) 통합 팬 아웃 패키지 및 방법
TWI803310B (zh) 積體電路元件和其形成方法
CN114975359A (zh) 半导体器件和制造方法
TW202243175A (zh) 半導體封裝及製造半導體封裝的方法
KR20220051780A (ko) 반도체 디바이스 및 제조 방법
TWI790702B (zh) 半導體封裝及製造半導體封裝的方法
CN220400576U (zh) 器件封装及半导体封装