CN104465418B - 一种扇出晶圆级封装方法 - Google Patents

一种扇出晶圆级封装方法 Download PDF

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CN104465418B
CN104465418B CN201410818160.7A CN201410818160A CN104465418B CN 104465418 B CN104465418 B CN 104465418B CN 201410818160 A CN201410818160 A CN 201410818160A CN 104465418 B CN104465418 B CN 104465418B
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layer
metal
chip
fan
wafer level
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CN104465418A (zh
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石磊
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Tongfu Microelectronics Co Ltd
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Tongfu Microelectronics Co Ltd
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Priority to CN201410818160.7A priority Critical patent/CN104465418B/zh
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Priority to US14/975,894 priority patent/US20160189983A1/en
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Abstract

本发明提供一种扇出晶圆级封装方法,包括以下工艺步骤:提供载板;在载板上贴上一层可剥离保护膜,并在特定区域形成图形开口;在所述的图形开口中形成金属层;将带有金属层的保护膜从载板上剥离;将芯片安装在所述的在金属层上,并进行打线或植球;对芯片和金属布线进行塑封。本发明的技术方案,工艺简单,封装精度高,成本低,能够适用于高密集的I/O端封装结构中,特别适用于薄型封装工艺中。

Description

一种扇出晶圆级封装方法
技术领域
本发明涉及半导体封装领域,具体地说,涉及一种高集成扇出晶圆级封装方法。
背景技术
在当前的半导体行业中,电子封装已经成为行业发展的一个重要方面,几十年的封装技术的发展,使高密度、小尺寸的封装要求成为封装的主流方向。扇出晶圆级是在晶圆级加工的嵌入式封装,也是一种I/O数较多、集成灵活性好的主要先进封装工艺。它能在一个封装内实现垂直和水平方向多芯片集成且不用衬底。这样,扇出晶圆级技术目前正在发展成为下一代封装技术,如多芯片、低剖面封装和3D SiP。随着电子产品向更薄、更轻、更高引脚密度、更低成本方面发展,采用单颗芯片封装技术已经逐渐无法满足产业需求,而扇出晶圆级封装技术的出现为封装行业想低成本封装发展提供了契机。
圆片级扇出结构,其通过重够圆片和圆片级再布线方式,实现芯片扇出结构的塑封,最终切割成单颗封装体。但其仍存在如下不足:1)芯片外面包覆塑料塑封强度偏低,扇出结构的支撑强度不够,在薄型封装中难以应用;2)扇出结构单一,应用不够广泛;3)现有工艺不利于产品的低成本化;4)I/O端密度相对较低。
中国专利201210243958.4公开了一种扇出型圆片级芯片封装方法,包括芯片、金属微结构、高密度布线层、硅腔体、键合层和焊球凸点,在芯片上通过溅射、光刻、电镀等工艺形成金属微结构,将芯片倒装在高密度布线层上,用光学掩膜、刻蚀等方法在硅腔体上形成下凹的硅腔,所述硅腔体将芯片扣置在硅腔内,所述高密度布线层与硅腔体通过键合层键合,加热使包封料层和键合层固化成形。但该发明工艺复杂,成本高,不适合薄型封装工艺。
中国专利201110032264.1公开了一种高集成度晶圆扇出封装结构,包括:被封装单元,包括芯片及无源器件,所述被封装单元具有功能面;与被封装单元的功能面相对的另一面形成有封料层,所述封料层对被封装单元进行封装固化,所述封料层表面对应于被封装单元之间设有凹槽。中国专利201110032591.7公开了一种高集成度晶圆扇出封装方法,包括步骤:在载板上形成胶合层;将由芯片和无源器件组成的被封装单元的功能面贴于所述胶合层上;将载板贴有芯片和无源器件的一面形成封料层,进行封装固化,所述封料层表面对应于被封装单元之间设有凹槽;去除所述载板和胶合层。以上专利可以避免封料层在晶圆封装的后续过程中出现翘曲变形,提高晶圆封装成品的质量。
中国专利201110069815.1公开了一种扇出系统级封装方法,包括以下步骤:提供载板,在载板上形成剥离膜,在剥离膜上形成保护层,在保护层中形成再布线金属层,在保护层上形成与再布线金属层导通的布线封装层,在布线封装层上形成引线键合封装层,各组封装层之间相互电连接,去除载板及剥离膜,裸露出第一保护层中的再布线金属,在裸露的再布线金属上形成金属焊球。该专利的技术方案可以降低系统内电阻、电感以及芯片间的干扰因素。
上述现有技术虽然对封装方法进行了改进,但并未解决扇出晶圆级工艺中的工艺复杂、成本高的问题,不适用于薄型产品的封装工艺。
发明内容
为了克服上述缺点,本发明提供一种扇出晶圆级封装方法,采用先去除载板再进行布线的工艺,可用于各类扇出型圆片级芯片封装。本发明的技术方案,工艺简单,成本低,能够适用于高密集的I/O端封装结构中,特别适用于薄型封装工艺中。
本发明的技术方案是:一种扇出晶圆级封装方法,包括以下工艺步骤:
(1)提供载板;
(2)在载板上贴上可剥离保护膜,并在特定区域形成图形开口;
(3)在所述图形开口中形成至少一层金属层;
(4)去除载板;
(5)将芯片安装在所述金属层上,并进行打线或植球;
(6)对芯片和金属布线进行塑封;
其中,所述可剥离保护膜的非图形开口区域在所述封装方法过程中保留。
更优地,所述金属层为两层,其中第一金属层为锡层或银层,第二金属层为铜、镍、钯、金中的一种。
更为优选地,所述芯片安装为正装或倒装;在芯片安装步骤中,通过CCD影像对位装置检测芯片的偏移情况,通过金属针管吸取多余的阻焊剂;通过芯片卡爪纠正芯片的偏移。所述芯片卡爪具有四个方向爪指,根据CCD影像对位装置的监控结果对芯片进行微移,使其位于准确的位置。
此外,还包括以下步骤:对芯片和金属布线进行塑封。在所述第二金属层以及靠近第二金属层的保护膜上形成介质保护层,所述介质保护层不完全覆盖第二金属层,在金属层处形成开口。在形成的开口上形成再布线层;在所述再布线层上植球。
此外,
所述载板材料为玻璃、氧化铝、单晶硅、氮化铝、氧化铍、碳化硅、蓝宝石中的一种。
所述可剥离保护膜为UV膜、PET膜、PE膜、OPP膜、聚乙烯醇膜中的一种。
所述塑封材料为硅树脂、环氧树脂、聚酰亚胺、酚醛树脂、聚氨酯、丙烯酸树脂中的一种。
所述的介质保护层为油墨、SiO2薄膜、UV膜、PET膜、聚酯膜、PP膜、PE膜中的一种。
与现有技术相比,本发明的有益效果是:本发明提供的扇出晶圆级封装方法,工艺简单,成本低,绿色环保,且能够适用于高密集的I/O端封装结构中,特别适用于薄型封装工艺中,而且封装过程芯片产生的偏移小,精确度高。
附图说明
图1是本发明步骤(1)载板结构示意图;
图2是本发明步骤(2)形成保护膜后的结构示意图;
图3是本发明步骤(2)保护膜开口后的结构示意图;
图4是本发明步骤(3)形成第一层金属层后的结构示意图;
图5是本发明步骤(3)形成第二层金属层后的结构示意图;
图6是本发明步骤(4)载板剥离时的结构示意图;
图7是本发明步骤(5)装片打线或植球后的结构示意图;
图8是本发明步骤(6)塑封后的结构示意图;
图9是本发明形成介质保护层并形成开口后的结构示意图;
图10是本发明形成再布线层后的结构示意图;
图11是本发明植球后的结构示意图;
图12是本发明封装时的CCD影像对位装置及金属针管结构示意图;
图13是本发明在封装时的芯片卡爪结构示意图。
图中,101载板,201可剥离保护膜,301第一金属层,401第二金属层,501芯片,502金属线,601塑封材料,701介质保护层,801再布线层,901锡球,1001为CCD影像对位装置、1002为金属针管、1003为芯片卡爪。
具体实施方式
以下结合附图和实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅用以解释本发明,并不用于限定本发明。
在本发明的第一实施方式中,提供了一种扇出晶圆级封装方法,包括以下工艺步骤:
(1)提供载板;
(2)在载板上贴上可剥离保护膜,并在特定区域形成图形开口;
(3)在所述图形开口中形成至少一层金属层;
(4)去除载板;
(5)将芯片安装在所述的在金属层上,并进行打线或植球;
(6)对芯片和金属布线用进行塑封;
其中,所述可剥离保护膜的非图形开口区域在所述封装方法过程中保留。
如图1所示,在上述步骤(1)中,在进行封装工艺前先提供一个集成电路所用的载板(图中101),载板材料为玻璃、氧化铝、单晶硅、氮化铝、氧化铍、碳化硅、蓝宝石中的一种。所述载板具有较好的硬度和平整度,降低封装器件的失效比例,防止封装过程中出现翘曲。选用载板的原则是后续步骤中易被剥离,抗腐蚀能力强,不会与胶合层的接触而发生物理和化学性能的改变,因此可以进行重复利用。
图2是本发明步骤(2)形成保护膜后的结构示意图。即在所述载板的正面贴上一层可剥离保护膜(图2中201所示),保护膜可以选用的材质有多种,比如UV膜、PET膜、PE膜、OPP膜、聚乙烯醇膜中的一种,这里优选UV膜,UV膜具有易剥离性,容易从载板上剥离下来,它可以耐130~150℃高温,收缩率低,柔韧性好,容易剥离,不断胶。在形成UV膜时可以选用丝网印刷法,印刷厚度为10-20μm,印刷完毕后,采用光刻法在保护膜的特定区域形成图形开口,具体方法是通过紫外光透过掩膜板将图像转移到UV胶上,UV胶在紫外光照射下会发生固化反应形成膜,然后将没有固化的区域冲洗掉,即就在特定区域形成了开口。如果采用PET膜、PE膜、OPP膜、聚乙烯醇膜等工艺稍复杂,需先将保护膜的表面做等离子处理,或在保护膜的表面涂氟处理,或涂硅油处理等,使其表现出极轻且稳定的可剥离性,然后采用等离子干蚀的方法在特定区域形成开口。图3是本发明步骤2)保护膜开口后的结构示意图,开口后形成镂空的槽。
图4、图5为步骤(3)中在所述的图形开口上形成金属层后的结构示意图,在该步骤中,至少形成一金属层。其中图4为形成第一层金属层后的结构示意图,图中,101为载板,201为可剥离保护膜,301为第一金属层。可选地,可在第一金属层301的基础上形成第二金属层。图5为形成第二层金属层后的结构示意图,401为第二金属层。其中第一金属层为锡层或银层,第二金属层为铜、镍、钯、金中的一种,形成所述金属层的方法为电镀、化学镀、真空蒸镀法、化学气相沉积法中的一种。
在形成第一金属层时,优选使用化学镀法或者溅射法,溅射法是在高真空充入适量的氩气,在阴极(柱状靶或平面靶)和阳极(镀膜室壁)之间施加几百K直流电压,在镀膜室内产生磁控型异常辉光放电,使氩气发生电离,氩离子被阴极加速并轰击阴极靶表面,将靶材表面原子溅射出来沉积在基底表面上形成薄膜层,溅射法镀层与基材的结合力强、镀层致密、均匀。在形成第二金属层时,优选使用电镀法,因为在在半导体芯片封装工艺中,线宽通常为微米、亚微米级(0.15—0.09um),如此精细的线宽对后续的工艺比如植球提出了更高的要求,得出的金属镀层必须有足够的抗剥离强度。因为有了前述的第一金属层,在形成第二金属层时,采用电镀法工艺简单,且和第一金属层结合紧密、均匀。
图6为去除载板的示意图,在该步骤中,由于前述采用的是可剥离保护膜,所以在本步骤很容易实现载板剥离,载板剥离的目的是为了便于后续芯片安装和打线或植球,本发明中采用先载板分离后打线或植球的方法,可以降低成本,且使封装后的产品更薄,利于向密集化方向发展。
图7为本发明步骤(5)装片打线或植球后的结构示意图;图中,501为芯片,502为金属线。去除载板后,将已经备好的芯片金属正装或倒装与第一金属层连接在一起,图7示意了正装的情况。连接的方式有热压焊接、焊料焊接、超声焊接、粘胶连接等,然后打线或植球焊接,打线或植球焊接的方式主要有热压焊、超声焊、金丝球焊三种。在本发明的该步骤中,优选使用超声焊、金丝球焊。
在芯片安装过程中,芯片发生偏斜是一个相当难处理的技术问题,如果偏移距离过大,就会导致良率的降低。如何迅速地消除造成芯片偏斜,一直是一个技术难题题。发明人在实践中发现,在芯片安装时多余的助焊剂是造成芯片偏移的原因之一,因此发明人在进行芯片安装时,在机器上安装了CCD影像对位装置(如图12中1001)中的,用来检测芯片的偏移情况,且安装了金属针管(如图12中1002)用来吸取多余的阻焊剂,同时安装了芯片卡爪(如图12中1003)用来纠正芯片的偏移,其中芯片卡爪具有四个方向的爪指,同时根据CCD影像对位装置的监控结果对芯片进行微移,使其位于准确的位置。
图8是本发明步骤(6)塑封后的结构示意图;芯片安装和金属布线后要进行塑封,进行塑封的材料为硅树脂、聚酰亚胺、酚醛树脂、环氧树脂、聚氨酯、丙烯酸树脂中的一种,为了进一步改善封装材料的性能,本发明一个优选的实施方式为在上述封装材料中添加适量的氧化铝粉或气相二氧化硅来对塑封材料进行改性,改性后的塑封材料粘接强度高、电性能好、耐化学腐蚀性好、耐温宽、收缩率低、密封性能好,塑型容易,在固化过程中不产生挥发性物质,不易产生气孔、裂纹和剥离等现象。封装的具体工艺是先用有机导电胶将芯片粘接在框架上,再通过引线键合将芯片的铝焊块和框架的管脚用金丝或铝丝连接起来,然后用塑封材料经过注塑模包封成型,最后外引线镀上一层铅锡合金,再从条带上冲切下来,按照所需要的形状成型。
塑封完毕后进行再布线,所述再布线的步骤包括:在所述第二金属层上设置介质保护层;所述介质保护层不完全覆盖第二金属层;在介质保护层未覆盖的第二金属层之上形成再布线层,所述再布线层至少为一层。如图9所示,述第二金属层以及靠近第二金属层的保护膜上形成介质保护层,所述介质保护层不完全覆盖第二金属层,并在金属层处形成开口,使得介质保护层不完全覆盖金属层。图9是本发明形成介质保护层后的结构示意图;图中,601为塑封,701为已经开口的介质保护层,形成的介质保护层可以为感光油墨、热固性油墨、涂料、SiO2薄膜、UV胶、PET膜、聚酯膜、pp膜、PE膜中的一种,形成介质保护层的方法有喷涂法、丝网印刷法、气相沉积法。如果该步骤中形成介质保护层选用UV胶,就可以采用光刻法进行开口,具体原理同前述步骤2)。如果选用其它材料,就需要采用等离子体干蚀法进行选择性蚀刻来实现介质保护层上的开口。在金属层形成的开口上形成再布线层。图10是本发明形成再布线层后的结构示意图;图中,801为所形成的再布线层。该再布线层至少为一层,可以为铜、银、锡、镍、钯、金中的一种或其合金中的一种。形成的再布线层的目的是为了增加前述第二金属层的厚度,以便于后续植球的顺利进行,提高良率,在该步骤中,其中一种可选的形成金属层的方法是化学镀,即不需要外在电流通过的情况下就可以在基体表面形成镀层,其工艺简便、节能、环保,而且镀层均匀,使用寿命也比其它方法长。
在所述再布线层上植球或者涂覆绝缘层。图11以植球为例进行说明,该图为植球后的结构示意图,即将微小尺寸的焊球放置到形成的再布线层上,然后经过回流焊炉固化,使其和再布线层紧密连接在一起,形成焊球凸点阵列,图中901为锡球。植球法技术可靠,工艺简单,效率高,可以大大降低封装成本。
采用本发明提供的扇出晶圆级封装方法,工艺简单,成本低,绿色环保,且能够适用于高密集的I/O端封装结构中,特别适用于薄型封装工艺中。
上述说明示出并描述了本发明的优选实施例,如前所述,应当理解本发明并非局限于本文所披露的形式,不应看作是对其他实施例的排除,而可用于各种其他组合、修改和环境,并能够在本文所述发明构想范围内,通过上述教导或相关领域的技术或知识进行改动。而本领域人员所进行的改动和变化不脱离本发明的精神和范围,则都应在本发明所附权利要求的保护范围内。

Claims (10)

1.一种扇出晶圆级封装方法,包括以下工艺步骤:
提供载板;
在所述载板上贴可剥离保护膜,并在所述可剥离保护膜上形成图形开口;
在所述图形开口中形成金属层,所述金属层为一层以上;
去除所述载板;
去除所述载板后,将芯片与所述金属层连接;
将所述芯片和所述金属层连接之后,进行塑封和再布线;
其中,所述可剥离保护膜的非图形开口区域在所述封装方法过程中保留。
2.如权利要求1所述的扇出晶圆级封装方法,其特征在于:所述金属层为两层,其中第一金属层与第二金属层为锡、银、铜、镍、钯、金中的一种;第一金属层为靠近载板的金属层,第二金属层位于第一金属层之上。
3.如权利要求2所述的扇出晶圆级封装方法,其特征在于:所述第一金属层和第二金属层为不同金属材料。
4.如权利要求3所述的扇出晶圆级封装方法,其特征在于:所述再布线的步骤包括:在所述第二金属层上设置介质保护层;所述介质保护层不完全覆盖第二金属层;在介质保护层未覆盖的第二金属层之上形成再布线层,所述再布线层至少为一层。
5.如权利要求4所述的扇出晶圆级封装方法,其特征在于:再布线之后,在所述再布线层上植球或者涂覆绝缘层。
6.如权利要求4所述的扇出晶圆级封装方法,其特征在于:将芯片与所述金属层连接的方式为正装或倒装。
7.如权利要求4所述的扇出晶圆级封装方法,其特征在于,所述载板材料为玻璃、氧化铝、单晶硅、氮化铝、氧化铍、碳化硅、蓝宝石中的一种。
8.如权利要求4所述的扇出晶圆级封装方法,其特征在于:所述可剥离保护膜为UV膜、PET膜、PE膜、OPP膜、聚乙烯醇膜中的一种;所述塑封材料为硅树脂、环氧树脂、聚酰亚胺、酚醛树脂、聚氨酯、丙烯酸树脂中的一种;所述的介质保护层为油墨、SiO2薄膜、UV膜、PET膜、聚酯膜、PP膜、PE膜中的一种。
9.如权利要求4所述的扇出晶圆级封装方法,其特征在于:所述芯片安装为正装或倒装;在芯片安装步骤中,通过CCD影像对位装置检测芯片的偏移情况,通过金属针管吸取多余的阻焊剂;通过芯片卡爪纠正芯片的偏移。
10.如权利要求9所述的扇出晶圆级封装方法,其特征在于:所述芯片卡爪具有四个方向爪指,根据CCD影像对位装置的监控结果对芯片进行微移,使其位于准确的位置。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106158792A (zh) * 2015-01-27 2016-11-23 日月光半导体制造股份有限公司 半导体封装及其制造方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9570406B2 (en) 2015-06-01 2017-02-14 Qorvo Us, Inc. Wafer level fan-out with electromagnetic shielding
CN105140211A (zh) * 2015-07-14 2015-12-09 华进半导体封装先导技术研发中心有限公司 一种fan-out的封装结构及其封装方法
US10236245B2 (en) * 2016-03-23 2019-03-19 Dyi-chung Hu Package substrate with embedded circuit
CN107887324B (zh) * 2016-09-30 2019-09-13 上海微电子装备(集团)股份有限公司 一种半导体重布线方法
CN106409698A (zh) * 2016-11-11 2017-02-15 上海伊诺尔信息技术有限公司 智能卡模块的制造方法、智能卡模块及智能卡和条带
CN107240556A (zh) * 2017-07-28 2017-10-10 中芯长电半导体(江阴)有限公司 人脸识别芯片的封装结构及封装方法
CN107705976B (zh) * 2017-08-30 2020-08-25 潍坊歌尔微电子有限公司 一种线圈的制造方法、线圈、电子设备
CN109729241B (zh) * 2017-10-27 2020-10-02 宁波舜宇光电信息有限公司 摄像模组及其扩展布线封装感光组件和其制作方法
CN108598254A (zh) * 2018-04-19 2018-09-28 嘉盛半导体(苏州)有限公司 滤波器封装方法及封装结构
CN111863635A (zh) * 2019-04-28 2020-10-30 无锡华润安盛科技有限公司 半导体封装方法
CN113097080B (zh) * 2021-03-23 2024-05-07 合肥芯碁微电子装备股份有限公司 晶圆级芯片扇出封装方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6872661B1 (en) * 1998-06-10 2005-03-29 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation and die attach pad array
CN101488463A (zh) * 2008-01-17 2009-07-22 阿克泰克萨特株式会社 半导体封装用基板的制造方法及利用它来制造的金属镀层
US7939935B2 (en) * 2006-05-22 2011-05-10 Hitachi Cable Ltd. Electronic device substrate, electronic device and methods for fabricating the same
CN103094241A (zh) * 2012-12-15 2013-05-08 华天科技(西安)有限公司 一种引线框架再布线的fcaaqfn封装件及其制作工艺

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4421972B2 (ja) * 2004-04-30 2010-02-24 日東電工株式会社 半導体装置の製法
US8525305B1 (en) * 2010-06-29 2013-09-03 Eoplex Limited Lead carrier with print-formed package components
JP5048815B2 (ja) * 2010-07-20 2012-10-17 日東電工株式会社 フリップチップ型半導体裏面用フィルム、及び、ダイシングテープ一体型半導体裏面用フィルム
CN102169840A (zh) * 2011-01-30 2011-08-31 南通富士通微电子股份有限公司 系统级扇出晶圆封装方法
US9324641B2 (en) * 2012-03-20 2016-04-26 Stats Chippac Ltd. Integrated circuit packaging system with external interconnect and method of manufacture thereof
JP2014022582A (ja) * 2012-07-19 2014-02-03 Hitachi Maxell Ltd 半導体装置の製造方法、及び半導体装置
US9355997B2 (en) * 2014-03-12 2016-05-31 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US20160005679A1 (en) * 2014-07-02 2016-01-07 Nxp B.V. Exposed die quad flat no-leads (qfn) package
JP2016533651A (ja) * 2014-09-18 2016-10-27 インテル コーポレイション WLCSPコンポーネントをe−WLB及びe−PLB内に埋設する方法
US9379087B2 (en) * 2014-11-07 2016-06-28 Texas Instruments Incorporated Method of making a QFN package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6872661B1 (en) * 1998-06-10 2005-03-29 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation and die attach pad array
US7939935B2 (en) * 2006-05-22 2011-05-10 Hitachi Cable Ltd. Electronic device substrate, electronic device and methods for fabricating the same
CN101488463A (zh) * 2008-01-17 2009-07-22 阿克泰克萨特株式会社 半导体封装用基板的制造方法及利用它来制造的金属镀层
CN103094241A (zh) * 2012-12-15 2013-05-08 华天科技(西安)有限公司 一种引线框架再布线的fcaaqfn封装件及其制作工艺

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106158792A (zh) * 2015-01-27 2016-11-23 日月光半导体制造股份有限公司 半导体封装及其制造方法

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