JP2017526168A - バッチパッケージング低ピンカウント埋め込み半導体チップの構造及び方法 - Google Patents
バッチパッケージング低ピンカウント埋め込み半導体チップの構造及び方法 Download PDFInfo
- Publication number
- JP2017526168A JP2017526168A JP2017500019A JP2017500019A JP2017526168A JP 2017526168 A JP2017526168 A JP 2017526168A JP 2017500019 A JP2017500019 A JP 2017500019A JP 2017500019 A JP2017500019 A JP 2017500019A JP 2017526168 A JP2017526168 A JP 2017526168A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- metal
- bumps
- insulating material
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004806 packaging method and process Methods 0.000 title description 3
- 239000010410 layer Substances 0.000 claims abstract description 63
- 229910052751 metal Inorganic materials 0.000 claims abstract description 51
- 239000002184 metal Substances 0.000 claims abstract description 51
- 239000011810 insulating material Substances 0.000 claims abstract description 17
- 238000004544 sputter deposition Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000003475 lamination Methods 0.000 claims abstract description 11
- 239000000853 adhesive Substances 0.000 claims abstract description 10
- 230000001070 adhesive effect Effects 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 10
- 239000012790 adhesive layer Substances 0.000 claims abstract description 6
- 238000004519 manufacturing process Methods 0.000 claims abstract description 5
- 238000010030 laminating Methods 0.000 claims abstract description 4
- 238000004140 cleaning Methods 0.000 claims abstract description 3
- 238000000059 patterning Methods 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 239000011651 chromium Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 229910052726 zirconium Inorganic materials 0.000 claims description 3
- 239000003365 glass fiber Substances 0.000 claims description 2
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 238000007747 plating Methods 0.000 claims 2
- 238000001816 cooling Methods 0.000 claims 1
- 238000005272 metallurgy Methods 0.000 claims 1
- 239000002344 surface layer Substances 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 5
- 239000000945 filler Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229920000106 Liquid crystal polymer Polymers 0.000 description 1
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000003044 adaptive effect Effects 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002648 laminated material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/033—Manufacturing methods by local deposition of the material of the bonding area
- H01L2224/0333—Manufacturing methods by local deposition of the material of the bonding area in solid form
- H01L2224/03334—Manufacturing methods by local deposition of the material of the bonding area in solid form using a preform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1181—Cleaning, e.g. oxide removal step, desmearing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1182—Applying permanent coating, e.g. in-situ coating
- H01L2224/11825—Plating, e.g. electroplating, electroless plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1182—Applying permanent coating, e.g. in-situ coating
- H01L2224/11826—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13599—Material
- H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13639—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13599—Material
- H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13599—Material
- H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13599—Material
- H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/13666—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13599—Material
- H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/1367—Zirconium [Zr] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13599—Material
- H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/13671—Chromium [Cr] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13599—Material
- H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/1368—Molybdenum [Mo] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13599—Material
- H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/13681—Tantalum [Ta] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13599—Material
- H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/13684—Tungsten [W] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8389—Bonding techniques using an inorganic non metallic glass type adhesive, e.g. solder glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Dicing (AREA)
Abstract
Description
Claims (9)
- パネルフォーマットのパッケージングされた半導体デバイスを製造する方法であって、
平坦なパネルシートをキャリアとして提供することであって、前記平坦なパネルシートが、パネル平坦性を保つために適切な絶縁性プレートの堅い基板と、高温で解放可能な第1の接着剤の表面層、コアベースフィルム、及び第2の接着剤を備えた底部層を有するテープとを含み、前記底部層が前記基板に取り付けられ、前記パネルが隣接する半導体チップのセットに適した横方向寸法を有する、前記提供すること、
前記第1の接着剤の層上に隣接する半導体チップのセットを取り付けることであって、半導体チップの前記セットが、側壁を備えた矩形を形成し、前記半導体チップの端子が、前記第1の接着剤の層から離れて面する金属バンプを有する、前記取り付けること、
前記半導体チップ端子のバンプを密着して覆うため及び前記金属バンプ間のギャップを充填するため、及び前記矩形の側壁を囲む絶縁フレームを形成するため、真空吸引下で、適合(compliant)絶縁性材料をラミネートすることであって、前記絶縁性材料が前記半導体チップの熱膨張係数に近い熱膨張係数を有する、前記ラミネートすること、
前記金属バンプの頂部が露出されるまで、ラミネーション材料を均一にグラインドすること、
金属をスパッタリングするための機器において前記パネル及び取り付けられたチップセットをプラズマ洗浄及び冷却すること、及び
均一なエネルギー及びレートで、金属の少なくとも一つの層を、露出されたラミネーション及び端子バンプ上にスパッタリングすることであって、前記少なくとも一つの層が前記表面に接着する、前記スパッタリングすること、
を含む、方法。 - 請求項1に記載の方法であって、前記スパッタリングすることが、チタン、タングステン、タンタル、ジルコニウム、クロム、モリブデン、及びそれらの合金を含む群から選択される金属の第1の層をスパッタリングすること、及び遅延なしに、前記第1の層上に、銅、銀、金、及びそれらの合金を含む群から選択される金属の少なくとも一つの第2の層をスパッタリングすることを含み、前記第1の層が、チップ及びラミネーション表面に接着し、前記第2の層が前記第1の層に接着する、方法。
- 請求項2に記載の方法であって、
前記第2の金属の或る層を、前記第2の金属の前記スパッタリングされた層上にめっきパターニングすること、
はんだ付け可能な金属の層を、前記めっきされた第2の金属の選択されたエリア上にめっきすること、
前記スパッタリングされた金属層の選択されたエリアを剥がすこと、
前記めっきされた第2の金属の選択されたエリアの上に絶縁性材料を堆積及びパターニングすること、
前記第1の接着剤を解放するために温度を上げることにより前記パネルを取り除くこと、及び
個別のデバイスをシンギュレートするためにチップの前記セットをダイシングすること、
を更に含む、方法。 - パッケージングされた半導体デバイスであって、
金属バンプを含む端子を備えた第1の表面、及び平行な第2の表面を有する半導体チップ、
前記半導体チップの少なくとも一つの側壁に接着する絶縁性材料のフレームであって、前記金属バンプ間の前記絶縁性材料に平坦な第1の表面と、前記半導体チップの前記第2の表面に平坦な、平行な第2の表面とを有する、前記フレーム、及び
前記金属バンプから絶縁性材料の層の表面にわたって前記絶縁フレームの端部まで延在する、スパッタリングされた金属の少なくとも一つのフィルムであって、前記フィルムが、前記フレームの上の拡張されたコンタクトパッド、及び前記半導体チップのバンプと前記拡張されたコンタクトパッドとの間の再配路トレースを形成するようにパターニングされ、前記フィルムが前記表面に接着する、前記フィルム、
を含む、デバイス。 - 請求項4に記載のデバイスであって、前記スパッタリングされたフィルムが、チタン、タングステン、タンタル、ジルコニウム、クロム、モリブデン、及びそれらの合金を含む群から選択される金属の第1の層、及び、前記第1の層上の、銅、銀、金、及びそれらの合金から選択される群を含む金属の少なくとも一つの第2の層を含み、前記第1の層が、前記半導体チップ端子、重合体の表面、及びフレーム表面に接着し、前記第2の層が前記第1の層に接着する、デバイス。
- 請求項5に記載のデバイスであって、更に、前記スパッタリングされた金属に接着するめっきされる金属の少なくとも一つの層を含む、デバイス。
- 請求項6に記載のデバイスであって、更に、絶縁性材料の前記層及び再配路トレースの露出された部分を保護する、パターニングされたリジッド(rigid)材料を含む、デバイス。
- 請求項6に記載のデバイスであって、前記フレームの前記絶縁性材料が、高弾性及びシリコンの熱膨張係数(CTE)に近いCTEを有する膠状性(gluey)樹脂が浸透されたグラスファイバーを含む、デバイス。
- 請求項4に記載のデバイスであって、前記拡張されたコンタクトパッドの構成及び冶金が、ランドグリッドアレイデバイス、ボールグリッドアレイデバイス、及びクワッドフラットノーリード(QFN)デバイスを含むデバイスに適切であるように選択される、デバイス。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/320,825 US20160005705A1 (en) | 2014-07-01 | 2014-07-01 | Structure and Method of Batch-Packaging Low Pin Count Embedded Semiconductor Chips |
US14/320,825 | 2014-07-01 | ||
PCT/US2015/038880 WO2016004238A1 (en) | 2014-07-01 | 2015-07-01 | Structure and method of batch-packaging low pin count embedded semiconductor chips |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2017526168A true JP2017526168A (ja) | 2017-09-07 |
JP6796054B2 JP6796054B2 (ja) | 2020-12-02 |
Family
ID=55017543
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017500019A Active JP6796054B2 (ja) | 2014-07-01 | 2015-07-01 | バッチパッケージング低ピンカウント埋め込み半導体チップの構造及び方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20160005705A1 (ja) |
EP (1) | EP3164887B1 (ja) |
JP (1) | JP6796054B2 (ja) |
CN (1) | CN106663672A (ja) |
WO (1) | WO2016004238A1 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109002806A (zh) * | 2018-07-27 | 2018-12-14 | 星科金朋半导体(江阴)有限公司 | 一种qfn产品的后道封装方法 |
US11183460B2 (en) | 2018-09-17 | 2021-11-23 | Texas Instruments Incorporated | Embedded die packaging with integrated ceramic substrate |
US11031332B2 (en) | 2019-01-31 | 2021-06-08 | Texas Instruments Incorporated | Package panel processing with integrated ceramic isolation |
CN112582287A (zh) * | 2019-09-30 | 2021-03-30 | 中芯长电半导体(江阴)有限公司 | 晶圆级芯片封装结构及封装方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4463059A (en) * | 1982-06-30 | 1984-07-31 | International Business Machines Corporation | Layered metal film structures for LSI chip carriers adapted for solder bonding and wire bonding |
JP2000299406A (ja) * | 1999-04-15 | 2000-10-24 | Sanyo Electric Co Ltd | 半導体装置 |
JP2001144217A (ja) * | 1999-11-17 | 2001-05-25 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
US20020055255A1 (en) * | 2000-11-08 | 2002-05-09 | Yoshie Noguchi | Electrode forming method and bump electrode formable base used therefor |
US20110037165A1 (en) * | 2009-08-14 | 2011-02-17 | Stats Chippac, Ltd. | Semiconductor Device and Method of Mounting Semiconductor Die to Heat Spreader on Temporary Carrier and Forming Polymer Layer and Conductive Layer Over the Die |
US20110291249A1 (en) * | 2010-05-26 | 2011-12-01 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Conductive Posts and Heat Sink Over Semiconductor Die Using Leadframe |
WO2014071312A1 (en) * | 2012-11-05 | 2014-05-08 | Deca Technologies Inc. | Semiconductor device and method of adaptive patterning for panelized packaging |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6717245B1 (en) * | 2000-06-02 | 2004-04-06 | Micron Technology, Inc. | Chip scale packages performed by wafer level processing |
US20080023821A1 (en) * | 2005-07-20 | 2008-01-31 | Shih-Ping Hsu | Substrate structure integrated with passive components |
US7399658B2 (en) * | 2005-10-21 | 2008-07-15 | Stats Chippac Ltd. | Pre-molded leadframe and method therefor |
EP2184776A1 (en) * | 2008-11-05 | 2010-05-12 | General Electric Company | Method for making an interconnect structure and low-temperature interconnect component recovery process |
US9064936B2 (en) * | 2008-12-12 | 2015-06-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP |
CN101958389A (zh) * | 2010-07-30 | 2011-01-26 | 晶科电子(广州)有限公司 | 一种硅基板集成有功能电路的led表面贴装结构及其封装方法 |
US8193610B2 (en) * | 2010-08-10 | 2012-06-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming B-stage conductive polymer over contact pads of semiconductor die in Fo-WLCSP |
US8343810B2 (en) * | 2010-08-16 | 2013-01-01 | Stats Chippac, Ltd. | Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers |
US8409917B2 (en) * | 2011-03-22 | 2013-04-02 | Stats Chippac Ltd. | Integrated circuit packaging system with an interposer substrate and method of manufacture thereof |
US9484259B2 (en) * | 2011-09-21 | 2016-11-01 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming protection and support structure for conductive interconnect structure |
US20130244377A1 (en) * | 2012-03-13 | 2013-09-19 | Nitto Denko Corporation | Heat-resistant pressure-sensitive adhesive tape for production of semiconductor device and method for producing semiconductor device using the tape |
-
2014
- 2014-07-01 US US14/320,825 patent/US20160005705A1/en not_active Abandoned
-
2015
- 2015-07-01 JP JP2017500019A patent/JP6796054B2/ja active Active
- 2015-07-01 EP EP15815539.0A patent/EP3164887B1/en active Active
- 2015-07-01 WO PCT/US2015/038880 patent/WO2016004238A1/en active Application Filing
- 2015-07-01 CN CN201580043083.5A patent/CN106663672A/zh active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4463059A (en) * | 1982-06-30 | 1984-07-31 | International Business Machines Corporation | Layered metal film structures for LSI chip carriers adapted for solder bonding and wire bonding |
JP2000299406A (ja) * | 1999-04-15 | 2000-10-24 | Sanyo Electric Co Ltd | 半導体装置 |
JP2001144217A (ja) * | 1999-11-17 | 2001-05-25 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
US20020055255A1 (en) * | 2000-11-08 | 2002-05-09 | Yoshie Noguchi | Electrode forming method and bump electrode formable base used therefor |
US20110037165A1 (en) * | 2009-08-14 | 2011-02-17 | Stats Chippac, Ltd. | Semiconductor Device and Method of Mounting Semiconductor Die to Heat Spreader on Temporary Carrier and Forming Polymer Layer and Conductive Layer Over the Die |
US20110291249A1 (en) * | 2010-05-26 | 2011-12-01 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Conductive Posts and Heat Sink Over Semiconductor Die Using Leadframe |
WO2014071312A1 (en) * | 2012-11-05 | 2014-05-08 | Deca Technologies Inc. | Semiconductor device and method of adaptive patterning for panelized packaging |
Also Published As
Publication number | Publication date |
---|---|
US20160005705A1 (en) | 2016-01-07 |
JP6796054B2 (ja) | 2020-12-02 |
EP3164887A1 (en) | 2017-05-10 |
EP3164887A4 (en) | 2018-03-07 |
EP3164887B1 (en) | 2020-12-02 |
CN106663672A (zh) | 2017-05-10 |
WO2016004238A1 (en) | 2016-01-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20240266321A1 (en) | Semiconductor device and manufacturing method thereof | |
TWI772672B (zh) | 晶片封裝方法及晶片結構 | |
US20150008566A1 (en) | Method and structure of panelized packaging of semiconductor devices | |
TWI780101B (zh) | 半導體裝置及其製造方法 | |
US7772691B2 (en) | Thermally enhanced wafer level package | |
US9929072B2 (en) | Packaged semiconductor devices | |
US20180151461A1 (en) | Stiffener for fan-out wafer level packaging and method of manufacturing | |
US9287233B2 (en) | Adhesive pattern for advance package reliability improvement | |
US20090152707A1 (en) | Methods and systems for packaging integrated circuits | |
TW201642360A (zh) | 扇出系統級封裝及用於形成其之方法 | |
JP2006287235A (ja) | 積層されたダイのパッケージ | |
US20090115037A1 (en) | Integrated circuit package with integrated heat sink | |
US11233028B2 (en) | Chip packaging method and chip structure | |
JP6796054B2 (ja) | バッチパッケージング低ピンカウント埋め込み半導体チップの構造及び方法 | |
JP2010147096A (ja) | 半導体装置及び半導体装置の製造方法 | |
TW201009967A (en) | Methods and systems for packaging integrated circuits with integrated passive components | |
US11721654B2 (en) | Ultra-thin multichip power devices | |
US20110134612A1 (en) | Rebuilt wafer assembly | |
KR101134706B1 (ko) | 리드 프레임 및 이의 제조 방법 | |
US10242962B1 (en) | Back side metallization | |
JP5200130B2 (ja) | ウエハレベルcspの製造方法 | |
WO2019160567A1 (en) | System and method of fabricating glass frame fan out packaging | |
JP2009027127A (ja) | 大型パネルサイズ採用による半導体パッケージ製造方法 | |
JP2010118679A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20170105 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20180629 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20181219 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20190319 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20190517 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20190520 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20190710 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20191110 Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20191111 |
|
C60 | Trial request (containing other claim documents, opposition documents) |
Free format text: JAPANESE INTERMEDIATE CODE: C60 Effective date: 20191110 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20191118 |
|
C21 | Notice of transfer of a case for reconsideration by examiners before appeal proceedings |
Free format text: JAPANESE INTERMEDIATE CODE: C21 Effective date: 20191120 |
|
A912 | Re-examination (zenchi) completed and case transferred to appeal board |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20191206 |
|
C211 | Notice of termination of reconsideration by examiners before appeal proceedings |
Free format text: JAPANESE INTERMEDIATE CODE: C211 Effective date: 20191210 |
|
C22 | Notice of designation (change) of administrative judge |
Free format text: JAPANESE INTERMEDIATE CODE: C22 Effective date: 20200527 |
|
C13 | Notice of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: C13 Effective date: 20200902 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20200903 |
|
C126 | Written invitation by the chief administrative judge to file intermediate amendments |
Free format text: JAPANESE INTERMEDIATE CODE: C126 Effective date: 20200916 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20200917 |
|
C302 | Record of communication |
Free format text: JAPANESE INTERMEDIATE CODE: C302 Effective date: 20200929 |
|
C23 | Notice of termination of proceedings |
Free format text: JAPANESE INTERMEDIATE CODE: C23 Effective date: 20201007 |
|
C03 | Trial/appeal decision taken |
Free format text: JAPANESE INTERMEDIATE CODE: C03 Effective date: 20201111 |
|
C30A | Notification sent |
Free format text: JAPANESE INTERMEDIATE CODE: C3012 Effective date: 20201111 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20201113 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6796054 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313117 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313117 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313117 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |