CN106663672A - 批量封装低引脚计数嵌入式半导体芯片的结构及方法 - Google Patents

批量封装低引脚计数嵌入式半导体芯片的结构及方法 Download PDF

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CN106663672A
CN106663672A CN201580043083.5A CN201580043083A CN106663672A CN 106663672 A CN106663672 A CN 106663672A CN 201580043083 A CN201580043083 A CN 201580043083A CN 106663672 A CN106663672 A CN 106663672A
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layer
metal
chip
group
panel
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升本睦
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

在一种制作呈面板格式的封装式半导体装置的方法中，针对一组连续芯片将作为载体(100)的平整面板薄片定尺寸且所述平整面板薄片包含：绝缘板的坚硬衬底(101)；及胶带(102)，其具有在升高温度下可释放的第一粘合剂的表面层(110)、核心基底膜(111)及具有第二粘合剂的底部层(112)，所述底部层附接到所述衬底(101)。所述方法包含将一组附接到所述第一粘合剂层上，芯片端子具有拥有背对所述第一粘合剂层的金属凸块的端子。并且，所述方法包含：层压柔软绝缘材料以填充所述凸块之间的间隙并形成环绕所述组的绝缘框架、研磨层压材料以暴露所述凸块、等离子清洗及溅镀至少一个金属层。

Description

批量封装低引脚计数嵌入式半导体芯片的结构及方法
技术领域
此一般来说涉及半导体装置及过程，且更特定来说涉及批量封装的低引脚计数嵌入式半导体芯片的结构及制作方法。
背景技术
将半导体装置的有源及无源组件制造到从半导体元件或组件的细长圆柱形单晶体切割的圆形晶片中是惯例。这些固态晶片的直径可高达12英寸。接着通常通过沿x方向及y方向穿过晶片锯切割道以从晶片形成矩形形状的离散件而使个别装置从圆形晶片单化。通常，这些件被称为裸片或芯片。每一芯片包含与相应金属接触垫耦合的至少一个装置。半导体装置包含许多大的电子组件系列。实例为有源装置(例如，二极管及如场效应晶体管的晶体管)、无源装置(例如电阻器及电容器)及有时具有远多于一百万有源及无源组件的集成电路。
在单化之后，一或多个芯片附接到离散支撑衬底，例如金属引线框架或由多个金属层及绝缘层层压的刚性多层级衬底。引线框架及衬底的导电迹线接着通常使用接合导线或金属凸块(例如焊料球)而连接到芯片接触垫。为保护免受环境及处置风险，经装配芯片可囊封于离散坚固封装中，所述离散坚固封装通常采用硬化的聚合化合物且通过例如转移模制等技术形成。装配及封装过程通常在个别基础上或以小的分组(例如引线框架的剥离或模具压机的装载)执行。
为以大突破增加生产率且减少制作成本，最近已开始进行技术努力来增加由每一批量过程步骤处置的体积。这些努力大体在标题面板化(panelization)下概述。作为实例，描述用于制作基于面板的封装结构的自适应图案化方法。其它技术努力针对于防止新兴问题，例如控制下的面板翘曲。
发明内容
在用以使一组完整芯片将芯片嵌入于封装中的过程流程中，方法使用粘合胶带而非环氧芯片附接程序、可重新使用载体，且使用溅镀方法来替换无电极电镀。此外，新过程技术不需要使用激光。因此，新过程流程保留清洁的芯片接触垫且同时处理一组四个芯片，因此大大增加生产率。并且，封装式装置提供经改进可靠性。对增强的可靠性的关键贡献为通过用绝缘填充物层压间隙而实现的减小的热机械应力，所述绝缘填充物具有高模数及针对接近硅的热膨胀系数的系数的玻璃转变温度。
在具有经等离子清洗且经冷却面板的溅镀技术中，跨越面板产生均匀经溅镀金属层，其而因此避免对无电极电镀的需要。由于溅镀程序还用于清洗衬底表面并使衬底表面粗糙化，因此经溅镀层同样好地粘附到电介质、硅及金属。经溅镀层可用作连接迹线或可充当籽晶层以用于后续经电镀金属层。
基于经修改过程的一个实施例可应用于具有小数目个端子的一组连续芯片。另一实施例适用于多组半导体芯片。许多经修改流程可适用于任何晶体管或集成电路。其它经修改流程尤其适用于较高数目个端子。一些封装式装置提供关于连接到外部部件的灵活性。所述封装式装置可经完成以适合用作具有平台栅格阵列的装置或用作球形栅格阵列或用作及QFN(四方平整无引线)端子。
附图说明
图1展示具有如由所描述实例所使用的三层级粘合胶带的可重新使用载体的横截面。
图2A是图1的载体的横截面，所述图图解说明将一组芯片附接到载体的顶部粘合层上的过程。
图2B是组合件的俯视图，所述图图解说明将一组四个芯片附接到载体的顶部粘合层上的过程。
图3展示组合件的横截面，所述图图解说明将聚合填充物材料层压于组合件上方的过程。
图4A是组合件的横截面，所述图图解说明研磨填充物材料以暴露凸起芯片端子的过程。
图4B是组合件的俯视图，所述图图解说明在研磨填充物材料之后的所暴露凸起芯片端子。
图5A是组合件的横截面，所述图概述沉积并图案化至少一个金属层以形成经延伸接触垫及垫与芯片端子之间的重新布线连接的过程。
图5B显示形成经延伸接触垫及介于垫与芯片端子之间的经重新布线连接的经沉积且经图案化至少一个金属层的俯视图。
图6A展示组合件的横截面，所述图描绘沉积并图案化保护绝缘体层的过程。
图6B是组合件的俯视图，所述图图解说明由具有用于经耗尽接触垫的开口的保护层覆盖的组合件表面。
图7A图解说明在将载体分离之后使离散装置从经封装组单化的过程。
图7B展示从组单化的经单化的封装式装置的俯视图。
具体实施方式
通过用于从既定用于半导体封装的若干组较少连续芯片到若干组较大数目的连续芯片的大规模面板的成功方法及过程流程来解析关键技术挑战。这些挑战包含：实现面板的平坦性且避免翘曲及机械不稳定性、使接触垫的间距延伸以用于容易地连接到外部部件，实现低电路连接且实现高可靠性背侧芯片连接件、避免尤其通过金属层及环氧层的昂贵激光过程步骤，以及经改进热特性。对于金属籽晶层，应实现跨越选定面板大小的层的均匀性，然而应避免无电极电镀技术。
至少一个实施例包含制作呈面板格式的封装式半导体装置的方法，所述方法的一些过程图解说明于图1到7B中。方法在图1中通过选择平整面板薄片作为刚性载体(通常指示为100)而开始。载体100包含坚硬衬底101及胶带102。衬底101为适合于维持面板平整度的绝缘板。举例来说，衬底101可由玻璃或另一坚硬无机或有机材料制成。胶带102优选地包含3层胶粘性箔，所述3层胶粘性箔包含具有在升高温度下可释放的第一粘合剂的表面层110、核心基底膜111及具有第二粘合剂的底部层112。底部层112附接到衬底101。载体100的组成确保载体不会成为最终封装式装置的永久部分。替代地，载体100可被赋予允许面板并入于最终装置封装中的组成。面板100具有适合于一组连续半导体芯片的横向尺寸。在图2A及2B的实例性实施例中，面板100具有大于布置为单元的四个连续半导体集成电路芯片(例如，制作于单晶硅中且尚未经单化的四个芯片)的横向尺寸。
将一组四个半导体芯片作为单批处理的能力会使所涉及过程步骤的生产率增强四倍。
图2A及2B展示将一组四个连续半导体芯片附接到载体100的电介质胶带102的第一粘合层110的过程步骤。图2B图解说明布置为大的大小的方形以利用将接触垫重新设计成对称几何形状的所述组四个方形形状的芯片。更一般来说，芯片组与侧壁一起形成矩形。替代地，其它不对称重新布置为可能的。在任一情形中，与常规芯片附接(一次附接一个芯片)中所需要的多个步骤相比，附接过程由单个步骤组成，从而展现生产率的显著增加。
实例性实施例的图2A及2B图解说明每一芯片具有位于芯片表面上的八个端子；所述端子优选地以有序甚至对称布置对准。此外，所述图展示端子具有金属凸块210。芯片可具有约150μm的厚度，且优选凸块包含圆形或方形铜柱以及压扁铜球(如通过导线接合技术而形成)。个别芯片的凸块210彼此间隔开间隙211。所述组的所附接芯片经定向，使得芯片端子垫的金属凸块210背对面板表面。
在图3的过程步骤中，在真空吸力下层压柔软绝缘材料330以粘着地填充芯片凸块之间的任何间隙211并覆盖芯片201及凸块210的表面。优选地，凸块顶部上方的经层压材料的高度330a介于约15μm与50μm之间。同样，绝缘材料形成环绕矩形侧壁的框架330b。所述框架的宽度331包含用于提供可用于支撑后续过程步骤中的经重新布线接触垫的区域所需要的部分。柔软材料经选择以具有高模数及接近半导体芯片的CTE的低CTE；其可为玻璃填充的且可包含液晶聚合物。
在图4A及4B中所描绘的下一过程步骤中，使用研磨技术来均匀地研磨绝缘层压材料330，直到暴露金属凸块210的顶部为止。研磨过程可通过移除一些凸块高度直到凸块210与层压材料330的平坦表面平整为止而继续；优选地，剩余凸块高度210a介于约25μm与50μm之间。此后，载体100与其组合件一起被转移到设备的真空及等离子室以用于溅镀金属。
在图5A及5B中所概述的过程期间，具有所暴露金属凸块及层压表面的载体100的组合件在面板被冷却时(优选地低于环境温度)进行等离子清洗。除清洗来自所吸附膜(尤其水单层)的表面以外，等离子还完成表面的一定粗糙化；两种效应均增强经溅镀金属层的粘附。接着，至少一个金属层540以均匀能量及速率跨越载体而溅镀到所暴露凸块及层压表面上。经溅镀层粘附到表面。
优选地，溅镀步骤包含：溅镀第一金属层，所述金属选自包含以下各项的群组：钛、钨、钽、锆、铬、钼及其合金，其中所述第一层粘附到芯片及层压表面；及毫不延迟地将至少一个第二金属层溅镀到第一层上，所述金属选自包含以下各项的群组：铜、银、金及其合金，其中所述第二层粘附到所述第一层。经溅镀层具有均匀性、强粘附性及用以在图案化之后充当用于重新布线的导电迹线所需要的低电阻率，参见图5A及5B；经溅镀层也可充当用于经镀覆较厚金属层的籽晶金属。
在任选步骤中，将至少一个金属层电镀到经溅镀层540上。优选金属为铜。经镀覆层优选地厚于经溅镀金属以降低薄片电阻，且因此降低在使经镀覆及经溅镀金属层图案化之后的重新布线迹线的电阻率。使经溅镀及经镀覆金属层图案化以形成凸块与加大封装接触垫之间的连接迹线的步骤优选地用激光直接成像技术执行。激光直接成像技术使用错位对准(out-alignment)校正技术。
在另一任选步骤中，可沉积一或多个可焊接金属(例如锡、锡合金、镍，后续接着钯)层。
图5B中图解说明用于重新布线及加大的接触垫的金属层图案化的结果。与原始凸块210及其间距211相比，新接触垫510得益于通过层压(由图3中的框架宽度331确定)及经定制重新布线而加大的面积。与原始凸块210相比，新接触垫510具有加大的接触直径510a；新接触垫510进一步具有更宽间距511及对称布局。同样，实现从垫到具有凸块的芯片端子的连接迹线520，其得益于经定制布局，但由于经溅镀及经镀覆金属层的高导电性，所述连接迹线仅具有可忽略的小的电阻及电感增加。
并且，如在图6A及6B中所展示，优选沉积并图案化刚性绝缘材料660(例如所谓的抗焊剂)以保护并加强未用于经延伸触点的剩余芯片区域；在刚性绝缘保护的优选应用中，仅经延伸接触区域610保持暴露且开放为窗口。接触区域可为圆形(如图7B中所展示)或方形的。为施加抗焊剂及其它电介质材料、可光成像材料、蚀刻剂及其它材料，优选技术使用超声波喷涂工具。在绝缘材料660的刚性保护下，完成针对芯片组的封装的装配。取决于接触区域610的配置，其可施加为球形栅格阵列、平台(land)栅格阵列及QFN型接触垫。
在下一过程步骤中，升高温度，使得层110的温度敏感第一粘合剂允许将面板110(衬底101及胶带102)从经封装芯片组的组合件移除。
图7A及7B中所图解说明的下一过程步骤，将经封装芯片组单化成离散装置700。优选分离技术为锯切。在单化之后，载体320的相应部件321与装置370的所完成封装保持在一起。针对图7A中所展示的实例性装置700，芯片组的单化形成单元，所述单元具有接触垫610、具有所暴露绝缘层压730的侧壁730c及具有所暴露硅701的侧壁701c。所暴露硅区域提供用于热散布的良好机会，且因此有助于改进热装置特性。
另一实施例为实例性封装式半导体装置700。所述装置具有半导体芯片701，所述半导体芯片具有第一表面701a及平行第二表面701b。第一表面701a具有多个端子710，所述多个端子具有金属凸块，例如铜柱或铜压扁球。
装置700具有绝缘材料框架730，所述绝缘材料框架粘附到芯片的至少一个侧壁。所述框架的绝缘材料包含浸渍有胶质树脂的玻璃纤维，所述胶质树脂具有高模数及接近于硅的热膨胀系数(CTE)的CTE。框架730具有与凸块710之间的绝缘材料成平面的第一表面730a，及与第二芯片表面701b成平面的平行第二表面730b。
装置700进一步具有经溅镀金属的至少一个膜740，所述膜从凸块710跨越绝缘材料层的表面730a而延伸到靠近于绝缘框架的边缘。膜740经图案化以在框架上方形成经延伸接触垫610，且在任何需要的地方重新布线芯片凸块710与经延伸接触垫610之间的迹线。由于膜740已通过溅镀形成，因此其粘附到所提及的所有表面。
取决于经延伸接触垫610的大小、轮廓及冶金配置，其可用作球形栅格阵列端子、平台栅格阵列端子及QFN型端子。
修改在所描述实施例中为可能的，且其它实施例在权利要求书的范围内为可能的。作为实例，取决于芯片及封装的大小，可针对与所讨论的八个接触垫相较相当更高数目个端子而利用足够面积来布局经重新分布接触垫。作为另一实例，针对一组四个芯片，芯片以及封装的配置可为矩形而非方形；可容纳经重新分布接触垫的布局。

Claims (9)

1.一种制作呈面板格式的封装式半导体装置的方法，其包括：
提供平整面板薄片作为载体，所述平整面板薄片包含：绝缘板的坚硬衬底，其适合于维持面板平整度；及胶带，其具有在升高温度下可释放的第一粘合剂的表面层、核心基底膜及具有第二粘合剂的底部层，所述底部层附接到所述衬底，所述面板具有适合于一组连续半导体芯片的横向尺寸；
将一组连续半导体芯片附接到所述第一粘合剂层上，所述组连续半导体芯片与侧壁形成矩形，芯片端子具有背对所述第一粘合剂层的金属凸块；
在真空吸力下层压柔软绝缘材料以粘着地覆盖所述芯片端子凸块并填充所述凸块之间的间隙且形成环绕所述矩形侧壁的绝缘框架，所述材料具有接近所述半导体芯片的热膨胀系数的热膨胀系数；
均匀地研磨层压材料，直到暴露所述金属凸块的顶部为止；
在设备中等离子清洗并冷却所述面板及所附接芯片组以用于溅镀金属；及
以均匀能量及速率将至少一个金属层溅镀到所暴露层压部及端子凸块上，所述层粘附到所述表面。
2.根据权利要求1所述的方法，其中溅镀包含：溅镀选自包含钛、钨、钽、锆、铬、钼及其合金的群组的金属的第一层，所述第一层粘附到芯片及层压表面；及毫不延迟地将选自包含铜、银、金及其合金的群组的金属的至少一个第二层溅镀到所述第一层上，所述第二层粘附到所述第一层。
3.根据权利要求2所述的方法，其进一步包括：
将一层第二金属镀覆到所述第二金属的所述经溅镀层上并图案化所述层第二金属；
将可焊接金属层镀覆到所述经镀覆第二金属的选定区域上；
剥离所述经溅镀金属层的选定区域；
在所述经镀覆第二金属的选定区域上方沉积并图案化绝缘材料；
通过升高温度以释放所述第一粘合剂而移除所述面板；及
切割所述组芯片以单化成若干离散装置。
4.一种封装式半导体装置，其包括：
半导体芯片，其具有第一表面及平行第二表面，所述第一表面具有包含金属凸块的端子；
绝缘材料框架，其粘附到所述芯片的至少一个侧壁，所述框架具有与所述凸块之间的所述绝缘材料成平面的第一表面及与所述第二芯片表面成平面的平行第二表面；及
至少一个经溅镀金属膜，其从所述凸块跨越绝缘材料层的表面而延伸到所述绝缘框架的边缘，所述膜经图案化以形成所述框架上方的经延伸接触垫及所述芯片凸块与所述经延伸接触垫之间的重新布线迹线，所述膜粘附到所述表面。
5.根据权利要求4所述的装置，其中所述经溅镀膜包含：选自包含钛、钨、钽、锆、铬、钼及其合金的群组的金属的第一层，所述第一层粘附到所述芯片端子、聚合物表面及框架表面；及在所述第一层上的选自包含铜、银、金及其合金的群组的金属的至少一个第二层，所述第二层粘附到所述第一层。
6.根据权利要求5所述的装置，其进一步包含至少一个经镀覆金属层，所述经镀覆金属层粘附到所述经溅镀金属。
7.根据权利要求6所述的装置，其进一步包含经图案化刚性材料，所述经图案化刚性材料保护所述绝缘材料层的所暴露部分及重新布线迹线。
8.根据权利要求6所述的装置，其中所述框架的所述绝缘材料包含浸渍有胶质树脂的玻璃纤维，所述胶质树脂具有高模数及接近于硅的热膨胀系数CTE的CTE。
9.根据权利要求4所述的装置，其中所述经延伸接触垫的配置及冶金经选择为适合于包含平台栅格阵列装置、球形栅格阵列装置及四方平整无引线QFN装置的装置。
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