JP2017017300A - チップパッケージ - Google Patents
チップパッケージ Download PDFInfo
- Publication number
- JP2017017300A JP2017017300A JP2015205229A JP2015205229A JP2017017300A JP 2017017300 A JP2017017300 A JP 2017017300A JP 2015205229 A JP2015205229 A JP 2015205229A JP 2015205229 A JP2015205229 A JP 2015205229A JP 2017017300 A JP2017017300 A JP 2017017300A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- dielectric
- die package
- chip
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003989 dielectric material Substances 0.000 claims abstract description 27
- 238000002161 passivation Methods 0.000 claims abstract description 12
- 239000010949 copper Substances 0.000 claims description 55
- 229910052802 copper Inorganic materials 0.000 claims description 54
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 43
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 32
- 229920002120 photoresistant polymer Polymers 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 29
- 229920000642 polymer Polymers 0.000 claims description 20
- 239000010931 gold Substances 0.000 claims description 16
- 229910052759 nickel Inorganic materials 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 230000004888 barrier function Effects 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 239000010936 titanium Substances 0.000 claims description 13
- 229910052719 titanium Inorganic materials 0.000 claims description 12
- 238000007747 plating Methods 0.000 claims description 11
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 9
- 239000011651 chromium Substances 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 9
- 229910052804 chromium Inorganic materials 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 7
- 239000003755 preservative agent Substances 0.000 claims description 7
- 230000002335 preservative effect Effects 0.000 claims description 7
- 229910000679 solder Inorganic materials 0.000 claims description 7
- 238000009713 electroplating Methods 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims description 5
- 229910052763 palladium Inorganic materials 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000010330 laser marking Methods 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 97
- 239000012790 adhesive layer Substances 0.000 abstract description 5
- 239000003365 glass fiber Substances 0.000 description 8
- 235000012431 wafers Nutrition 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- 239000004721 Polyphenylene oxide Substances 0.000 description 6
- 239000011159 matrix material Substances 0.000 description 6
- 229920001955 polyphenylene ether Polymers 0.000 description 6
- 229920006380 polyphenylene oxide Polymers 0.000 description 6
- 239000004642 Polyimide Substances 0.000 description 4
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 3
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229920003192 poly(bis maleimide) Polymers 0.000 description 3
- 229920006254 polymer film Polymers 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 229920002430 Fibre-reinforced plastic Polymers 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 239000011151 fibre-reinforced plastic Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000013021 overheating Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000011253 protective coating Substances 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000002845 discoloration Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000002952 polymeric resin Substances 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000002470 thermal conductor Substances 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26122—Auxiliary members for layer connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/26125—Reinforcing structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49586—Insulating layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/37—Effects of the manufacturing process
- H01L2924/37001—Yield
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemical & Material Sciences (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
【解決手段】パッシベーション層14に存在するダイ接触パッド18であって、接着層によってフィーチャ層の第1側に結合されるダイ接触パッドを有するチップ10、及びフィーチャ層の第2側から延伸するピラー12の層を含み、ダイ、フィーチャ層及びピラー12の層が、誘電材料16によって封入される埋め込みダイパッケージ。
【選択図】図1
Description
ポリマーフレームによって囲まれたソケットのグリッドを入手し;
チップソケットのグリッドをテープ上に載置し;
グリッドのソケット内に、下向きにチップ(フリップチップ)を載置し;
ダイ及びグリッド上に誘電材料を積層し;
誘電体上にキャリアを塗布し;
チタニウム、タンタル、タングステン、クロム及び/又はニッケルの少なくとも1つを含む接着/バリア層を堆積し、続いて新たに露出した表面上に銅のシード層を堆積し;
フォトレジストの第1層の層を塗布して、フィーチャ層でパターンを現像し;
フィーチャを形成するために、銅を、パターンに電気めっきし;
フォトレジストの第1層を剥離し;
ビアピラーのパターンでパターニングされたフォトレジストの第2層を塗布し;
ビアピラーを形成するために、銅をパターンに電気めっきし;
フォトレジストの第2層を剥離し;
接着層と銅シード層の露出部分をエッチング除去し;
銅フィーチャ、ピラー及び、チップの下側を被覆する誘電性バリア層を塗布し;
キャリアを除去し;
ダイのアレイ裏面上に薄層の黒色誘電体を積層し;
銅ピラーを露出するために、誘電体を薄くし、
終端部を塗布し;
グリッドを、個別の実装チップにダイシングする、方法に向けられる。
正方形又は長方形であること;
外面は、無電解ニッケル/無電解パラジウム/無電解金(ENEPIG)、無電解ニッケル/無電解金(ENIG)又は電解ニッケル−金(Ni/Au)終端技術を含む最終金属めっきが施されること;
任意には、周囲の誘電体から最大10ミクロン突出することを特徴とする。
周囲の誘電体に対して最大10ミクロン陥凹されること;
半田ボールを湿潤し易くするための円形端部を有する筒状であること;及び
有機半田付け性保存剤(Organic Solderability Preservative: OSP)でコーティングされること、の少なくとも1つを特徴とする。
6 フレーム
8、108 電子チップパッケージ
10、110 チップ
12、112 ピラー
14、114 パッシベーション層
16、26、116、126 誘電材料
18、118 パッド
20、22、24 ランドグリッドアレイ(LGA)
28、128 黒色誘電体
30 テープ
32 キャリア
34 接着層
36、38 フォトレジスト
120、122、124 ボールグリッドアレイ(BGA)
130 有機半田付け性保存剤
Claims (24)
- パッシベーション層に存在するダイ接触パッドであって、接着/バリア層によってフィーチャ層の第1側に結合されるダイ接触パッドを有するダイ、及び前記フィーチャ層の第2側から延伸するピラーの層を含み、前記ダイ、前記フィーチャ層及び前記ピラーの層が、誘電材料によって封入される埋め込みダイパッケージ。
- 前記ダイ接触パッドは、アルミニウムを含む、請求項1に記載の埋め込みダイパッケージ。
- 前記パッシベーション層は、PI又はSiNのどちらかを含む、請求項3に記載の埋め込みダイパッケージ。
- 前記接着/バリア層は、Ti/Cu、Ti/W/Cu、Ti/Ta/Cu、Cr/Cu及びNi/Crから成る群から選択される、請求項1に記載の埋め込みダイパッケージ。
- 前記接着/バリア層の厚さは、0.05ミクロン〜1ミクロンの範囲にある、請求項4に記載の埋め込みダイパッケージ。
- 前記フィーチャ層は、銅を含む、請求項1に記載の埋め込みダイパッケージ。
- 前記フィーチャ層の厚さは、1ミクロン〜25ミクロンの範囲にある、請求項6に記載の埋め込みダイパッケージ。
- 前記ピラーの層の高さは、15ミクロン〜50ミクロンの範囲にある、請求項6に記載の埋め込みダイパッケージ。
- 前記フィーチャ層は、ファンアウト形状を有する、請求項1に記載の埋め込みダイパッケージ。
- 前記フィーチャ層は、ファンイン形状を有する、請求項1に記載の埋め込みダイパッケージ。
- 前記チップと前記ピラーの層は、異なるポリマー誘電材料内に埋め込まれる、請求項1に記載の埋め込みダイパッケージ。
- 前記ピラーの層は、前記ダイを基板に結合させる接点として機能するパッドのグリッドアレイを含む、請求項1に記載の埋め込みダイパッケージ。
- 前記基板は、PCBである、請求項12に記載の埋め込みダイパッケージ。
- 前記基板は、Package on Package(PoP)を作製するためのパッケージである、請求項12に記載の埋め込みダイパッケージ。
- 前記パッドのグリッドアレイは、誘電体より最大10ミクロン延出する、又は前記誘電体と面一にして、それによりLGAパッドを提供する、請求項12に記載の埋め込みダイパッケージ。
- 前記パッドのグリッドアレイは、電解Ni/Au、ENIG又はENEIGから成る群から選択される終端部で終端される、請求項15に記載の埋め込みダイパッケージ。
- 前記パッドのグリッドアレイは、前記誘電体より最大10ミクロン陥凹される、又は前記誘電体と面一にして、それによりBGAパッドを提供する、請求項12に記載の埋め込みダイパッケージ。
- 前記パッドのグリッドアレイは、有機半田付け性保存剤(Organic Solderability Preservative: OSP)で終端される、請求項17に記載の埋め込みダイパッケージ。
- 本明細書に記載された新規なチップパッケージを作製する方法であって、
ポリマーフレームによって囲まれたソケットのグリッドを入手し;
前記チップソケットのグリッドをテープ上に載置し;
前記グリッドの前記ソケット内に、下向きにチップ(フリップチップ)を載置し;
前記ダイ及び前記グリッド上に誘電材料を積層し;
前記誘電体上にキャリアを塗布し;
チタニウム、タンタル、タングステン、クロム及び/又はニッケルの少なくとも1つを含む接着/バリア層を堆積し、続いて新たに露出した表面上に銅のシード層を堆積し;
フォトレジストの第1層の層を塗布して、フィーチャ層でパターンを現像し;
フィーチャを形成するために、銅を、前記パターンに電気めっきし;
前記フォトレジストの第1層を剥離し;
ビアピラーのパターンでパターニングされたフォトレジストの第2層を塗布し;
ビアピラーを形成するために、銅を前記パターンに電気めっきし;
前記フォトレジストの第2層を剥離し;
前記接着層と前記銅シード層の露出部分をエッチング除去し;
前記銅フィーチャ、ピラー及び、前記チップの下側を被覆する誘電性バリア層を塗布し;
キャリアを除去し;
前記ダイのアレイ裏面上に薄層の黒色誘電体を積層し;
前記銅ピラーを露出するために、前記誘電体を薄くし、
終端部を塗布し;
前記グリッドを、個別の実装チップにダイシングする、方法。 - 前記黒色誘電体をレーザマーキングする更なるステップが続く、請求項19に記載の方法。
- チップのアレイは、各ソケット内に配置される、請求項19に記載の方法。
- ウエハ上にチップのアレイを有するウエハは、各ソケット内に配置される、請求項19に記載の方法。
- 前記銅ピラーは、ランドグリッドアレイ(LGA)を含み、少なくとも1つの以下の制限:
正方形又は長方形とすること;
外面は、無電解ニッケル/無電解パラジウム/無電解金(ENEPIG)、無電解ニッケル/無電解金(ENIG)又は電解ニッケル−金(Ni/Au)終端技術を含む最終金属めっきが施されること;
任意には、周囲の誘電体から最大10ミクロン突出することを特徴とする、請求項19に記載の方法。 - 前記銅ピラーは、パッドのボールグリッドアレイ(BGA)を含み、
周囲の誘電体に対して最大10ミクロン陥凹されること;
半田ボールを湿潤し易くするための円形端部を有する筒状であること;及び
有機半田付け性保存剤(Organic Solderability Preservative: OSP)でコーティングされること、の少なくとも1つを特徴とする、請求項19に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/789,165 | 2015-07-01 | ||
US14/789,165 US9779940B2 (en) | 2015-07-01 | 2015-07-01 | Chip package |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2017017300A true JP2017017300A (ja) | 2017-01-19 |
JP6797521B2 JP6797521B2 (ja) | 2020-12-09 |
Family
ID=57683265
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015205229A Active JP6797521B2 (ja) | 2015-07-01 | 2015-10-19 | ダイパッケージ及びダイパッケージを作製する方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9779940B2 (ja) |
JP (1) | JP6797521B2 (ja) |
KR (2) | KR101713643B1 (ja) |
CN (1) | CN106328604B (ja) |
TW (1) | TWI715567B (ja) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108305864B (zh) * | 2017-01-12 | 2020-08-18 | 珠海越亚半导体股份有限公司 | 端子 |
JP6432639B2 (ja) * | 2017-04-28 | 2018-12-05 | 日亜化学工業株式会社 | 発光装置 |
TWI628756B (zh) * | 2017-08-22 | 2018-07-01 | 鳳凰先驅股份有限公司 | 封裝結構及其製作方法 |
CN207134353U (zh) * | 2017-08-31 | 2018-03-23 | 深圳市江波龙电子有限公司 | 移动终端及其芯片封装结构 |
US11610855B2 (en) * | 2017-11-29 | 2023-03-21 | Pep Innovation Pte. Ltd. | Chip packaging method and package structure |
JP7303294B2 (ja) * | 2018-10-30 | 2023-07-04 | 長江存儲科技有限責任公司 | Icパッケージ |
CN109257874A (zh) * | 2018-11-16 | 2019-01-22 | 深圳市和美精艺科技有限公司 | 一种在pcb板制作过程中芯片埋入的方法及其结构 |
CN109904079B (zh) * | 2019-01-30 | 2022-03-04 | 深圳市志金电子有限公司 | 封装基板制造工艺、封装基板以及芯片封装结构 |
KR102543996B1 (ko) | 2019-09-20 | 2023-06-16 | 주식회사 네패스 | 반도체 패키지 및 이의 제조방법 |
CN111564374A (zh) * | 2020-07-15 | 2020-08-21 | 珠海越亚半导体股份有限公司 | 封装基板制作方法 |
CN112103191B (zh) * | 2020-08-07 | 2022-01-11 | 珠海越亚半导体股份有限公司 | 芯片封装结构及其制作方法 |
CN116705633A (zh) * | 2023-07-25 | 2023-09-05 | 成都电科星拓科技有限公司 | 一种lga封装焊盘可焊性增强的实现方法及封装结构 |
CN118156161A (zh) * | 2024-03-11 | 2024-06-07 | 深圳市知音科技有限公司 | 一种芯片封装方法及芯片封装结构 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000188357A (ja) * | 1998-12-22 | 2000-07-04 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
JP2006147810A (ja) * | 2004-11-19 | 2006-06-08 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
JP2009123862A (ja) * | 2007-11-14 | 2009-06-04 | Spansion Llc | 半導体装置及びその製造方法 |
JP2014135346A (ja) * | 2013-01-09 | 2014-07-24 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2015508240A (ja) * | 2012-02-24 | 2015-03-16 | インヴェンサス・コーポレイション | 封止面へのワイヤボンドを有するパッケージオンパッケージアセンブリのための方法 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI236118B (en) | 2003-06-18 | 2005-07-11 | Advanced Semiconductor Eng | Package structure with a heat spreader and manufacturing method thereof |
US7459781B2 (en) * | 2003-12-03 | 2008-12-02 | Wen-Kun Yang | Fan out type wafer level package structure and method of the same |
WO2006068641A1 (en) * | 2004-12-20 | 2006-06-29 | Semiconductor Components Industries, L.L.C. | Electronic package having down-set leads and method |
JP5203108B2 (ja) * | 2008-09-12 | 2013-06-05 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
US7897433B2 (en) * | 2009-02-18 | 2011-03-01 | Advanced Micro Devices, Inc. | Semiconductor chip with reinforcement layer and method of making the same |
US8472190B2 (en) * | 2010-09-24 | 2013-06-25 | Ati Technologies Ulc | Stacked semiconductor chip device with thermal management |
US8552540B2 (en) * | 2011-05-10 | 2013-10-08 | Conexant Systems, Inc. | Wafer level package with thermal pad for higher power dissipation |
US9312214B2 (en) * | 2011-09-22 | 2016-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages having polymer-containing substrates and methods of forming same |
US8703542B2 (en) * | 2012-05-18 | 2014-04-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer-level packaging mechanisms |
US8981559B2 (en) * | 2012-06-25 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package devices and methods of packaging semiconductor dies |
US8952533B2 (en) * | 2012-09-10 | 2015-02-10 | Futurewei Technologies, Inc. | Devices and methods for 2.5D interposers |
US10269747B2 (en) * | 2012-10-25 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company | Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices |
JP2014096547A (ja) * | 2012-11-12 | 2014-05-22 | Ps4 Luxco S A R L | 半導体装置及びその製造方法 |
US9040349B2 (en) * | 2012-11-15 | 2015-05-26 | Amkor Technology, Inc. | Method and system for a semiconductor device package with a die to interposer wafer first bond |
US8866286B2 (en) * | 2012-12-13 | 2014-10-21 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. | Single layer coreless substrate |
KR101546572B1 (ko) * | 2013-07-16 | 2015-08-24 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 그 제조 방법 |
US9607933B2 (en) * | 2014-02-07 | 2017-03-28 | Dawning Leading Technology Inc. | Lead frame structure for quad flat no-lead package, quad flat no-lead package and method for forming the lead frame structure |
US9564387B2 (en) * | 2014-08-28 | 2017-02-07 | UTAC Headquarters Pte. Ltd. | Semiconductor package having routing traces therein |
US9589924B2 (en) * | 2014-08-28 | 2017-03-07 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and method of manufacturing the same |
US10109584B2 (en) * | 2014-09-02 | 2018-10-23 | Qualcomm Incorporated | Patterned grounds and methods of forming the same |
-
2015
- 2015-07-01 US US14/789,165 patent/US9779940B2/en active Active
- 2015-09-04 KR KR1020150125230A patent/KR101713643B1/ko active IP Right Grant
- 2015-10-19 JP JP2015205229A patent/JP6797521B2/ja active Active
-
2016
- 2016-03-29 CN CN201610191287.XA patent/CN106328604B/zh active Active
- 2016-04-14 TW TW105111634A patent/TWI715567B/zh active
- 2016-10-18 KR KR1020160134748A patent/KR101730344B1/ko active IP Right Grant
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000188357A (ja) * | 1998-12-22 | 2000-07-04 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
JP2006147810A (ja) * | 2004-11-19 | 2006-06-08 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
JP2009123862A (ja) * | 2007-11-14 | 2009-06-04 | Spansion Llc | 半導体装置及びその製造方法 |
JP2015508240A (ja) * | 2012-02-24 | 2015-03-16 | インヴェンサス・コーポレイション | 封止面へのワイヤボンドを有するパッケージオンパッケージアセンブリのための方法 |
JP2014135346A (ja) * | 2013-01-09 | 2014-07-24 | Fujitsu Ltd | 半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US9779940B2 (en) | 2017-10-03 |
US20170005057A1 (en) | 2017-01-05 |
CN106328604A (zh) | 2017-01-11 |
KR101730344B1 (ko) | 2017-04-27 |
KR101713643B1 (ko) | 2017-03-22 |
TWI715567B (zh) | 2021-01-11 |
CN106328604B (zh) | 2021-07-06 |
KR20170004917A (ko) | 2017-01-11 |
KR20170004796A (ko) | 2017-01-11 |
TW201703212A (zh) | 2017-01-16 |
JP6797521B2 (ja) | 2020-12-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI715567B (zh) | 晶片封裝 | |
TWI640067B (zh) | New embedded package | |
TWI658542B (zh) | 具有矩形空腔陣列的聚合物框架的製造方法 | |
US9196597B2 (en) | Semiconductor package with single sided substrate design and manufacturing methods thereof | |
US8945994B2 (en) | Single layer coreless substrate | |
KR101690549B1 (ko) | 내장 칩 패키지 | |
TWI706519B (zh) | 具有可路由囊封的傳導基板的半導體封裝及方法 | |
TWI538137B (zh) | 具有單側基板設計的半導體封裝及其製造方法 | |
TWI647790B (zh) | 以聚合物部件爲主的互連體 | |
US9589920B2 (en) | Chip package | |
JP5942823B2 (ja) | 電子部品装置の製造方法、電子部品装置及び電子装置 | |
CN107808856A (zh) | 半导体封装结构及其制造方法 | |
US11205602B2 (en) | Semiconductor device and manufacturing method thereof | |
TWI463622B (zh) | 具有單側基板設計的半導體封裝及其製造方法 | |
US11062985B2 (en) | Wiring structure having an intermediate layer between an upper conductive structure and conductive structure | |
CN219329258U (zh) | 封装结构 | |
TWI399839B (zh) | 內置於半導體封裝構造之中介連接器 | |
KR20170026214A (ko) | 개선된 칩 패키지 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20181012 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20190213 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20191015 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20191029 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20200128 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20200707 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20200925 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20201110 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20201118 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6797521 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |