TWI706519B - 具有可路由囊封的傳導基板的半導體封裝及方法 - Google Patents
具有可路由囊封的傳導基板的半導體封裝及方法 Download PDFInfo
- Publication number
- TWI706519B TWI706519B TW105119098A TW105119098A TWI706519B TW I706519 B TWI706519 B TW I706519B TW 105119098 A TW105119098 A TW 105119098A TW 105119098 A TW105119098 A TW 105119098A TW I706519 B TWI706519 B TW I706519B
- Authority
- TW
- Taiwan
- Prior art keywords
- conductive
- layer
- resin layer
- surface finishing
- semiconductor device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 144
- 238000000034 method Methods 0.000 title claims description 35
- 239000000758 substrate Substances 0.000 title claims description 29
- 229920005989 resin Polymers 0.000 claims abstract description 187
- 239000011347 resin Substances 0.000 claims abstract description 187
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 29
- 239000010949 copper Substances 0.000 claims description 47
- 238000004519 manufacturing process Methods 0.000 claims description 43
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 39
- 239000010931 gold Substances 0.000 claims description 26
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 24
- 229910052802 copper Inorganic materials 0.000 claims description 24
- 230000004048 modification Effects 0.000 claims description 23
- 238000012986 modification Methods 0.000 claims description 23
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 20
- 229910052709 silver Inorganic materials 0.000 claims description 20
- 239000004332 silver Substances 0.000 claims description 20
- 238000005538 encapsulation Methods 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 15
- 229910052737 gold Inorganic materials 0.000 claims description 13
- 229910052759 nickel Inorganic materials 0.000 claims description 13
- 238000009966 trimming Methods 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 230000008878 coupling Effects 0.000 claims description 7
- 238000010168 coupling process Methods 0.000 claims description 7
- 238000005859 coupling reaction Methods 0.000 claims description 7
- 238000000465 moulding Methods 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims 2
- 238000005530 etching Methods 0.000 description 14
- 238000000227 grinding Methods 0.000 description 13
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 230000003750 conditioning effect Effects 0.000 description 8
- 239000004642 Polyimide Substances 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000007772 electroless plating Methods 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 7
- 229920001721 polyimide Polymers 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 6
- 238000005868 electrolysis reaction Methods 0.000 description 6
- 229920006336 epoxy molding compound Polymers 0.000 description 6
- 238000001883 metal evaporation Methods 0.000 description 6
- 229920002577 polybenzoxazole Polymers 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 239000007769 metal material Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000001723 curing Methods 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 3
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 3
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 3
- 239000005011 phenolic resin Substances 0.000 description 3
- 229920001568 phenolic resin Polymers 0.000 description 3
- 229920003192 poly(bis maleimide) Polymers 0.000 description 3
- 239000002861 polymer material Substances 0.000 description 3
- 239000002775 capsule Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 238000003848 UV Light-Curing Methods 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 235000012149 noodles Nutrition 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000001029 thermal curing Methods 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4839—Assembly of a flat lead with an insulating support, e.g. for TAB
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/83439—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/83444—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/83447—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85439—Silver (Ag) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85444—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85447—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49534—Multi-layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49537—Plurality of lead frames mounted in one device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49558—Insulating layers on lead frames, e.g. bridging members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49586—Insulating layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
一種經封裝半導體裝置包含具有表面修整層的可路由的模制引線框架結構。在一個實施例中,所述可路由的模制引線框架結構包含第一層壓層,所述第一層壓層包含所述表面修整層、連接到所述表面修整層的導通孔,及覆蓋所述導通孔從而使所述表面修整層的頂部表面暴露的第一樹脂層。第二層壓層包含連接到所述導通孔的第二傳導圖案、連接到所述第二傳導圖案的凸塊墊及覆蓋所述第一樹脂層的一個側、所述第二傳導圖案及所述凸塊墊的第二樹脂層。半導體晶粒電連接到所述表面修整層,且囊封物覆蓋所述半導體晶粒及所述第一樹脂層的另一側。所述表面修整層提供用於將所述半導體晶粒連接到所述可路由的模制引線框架結構的可定制且經改進的接合結構。
Description
本發明大體上涉及電子元件,並且更具體地說,涉及半導體封裝、其結構及製造半導體封裝的方法。
相關申請案的交叉參考
本申請案主張名為“具有可路由囊封的傳導基板的半導體封裝及方法(SEMICONDUCTOR PACKAGE HAVING ROUTABLE ENCAPSULATED CONDUCTIVE SUBSTRATE AND METHOD)”的2016年6月3日在美國專利局申請的美國專利申請案第15/173,379號及2015年9月8日在韓國智慧財產權局申請的韓國專利申請案第10-2015-0126935號的優先權,且所有權益是依據35 U.S.C. §119而從所述專利申請案得到,其全部內容以引用的方式併入本文中。
一般來說,半導體封裝經設計以保護積體電路或晶片免於物理損害及外部應力。並且,半導體封裝可提供熱導路徑以有效地移除半導體晶片中產生的熱,且可進一步將電連接提供到其它元件,例如印刷電路板。用於半導體封裝的材料通常包含陶瓷及/或塑膠,且封裝技術已從陶瓷扁平封裝及雙列直插式封裝發展為引腳柵陣列及無引線晶片載體封裝,以
及其它封裝。由於對小型化和較高性能的經封裝半導體裝置的持續需求,需要較精細線寬的傳導基板;尤其是支援各種外部互連結構的傳導基板。
相應地,希望具有形成包含可路由囊封的傳導基板結構的經封裝半導體裝置的結構和方法,所述結構例如可路由的微引線框架結構,其支援對小型化和較高性能電子裝置的需求。還希望在完成經封裝半導體裝置的組裝之前製造可路由囊封的傳導基板結構或其部分以縮減製造週期時間。另外,使所述結構及方法支援多個外部互連結構將為有益的。另外,還希望使所述結構及方法容易地併入到製造流程中並且使兩者具成本效益。
本發明包含一種經封裝半導體裝置及其製造方法,以及其它特徵,所述經封裝半導體裝置包含具有傳導表面修整層的可路由囊封的傳導基板(例如,可路由的模制引線框架)。更具體地說,本文中所描述的實施例促進封裝級傳導圖案的有效路由且在表面修整層與半導體晶粒之間提供增強的連接可靠性。對於可路由囊封的傳導基板的一個實施例,表面修整層可在製造過程的初始階段形成。在可路由囊封的傳導基板的另一實施例中,表面修整層既可在製造過程的初始階段又可在最後階段形成。
在一些實施例中,傳導球在表面修整層於製造過程的初始階段形成時直接形成於不具有表面修整層的凸塊墊上、連接到所述凸塊墊或毗鄰所述凸塊墊以提供球柵陣列封裝。另外,當表面修整層於可路由囊封的傳導基板的製造過程的初始及最後階段中的每一者處形成時,形成於最後階段的表面修整層可用作輸入/輸出終端以提供柵格陣列封裝。
在一些優選實施例中,用於形成可路由的模制引線框架的第一樹脂層及第二樹脂層的材料以及用於形成囊封半導體晶粒的封裝體的材料為相同的,或具有相似的熱膨脹係數以及其它相似材料屬性,進而在裝置的製造過程或操作期間有效地抑制翹曲。
更具體地說,在一個實施例中,一種半導體裝置包括第一層壓層,所述第一層壓層包含:第一表面修整層;第一傳導圖案,其包括連接到第一表面修整層的第一部分及與第一表面修整層側向隔開的第二部分;傳導導通孔,其連接到第一傳導圖案;及第一樹脂層,其覆蓋第一傳導圖案、傳導導通孔,及第一表面修整層的一部分,其中第一表面修整層暴露於第一樹脂層的第一表面中且傳導導通孔暴露於第一樹脂層的第二表面中。第二層壓層鄰近於第一層壓層而安置,且包含連接到傳導導通孔的第二傳導圖案、連接到第二傳導圖案的傳導墊,及覆蓋第一樹脂層、第二傳導圖案及傳導墊的至少一部分的第二樹脂層,其中傳導墊暴露於第二樹脂層的第一表面中。半導體晶粒電連接到第一表面修整層,且囊封物覆蓋第一層壓層及半導體晶粒的至少一部分。
在另一實施例中,一種經封裝半導體裝置包含可路由囊封的傳導基板,其包括囊封在第一樹脂層內的第一傳導結構、電連接到第一傳導結構且囊封在第二樹脂層內的第二傳導結構,及安置在第一傳導結構的至少部分上的第一表面修整層。第一表面修整層暴露於第一樹脂層中且第二傳導結構的至少部分暴露於第二樹脂層中。半導體晶粒電連接到第一表面修整層且囊封物囊封半導體晶粒及第一表面修整層。
在另一實施例中,製造半導體裝置的方法包含提供可路由囊
封的傳導基板,其包括囊封在第一樹脂層內的第一傳導結構、電連接到第一傳導結構且囊封在第二樹脂層內的第二傳導結構以及安置在第一傳導結構的至少部分上的第一表面修整層,其中第一表面修整層暴露在第一樹脂層中且第二傳導結構的至少部分暴露在第二樹脂層中。所述方法包含將半導體晶粒電連接到第一表面修整層以及形成覆蓋半導體晶粒及第一表面修整層的囊封物。
100:半導體裝置
101:可路由囊封的傳導基板/可路由的模制引線框架
110:第一層壓層/第一囊封層
111:第一表面修整層/第一接合層/第一可線接合修整層
112,112’:第一傳導圖案
113:導通孔/傳導導通孔/傳導柱
114,114’:第一樹脂層
114a,114a’:第一開口
120:第二層壓層/第二囊封層
121:第二傳導圖案
122,122’:凸塊墊
123,123’:第二樹脂層
123a,123a’:第二開口
130:半導體晶粒
135:黏著劑
140:傳導連接結構/導線
150:囊封物
160:傳導凸塊
170:載體
171:載體
172:載體
200:半導體裝置
224:第二表面修整層
300:半導體裝置
311:第一表面修整層/第一接合層/第一可線接合修整層
400:半導體裝置
411:第一表面修整層/第一接合層/第一可線接合修整層
435:微凸塊
通過參考附圖詳細描述其示例性實施例,本發明的上述以及其它特徵將變得更加顯而易見,在附圖中:圖1A為根據本發明的實施例的說明經封裝半導體裝置的橫截面圖;圖1B為說明圖1A的區的放大橫截面圖;圖2A為根據本發明的另一實施例的說明經封裝半導體裝置的橫截面圖;圖2B為說明圖2A的區的放大橫截面圖;圖2C為根據替代性實施例的說明圖2A的區的放大橫截面圖;圖3為根據本發明的另一實施例的說明經封裝半導體裝置的橫截面圖;圖4為根據本發明的又一實施例的說明經封裝半導體裝置的橫截面圖;圖5A為說明由(N×M)個單元構成的載體的平面圖;
圖5B為說明由N個單元構成的載體的平面圖;圖6A到圖6J為根據本發明的實施例的依序說明經封裝半導體裝置的製造方法的橫截面圖;圖7A到圖7C為根據本發明的另一個實施例的依序說明經封裝半導體裝置的製造方法的橫截面圖;圖8A到圖8I為根據本發明的另一實施例的依序說明經封裝半導體裝置的製造方法的橫截面圖;且圖9A到圖9C為根據本發明的又一實施例的依序說明經封裝半導體裝置的製造方法的橫截面圖。
為了說明的簡單和清楚起見,圖中的元件未必按比例繪製,並且相同參考數位在不同圖中表示相同元件。另外,為了描述的簡單起見省略眾所周知的步驟和元件的描述和細節。如本文中所使用,術語“及/或”包含相關聯的所列項目中的一或多者的任何及所有組合。另外,本文中所使用的術語僅僅是出於描述特定實施例的目的而並不意圖限制本發明。如本文中所使用,除非上下文另外明確指示,否則單數形式也意圖包含複數形式。將進一步理解術語“包括(comprises/comprising)”及/或“包含(includes/including)”在用於本說明書時規定所陳述的特徵、數目、步驟、操作、元件及/或元件的存在,但是並不排除一個或多個其它特徵、數目、步驟、操作、元件、元件及/或其群組的存在或添加。將理解,儘管術語“第一”、“第二”等可在本文中使用以描述各個部件、元件、區、層及/或區段,但這些部件、元件、區、層及/或區段應不受這些術語限制。這些術語
僅用於區分一個部件、元件、區、層及/或區段與另一部件、元件、區、層及/或區段。因此,舉例來說,下文論述的第一部件、第一元件、第一區、第一層及/或第一區段可被稱為第二部件、第二元件、第二區、第二層及/或第二區段而不脫離本發明的教示。參考“一個實施例”或“實施例”意味著結合實施例描述的特定特徵、結構或特性包含於本發明的至少一個實施例中。因此,在本說明書通篇的各個位置中短語“在一個實施例中”或“在實施例中”的出現未必全部是指同一實施例,但是在一些情況下可以指同一實施例。此外,特定特徵、結構或特性可以任何合適方式組合,如在一或多個實施例中將對於所屬領域的一般技術人員是顯而易見的。另外,術語“在…時”是指某一動作至少出現在起始動作的持續時間的某一部分內。詞語“大約”、“近似”或“基本上”的使用是指元件的值預期為接近一種狀態值或位置。然而,眾所周知,在本領域中總是存在妨礙值或位置恰好如所陳述的一般的輕微變化。除非另外規定,否則如本文中所使用,詞語“在…上面”或“在…上”包含所規定的元件可直接或間接物理接觸的定向、放置或關係。應進一步理解,下文中所說明及描述的實施例適當地可具有實施例及/或可在無本文中確切地揭示的任何元件存在的情況下實踐。
圖1A為根據第一實施例的說明具有表面修整層的半導體裝置100或經封裝半導體裝置100的橫截面圖,且圖1B為說明圖1A的區的放大橫截面圖。如圖1A中所說明,半導體裝置100包含第一層壓層110或第一囊封層110、第二層壓層120或第二囊封層120、半導體晶粒130、傳導連接結構140(例如導線140)、囊封物150、凸塊墊122以及傳導凸塊160。
根據本實施例,第一層壓層110及第二層壓層120可被稱作可路由的模制引線框架101或可路由囊封的傳導基板101。
在一個實施例中,第一層壓層110包含第一表面修整層111、第一接合層111或第一可線接合修整層111、第一傳導圖案112、導通孔113、傳導導通孔113或傳導柱113以及第一樹脂層114。在一些實施例中,第一表面修整層111可為金屬材料,例如鎳/金(Ni/Au)、銀(Ag)、銅(Cu)、其組合以及其等效物,但本實施例的方面不限於此。在一個實施例中,第一傳導圖案112可安置在第一表面修整層111上或毗鄰所述第一表面修整層111,及/或可與第一表面修整層111隔開而安置。第一傳導圖案112可由金屬製成,例如銅(Cu)及其等效物,但本實施例的方面不限於此。在一個實施例中,導通孔113形成於第一傳導圖案112上、連接到所述第一傳導圖案112,或毗鄰所述第一傳導圖案112,且相較於第一傳導圖案112可具有較小寬度及較大厚度。導通孔113也可由金屬製成,例如銅(Cu)及其等效物,但本實施例的方面不限於此。第一樹脂層114可覆蓋第一表面修整層111、第一傳導圖案112及導通孔113。然而,第一表面修整層111及第一傳導圖案112的頂部表面可不由第一樹脂層114覆蓋。並且,導通孔113的底部表面可不由第一樹脂層114覆蓋。第一樹脂層114可由聚合物材料製成,例如一或多種聚醯亞胺(PI)、苯並環丁烯(BCB)、聚苯並惡唑(PBO)、雙馬來醯亞胺三嗪(BT)、酚系樹脂、環氧模制化合物及其等效物,但本實施例的方面不限於此。在一些實施例中,導通孔113連接到第一傳導圖案112的僅第一部分,從而使第一傳導圖案112的第二部分至少部分地嵌入在第一樹脂層114內,如圖1A中大體上所說明。
在一個實施例中,第二層壓層120包含第二傳導圖案121、凸塊墊122,及第二樹脂層123。在一個實施例中,第二傳導圖案121可安置在導通孔113上或毗鄰所述導通孔113,且可定位成鄰近於第一樹脂層114的底部表面。在一些實施例中,第二傳導圖案121可安置在第一樹脂層114的底部表面上或毗鄰所述第一樹脂層114的所述底部表面。另外,第二傳導圖案121可為金屬,例如銅(Cu)及其等效物,但本實施例的方面不限於此。在一個實施例中,凸塊墊122可形成於第二傳導圖案121上,連接到所述第二傳導圖案121,或毗鄰所述第二傳導圖案121,且可相較於第二傳導圖案121具有較小寬度及較大厚度。凸塊墊122也可為金屬,例如銅(Cu)及其等效物,但本實施例的方面不限於此。第二樹脂層123可覆蓋第一樹脂層114、第二傳導圖案121及凸塊墊122的至少部分。然而,第二傳導圖案121的頂部表面可不由第二樹脂層123覆蓋。並且,凸塊墊122的底部表面可不由第二樹脂層123覆蓋且可暴露於外部。第二樹脂層123可由聚合物材料製成,例如一或多種聚醯亞胺(PI)、苯並環丁烯(BCB)、聚苯並惡唑(PBO)、雙馬來醯亞胺三嗪(BT)、酚系樹脂、環氧模制化合物及其等效物,但本實施例的方面不限於此。
根據本實施例,包含第一層壓層110及第二層壓層120的堆疊結構可被稱作可路由囊封的傳導基板101或可路由的模制引線框架101,所述可路由囊封的傳導基板101或所述可路由的模制引線框架101可在製造半導體裝置100的過程中作為單個單元處置。
在一個實施例中,半導體晶粒130連接到可路由的模制引線框架101。在一些實施例中,半導體晶粒130使用(例如)黏著劑135附接
到第一層壓層110,且進一步電連接到第一層壓層110。根據一個實施例,半導體晶粒130可使用導線140電連接到第一表面修整層111。在一個實施例中,導線140包括金線,且第一表面修整層111包括鎳/金(Ni/Au)或銀(Ag)。在此實施例中,導線140及第一表面修整層111可較容易地彼此連接。在一些實施例中,半導體晶粒130可包含電路,其包含(例如)數位訊號處理器(DSP)、網路處理器、功率管理單元、音訊處理器、RF電路、無線基帶晶片上系統(SoC)處理器、感測器、專用積體電路(ASIC),及/或所屬技術領域中具有通常知識者已知的其它有源及/或無源電子裝置。
在一個實施例中,囊封物150囊封、覆蓋或模制可路由的模制引線框架101,所述可路由的模制引線框架101包含(例如)半導體晶粒130及導線140,以及第一層壓層110的至少部分。在一些實施例中,囊封物150可覆蓋第一表面修整層111及第一傳導圖案112。囊封物150可為聚合物複合材料,例如,用於通過模制過程執行囊封的環氧模制化合物、用於通過分配器執行囊封的液體囊封部件,或其等效物,但本實施例的方面不限於此。在一個優選實施例中,當第一樹脂層114、第二樹脂層123及囊封物150使用同一材料形成時,其可具有相同熱膨脹係數,進而在半導體裝置100的製造過程或操作期間最小化翹曲。
在一個實施例中,傳導凸塊160可連接到凸塊墊122。在一個實施例中,傳導凸塊160可熔接或附接到凸塊墊122,所述凸塊墊122不由第二樹脂層123覆蓋。傳導凸塊160可為導柱、具有焊蓋的導柱、傳導球、焊球及其等效物,但本實施例的方面不限於此。在所說明的實施例中,傳導凸塊160作為一個實例展示為傳導球。
根據本實施例,半導體裝置100經配置為經線接合的可路由的模制引線框架封裝,其經進一步配置為球柵陣列類型封裝。
根據本實施例,包含(例如)第一層壓層110及第二層壓層120的可路由的模制引線框架101及囊封物150的側表面通過在製造半導體裝置100的過程中分離而經配置為彼此共面。在一個實施例中,以下各者的側表面基本上彼此共面:第一層壓層110的第一樹脂層114、第二層壓層120的第二樹脂層123以及囊封物150。在一個優選的實施例中,第一層壓層110的第一傳導圖案112不通過第一樹脂層114的側表面暴露於外部,且第二層壓層120的第二傳導圖案121不通過第二樹脂層123的側表面暴露於外部。因此,可防止第一傳導圖案112及第二傳導圖案121中的每一者與外部裝置之間的不必要的電短路。另外,因為第一表面修整層111形成於第一傳導圖案112上,因此導線140可容易地連接到第一表面修整層111。
如圖1B中所說明,在一個實施例中,第一表面修整層111的頂部表面基本上與第一樹脂層114的頂部表面共面。然而,與第一表面修整層111水準或側向隔開的第一傳導圖案112中的每一者的頂部表面可低於第一樹脂層114的頂部表面或相對於所述第一樹脂層114的所述頂部表面凹陷。此外,凸塊墊122中的每一者的底部表面高於第二樹脂層123的底部表面或相對於所述第二樹脂層123的所述底部表面凹陷。換句話說,第一傳導圖案112中的每一者的頂部表面在形成於第一樹脂層114中的第一開口114a內部凹陷。同樣地,凸塊墊122中的每一者的底部表面在形成於第二樹脂層123中的第二開口123a內部凹陷。
根據本實施例,此類配置特徵可由製造過程所造成。舉例來
說,當對第一樹脂層114執行移除步驟(例如研磨及/或蝕刻)時,第一表面修整層111充當遮罩,且第一傳導圖案112中的每一者的頂部表面可比第一樹脂層114略微多地過度蝕刻以使得第一傳導圖案112中的每一者的頂部表面可定位在第一開口114a內部或在所述第一開口114a內凹陷。另外,當對第二樹脂層123執行移除步驟(例如,研磨及/或蝕刻)時,第二傳導圖案121中的每一者的底部表面相對於第二樹脂層123過度蝕刻,以使得第二傳導圖案121中的每一者的底部表面可定位在第二開口123a內部或在所述第二開口123a內凹陷。
因此,根據本實施例,形成於第一樹脂層114中的第一開口114a改進囊封物150與第一樹脂層114之間的耦合力,且形成於第二樹脂層123中的第二開口123a改進傳導凸塊160、凸塊墊122及第二樹脂層123中的每一者之間的耦合力。在一些實施例中,導通孔113及第一傳導圖案112及/或第二傳導圖案121以及凸塊墊122的部分於如在圖1B中大體上所說明的橫截面圖中形成如同“T”的形狀。在一些實施例中,第一傳導圖案112及導通孔113為第一傳導結構的實例,且第二傳導圖案121及凸塊墊122為第二傳導結構的實例。換句話說,第一傳導結構可包括第一傳導圖案112及導通孔113,且第二傳導結構可包括第二傳導圖案121及凸塊墊122。
圖2A為根據另一實施例的說明具有表面修整層的半導體裝置200或經封裝半導體裝置200的橫截面圖;圖2B為說明圖2A的區的放大橫截面圖;且圖2C為根據替代性實施例的說明不具有表面修整層的區的放大橫截面圖。
如圖2A中所說明,代替使用傳導凸塊,可路由的模制引線
框架101可替代地包含形成於第二層壓層120的凸塊墊122上或連接到所述第二層壓層120的所述凸塊墊122的第二表面修整層224或第二接合層224。在一些實施例中,第二表面修整層224可包括金屬材料,例如鎳/金(Ni/Au)、銀(Ag)、錫(Sn)、其組合及其等效物,但本發明的實施例的方面不限於此。根據本實施例,半導體裝置200經配置為經線接合的可路由的模制引線框架封裝,其經進一步配置為柵格陣列類型封裝。在另一實施例中,傳導凸塊可連接到第二表面修整層224。
如圖2B中所說明,在一個實施例中,第一表面修整層111的頂部表面基本上與第一樹脂層114的頂部表面共面,且第二表面修整層224的底部表面基本上與第二樹脂層123的底部表面共面。然而,與第一表面修整層111水準或側向隔開的第一傳導圖案112中的每一者的頂部表面可低於第一樹脂層114的頂部表面或相對於所述第一樹脂層114的所述頂部表面凹陷。換句話說,第一傳導圖案112中的每一者的頂部表面在形成於第一樹脂層114中的第一開口114a內部凹陷。
根據本實施例,此類配置特徵可由製造過程所造成。舉例來說,當對第一樹脂層114及/或第二樹脂層123執行移除步驟(例如,研磨及/或蝕刻)時,第一表面修整層111及/或第二樹脂層123充當遮罩,且第一傳導圖案112中的每一者的頂部表面可比第一樹脂層114略微多地過度蝕刻,以使得第一傳導圖案112中的每一者的頂部表面定位在形成於第一樹脂層114中的第一開口114a內部或在所述第一開口114a內凹陷。
如圖2C中所說明,當第一傳導圖案112'上無第一表面修整層形成且凸塊墊122'上無第二表面修整層形成時,第一傳導圖案112'中的每
一者的頂部表面可定位成低於第一樹脂層114'的頂部表面或相對於所述第一樹脂層114'的所述頂部表面凹陷,且凸塊墊122'中的每一者的底部表面可定位成高於第二樹脂層123'的底部表面或相對於所述第二樹脂層123'的所述底部表面凹陷。在一個實施例中,當在不存在遮罩層的情況下對第一樹脂層114'及/或第二樹脂層123'執行移除步驟(例如,研磨及/或蝕刻)時,第一傳導圖案112'中的每一者的頂部表面及/或凸塊墊122'中的每一者的底部表面可相較於第一樹脂層114'及/或第二樹脂層123'過度蝕刻。因此,第一傳導圖案112'定位在第一樹脂層114'的第一開口114a'內部或在所述第一樹脂層114'的所述第一開口114a'內凹陷,且凸塊墊122'中的每一者的底部表面定位在第二樹脂層123'的第二開口123a'內部或在所述第二樹脂層123'的所述第二開口123a'內凹陷。
圖3為根據另一實施例的說明具有表面修整層的半導體裝置300或經封裝半導體裝置300的橫截面圖。如圖3中所說明,第一表面修整層311、第一接合層311或第一可線接合修整層311包括金屬材料,例如銀(Ag),且由銅(Cu)製成的導通孔113可形成於第一表面修整層311上,連接到所述第一表面修整層311,或毗鄰所述第一表面修整層311。根據本實施例,在半導體裝置300中,導線140可較容易地接合到由銀(Ag)製成的第一表面修整層311。另外,根據本實施例,半導體裝置300經配置為經線接合的可路由的模制引線框架封裝,其經進一步配置為球柵陣列類型封裝。此外,根據本實施例,第一表面修整層311還可經配置為用於半導體裝置300的第一傳導圖案。在一些實施例中,導通孔113為第一傳導結構的實例,且第二傳導圖案121及凸塊墊122為第二傳導結構的實例。
圖4為根據又一實施例的說明具有表面修整層的半導體裝置400或經封裝半導體裝置400的橫截面圖。如圖4中所說明,第一表面修整層411、第一接合層411或第一可線接合修整層411可包括金屬材料,例如銅(Cu),且由銅(Cu)製成的導通孔113可形成於第一表面修整層411上,連接到所述第一表面修整層411,或毗鄰所述第一表面修整層411。根據本實施例,因為半導體晶粒130不通過線接合直接連接到第一表面修整層411,因此其可通過其它類型的傳導連接結構(例如,微凸塊435)連接到第一表面修整層411。在一個實施例中,半導體晶粒130以倒裝晶片型配置電連接到第一表面修整層411。另外,囊封物150插入在半導體晶粒130與第一層壓層110之間,進而允許半導體晶粒130及第一層壓層110彼此機械地整合。另外,由金屬材料(例如,鎳/金(Ni/Au)、銀(Ag)或錫(Sn))製成的第二表面修整層224或第二接合層224可形成於凸塊墊122上而非傳導凸塊上。根據本實施例,半導體裝置400經配置為倒裝晶片可路由的模制引線框架封裝,其經進一步配置為柵格陣列類型封裝。根據本實施例,第一表面修整層411還可經配置為用於半導體裝置400的第一傳導圖案。在一替代性實施例中,傳導凸塊可形成於第二表面修整層224上。在一些實施例中,導通孔113為第一傳導結構的實例,且第二傳導圖案121及凸塊墊122為第二傳導結構的實例。應理解,圖4中用於半導體晶粒130的附接配置可用於本文中所描述的實施例中的任一者中。
圖5A為說明由經封裝單元的N×M矩陣或陣列構成的載體171的平面圖,且圖5B為說明由1xM個單元構成的載體172的平面圖。如圖5A中所說明,於其上製造(例如)半導體裝置100到400的載體171形
成於由N×M個單元構成的矩陣中。在一個實施例中,N及M優選地可為大於或等於2的整數。如上文所描述,由於載體171以矩陣類型形成,因此可大批量地製造根據本發明的實施例的半導體裝置100到半導體裝置400。如圖5B中所說明,載體172可作為1xM個單元的條帶形成。在一個實施例中,M優選地可為大於1的整數。
圖6A到圖6J為依序說明具有表面修整層111的半導體裝置100或經封裝半導體裝置100的製造方法的實施例的橫截面圖。如圖6A到圖6J中所說明,半導體裝置100的製造方法包含以下步驟:提供載體170及形成第一表面修整層111;形成第一傳導圖案112;形成導通孔113;提供第一樹脂層114;首先移除(例如,研磨)第一樹脂層114的一部分;形成第二傳導圖案121;形成凸塊墊122;提供第二樹脂層123;移除載體170;連接半導體晶粒130;形成囊封物150;以及形成傳導凸塊160。
如圖6A中所說明,在提供載體170及形成第一表面修整層111的步驟中,製備具有(例如)基本上扁平板狀形狀的載體170,且多個第一表面修整層111形成於載體170的主表面上或鄰近於所述載體170的所述主表面形成。在一個實施例中,載體170可由傳導材料(例如,銅(Cu))、絕緣材料(例如,聚醯亞胺)及/或陶瓷材料(例如,氧化鋁),或所屬技術領域中具有通常知識者已知的其它材料製成。在載體170由傳導材料製成的一些實施例中,第一表面修整層111可形成於載體170的表面上,連接到所述載體170的所述表面,或毗鄰所述載體170的所述表面。在載體170由絕緣材料或陶瓷材料製成的其它實施例中,傳導晶種層(由(例如)鎢或鎢鈦製成)可首先形成,且第一表面修整層111接著可形成於傳導晶種層
上,連接到所述傳導晶種層,或毗鄰所述傳導晶種層。另外,第一表面修整層111可通過物理氣相沉積(PVD)、化學氣相沉積(CVD)、金屬濺鍍、金屬蒸鍍、電解或無電電鍍或所屬技術領域中具有通常知識者已知的其它形成技術形成。根據本實施例,第一表面修整層111包括較容易地接合到傳導連接結構(例如,連接線或凸塊)或與所述傳導連接結構形成接合的材料。另外,第一表面修整層111優選地包括相對於第一傳導圖案112選擇性地蝕刻的材料。在一些實施例中,第一表面修整層111可由鎳/金(Ni/Au)或銀(Ag)製成,但本實施例的方面不限於此。在一個實施例中,第一表面修整層111具有在從大約0.1微米到15微米的範圍內的厚度。
如圖6B中所說明,在形成第一傳導圖案112的步驟中,第一傳導圖案112形成於第一表面修整層111及載體170的表面上,連接到所述第一表面修整層111及所述載體170的表面,或毗鄰所述第一表面修整層111及所述載體170的表面。更具體地說,第一傳導圖案經配置為經路由的第一傳導圖案112,且可形成於第一表面修整層111及載體170的表面上。第一傳導圖案112可通過PVD、CVD、金屬濺鍍、金屬蒸鍍、電解或無電電鍍或所屬技術領域中具有通常知識者已知的其它形成技術形成。另外,第一傳導圖案112可由傳導材料製成,例如銅(Cu)。在一個實施例中,第一傳導圖案112具有在從大約3微米到30微米的範圍內的厚度。
如圖6C中所說明,在形成導通孔113、傳導導通孔113或傳導柱113的步驟中,形狀為相對厚的導柱的導通孔113形成於第一傳導圖案112上,連接到所述第一傳導圖案112,或毗鄰所述第一傳導圖案112。導通孔113可通過無電電鍍及/或電鍍形成且可由銅(Cu)製成。在一個實
施例中,導通孔113具有在從大約20微米到100微米的範圍內的厚度。
如圖6D中所說明,在形成第一樹脂層114的步驟中,第一樹脂層114形成或被塗布到載體170上,進而允許第一樹脂層114覆蓋載體170、第一表面修整層111、第一傳導圖案112及導通孔113。在一些實施例中,第一樹脂層114可通過(例如)旋塗、噴塗或深塗接著通過UV及/或熱固化而形成於載體170上。第一樹脂層114可由聚合物材料製成,例如一或多種聚醯亞胺(PI)、苯並環丁烯(BCB)、聚苯並惡唑(PBO)、雙馬來醯亞胺三嗪(BT)、酚系樹脂、環氧模制化合物及其等效物,但本實施例的方面不限於此。在一個實施例中,第一樹脂層114與囊封物150相似可由普通環氧模制化合物製成。在此實施例中,第一樹脂層114可通過壓縮模塑或傳遞模塑形成。
如圖6E中所說明,在第一次移除的步驟中,使用(例如)研磨及/或蝕刻製程部分地移除第一樹脂層114直到導通孔113暴露於第一樹脂層114外部為止。以此方式,導通孔113的頂部表面變得基本上與第一樹脂層114的頂部表面共面。
根據本實施例,第一表面修整層111、第一傳導圖案112、導通孔113及第一樹脂層114可共同地界定為第一層壓層110。
如圖6F中所說明,在形成第二傳導圖案121的步驟中,第二傳導圖案121形成於通過第一樹脂層114暴露於外部的導通孔113上,毗鄰所述導通孔113,或連接到所述導通孔113。在一個實施例中,第二傳導圖案121於第二樹脂層123上路由同時電連接到導通孔113。第二傳導圖案121可通過PVD、CVD、金屬濺鍍、金屬蒸鍍、電解或無電電鍍或所屬技術
領域中具有通常知識者已知的其它形成技術形成。另外,第二傳導圖案121可由傳導材料製成,例如銅(Cu)。在一個實施例中,第二傳導圖案121具有在從大約3微米到15微米的範圍內的厚度。
如圖6G中所說明,在形成凸塊墊122的步驟中,凸塊墊122形成於第二傳導圖案121上,連接到所述第二傳導圖案121,或毗鄰或連接到所述第二傳導圖案121。凸塊墊122可通過PVD、CVD、金屬濺鍍、金屬蒸鍍、電解或無電電鍍或所屬技術領域中具有通常知識者已知的其它形成技術形成。另外,凸塊墊122可由傳導材料製成,例如銅(Cu)。在一個實施例中,凸塊墊122具有在從大約20微米到100微米的範圍內的厚度。
如圖6H中所說明,在形成第二樹脂層123的步驟中,第二樹脂層123形成或被塗布到第一層壓層110上,進而允許第二樹脂層123覆蓋第一樹脂層114、第二傳導圖案121及凸塊墊122。在一些實施例中,第二樹脂層123可以與第一樹脂層114相同的方法且使用與第一樹脂層114相同的材料塗布。另外,在塗布以及固化第二樹脂層123之後,可進一步執行第二次移除步驟。在第二次移除步驟中,使用(例如)研磨及/或蝕刻製程部分地移除第二樹脂層123直到凸塊墊122暴露於第二樹脂層123外部為止。以此方式,凸塊墊122的頂部表面變得基本上與第二樹脂層123的頂部表面共面。在一個實施例中,如果凸塊墊122上無遮罩層形成,那麼凸塊墊122的表面在如圖1B中所說明的蝕刻製程之後定位在第二樹脂層123的第二開口內部或在所述第二樹脂層123的所述第二開口內部凹陷。
根據本實施例,第二傳導圖案121、凸塊墊122及第二樹脂層123可集體地界定為第二層壓層120。另外,第一層壓層110及第二層壓
層120可集體地界定為可路由的模制引線框架101。
如圖6I中所說明,在移除載體170的步驟中,從第一層壓層110移除載體170。更具體地說,從第一表面修整層111、第一傳導圖案112及第一樹脂層114移除載體170,進而允許第一表面修整層111、第一傳導圖案112及第一樹脂層114暴露於外部。在一個實施例中,可使用研磨及/或蝕刻製程移除載體170。在一個實施例中,不具有第一表面修整層111的第一傳導圖案112的表面可過度蝕刻以定位在如圖1B中所說明的第一樹脂層114的第一開口內部或在所述第一樹脂層114的所述第一開口內凹陷。
如圖6J中所說明,在連接半導體晶粒130、形成囊封物150及形成傳導凸塊160的步驟中,半導體晶粒130可使用(例如)黏著劑135附接到第一層壓層110。並且,半導體晶粒130可使用傳導連接結構(例如,導線140)電連接到第一表面修整層111。接下來,半導體晶粒130及導線140使用囊封物150加以囊封。囊封物150可為聚合物複合材料,例如,用於通過模制過程執行囊封的環氧模制化合物、用於通過分配器執行囊封的液體囊封部件,或其等效物,但本實施例的方面不限於此。在一個實施例中,傳導凸塊160形成於通過第二層壓層120暴露於外部的凸塊墊122上或連接到所述凸塊墊122。傳導凸塊160可選自由以下組成的群組:導柱、具有焊蓋的導柱、傳導球、焊球,及其等效物,但本實施例的方面不限於此。在圖6J的所說明的實施例中,傳導凸塊160作為一實例實施例展示為傳導球。
另外,如上文所描述,由於本實施例的過程可以N×M矩陣或1xM個條帶的形式執行,因此可接著執行分離過程(例如,鋸切過程)
以產生個別半導體裝置100。
根據本實施例,提供用於製造半導體裝置100的製造方法,其中第一表面修整層111首先形成且結構及元件的其餘部分可隨後形成。具體地說,本實施例提供經線接合的可路由的模制引線框架球柵陣列類型封裝。
圖7A到圖7C為依序說明用於具有另一表面修整層224的半導體裝置200或經封裝半導體裝置200的製造方法的實施例的橫截面圖。在本實施例中,可使用結合圖6A到圖6H說明的製造步驟,且將不在此處再次重複其細節。
如圖7A中所說明,在形成(例如,塗布以及固化)第二樹脂層123以及部分地移除(例如,研磨及/或蝕刻)第二樹脂層123的步驟之後,第二表面修整層224可進一步形成於通過第二樹脂層123暴露於外部的凸塊墊122上,連接到所述凸塊墊122,或毗鄰所述凸塊墊122。在一個實施例中,第二表面修整層224可通過PVD、CVD、金屬濺鍍、金屬蒸鍍、電解或無電電鍍或所屬技術領域中具有通常知識者已知的其它形成技術形成。根據本實施例,第二表面修整層224包括較容易地接合到安置在組裝的下一級上的傳導結構(例如,印刷電路板)或與所述傳導結構形成接合。在一些實施例中,第二表面修整層224可由鎳/金(Ni/Au)、銀(Ag)、錫(Sn)及其等效物製成,但本實施例的方面不限於此。
如圖7B中所說明,由於移除載體170,因此提供可路由的模制引線框架101,所述可路由的模制引線框架101具有通過第一層壓層110暴露於外部的第一表面修整層111及第一傳導圖案112,以及通過第二層壓
層120暴露於外部的第二表面修整層224。根據本實施例,第一表面修整層111在可路由的模制引線框架101的製造過程的初始階段形成,且第二表面修整層224在可路由的模制引線框架101的製造過程的最後階段形成。
如圖7C中所說明,半導體晶粒130使用(例如)黏著劑135附接到可路由的模制引線框架101,且半導體晶粒130由傳導連接結構(例如,導線140)電連接到第一表面修整層111。另外,半導體晶粒130及導線140可使用如先前所描述的囊封物150加以囊封或模制。
根據本實施例,傳導凸塊可不包含在凸塊墊122上,且先前形成的第二表面修整層224暴露於外部。因此,本實施例提供經線接合的可路由的模制引線框架柵格陣列封裝。在一替代性實施例中,傳導凸塊也可形成於第二表面修整層224上。
圖8A到圖8I為根據另一實施例的依序說明具有表面修整層311的半導體裝置300或經封裝半導體裝置300的製造方法的橫截面圖。如圖8A到圖8I中所說明,半導體裝置300的製造方法可包含以下步驟:提供載體170及形成第一表面修整層311;形成導通孔113;提供第一樹脂層114;首先移除(例如,研磨);形成第二傳導圖案121;形成凸塊墊122;提供第二樹脂層123;移除載體170;連接半導體晶粒130;形成囊封物150;以及形成傳導凸塊160。
如圖8A中所說明,在提供載體170及形成第一表面修整層111的步驟中,製備如先前所描述的載體170,且第一表面修整層311形成於載體170上。在一個實施例中,第一表面修整層311可基本上充當第一傳導圖案。根據本實施例,第一表面修整層311包括較容易地接合到傳導連
接結構(例如,連接線或凸塊)或與所述傳導連接結構形成接合的材料。在一些實施例中,第一表面修整層311可由銀(Ag)製成。另外,第一表面修整層311可通過PVD、CVD、金屬濺鍍、金屬蒸鍍、電解或無電電鍍或所屬技術領域中具有通常知識者已知的其它形成技術形成。在一個實施例中,第一表面修整層311具有在從大約3微米到15000微米的範圍內的厚度。
如圖8B中所說明,在形成導通孔113的步驟中,形狀為相對厚的導柱的導通孔113形成於第一表面修整層311上,連接到所述第一表面修整層311,或毗鄰所述第一表面修整層311。導通孔113可由銅(Cu)製成且如先前所描述而形成。
如圖8C中所說明,在提供第一樹脂層114的步驟中,第一樹脂層114形成或被塗布到如先前所描述的載體170上,進而允許第一樹脂層114覆蓋載體170、第一表面修整層311及導通孔113。
如圖8D中所說明,在第一次移除的步驟中,使用(例如)研磨及/或蝕刻製程部分地移除第一樹脂層114直到導通孔113暴露於第一樹脂層114外部為止。根據本實施例,第一表面修整層311、導通孔113及第一樹脂層114可集體地界定為第一層壓層110。
如圖8E中所說明,在形成第二傳導圖案121的步驟中,第二傳導圖案121形成於通過第一樹脂層114暴露於外部的導通孔113上,連接到所述導通孔113,或毗鄰所述導通孔113。根據本實施例,第二傳導圖案121於第二樹脂層123上路由同時電連接到導通孔113。第二傳導圖案121可如先前所描述而形成且可由銅(Cu)或所屬技術領域中具有通常知識者
已知的其它材料製成。
如圖8F中所說明,在形成凸塊墊122的步驟中,凸塊墊122形成於第二傳導圖案121上或連接到所述第二傳導圖案121。凸塊墊122可如先前所描述而形成且可由銅(Cu)或所屬技術領域中具有通常知識者已知的其它材料製成。
如圖8G中所說明,在提供第二樹脂層123的步驟中,第二樹脂層123形成或被塗布到第一層壓層110上,進而安置第二樹脂層123以覆蓋第一樹脂層114、第二傳導圖案121及凸塊墊122。另外,在塗布以及固化第二樹脂層123之後,可進一步執行第二次移除步驟。在第二次移除步驟中,使用(例如)研磨及/或蝕刻製程部分地移除第二樹脂層123直到凸塊墊122暴露於第二樹脂層123外部為止。在一個實施例中,如果凸塊墊122上無遮罩層形成,那麼凸塊墊122的表面可在蝕刻步驟之後定位在第二樹脂層123的第二開口內部或在所述第二樹脂層123的所述第二開口內凹陷。
根據本實施例,第二傳導圖案121、凸塊墊122及第二樹脂層123可集體地界定為第二層壓層120。
如圖8H中所說明,在移除載體170的步驟中,從第一層壓層110移除載體170。更具體地說,從第一表面修整層311及第一樹脂層114移除載體170,進而允許第一表面修整層311及第一樹脂層114暴露於外部。在一個實施例中,可使用研磨及/或蝕刻製程移除載體170。根據本實施例,包含銀(Ag)的第一表面修整層311充當遮罩,第一表面修整層311的表面變得基本上與第一樹脂層114的表面共面。
如圖8I中所說明,在連接半導體晶粒130、形成囊封物150及形成傳導凸塊160的步驟中,半導體晶粒130可使用(例如)黏著劑135附接到第一層壓層110。並且,半導體晶粒130使用傳導連接結構(例如,導線140)電連接到第一表面修整層311。接下來,半導體晶粒130及導線140使用如先前所描述的囊封物150加以囊封。在一個實施例中,傳導凸塊160形成於通過第二層壓層120暴露於外部的凸塊墊122上或連接到所述凸塊墊122。
如上文所描述,本實施例提供半導體裝置300的製造方法,其中可包括銀(Ag)的第一表面修整層311首先形成且結構及元件的其餘部分可隨後形成。另外,本實施例提供經線接合的可路由的模制引線框架球柵陣列封裝。
圖9A到圖9C為根據又一實施例的依序說明具有表面修整層的半導體裝置400或經封裝半導體裝置400的製造方法的橫截面圖。在本實施例中,可使用結合圖8A到圖8G說明的製造步驟,且將不在此處再次重複其細節。然而,半導體裝置400的製造方法不同於半導體裝置300的製造方法。確切地說,第一表面修整層411由不同材料製成。在一個實施例中,第一表面修整層411由銅(Cu)而不是銀(Ag)製成。
如圖9A中所說明,在形成及固化第二樹脂層123以及研磨及/或蝕刻第二樹脂層123的步驟之後,第二表面修整層224可進一步形成於暴露於第二樹脂層123外部的凸塊墊122上或連接到所述凸塊墊122。在一個實施例中,第二表面修整層224可如先前所描述而製成且可包括鎳/金(Ni/Au)、銀(Ag)、錫(Sn)及其等效物中的一或多者,但本實施例的方
面不限於此。
如圖9B中所說明,在移除載體170之後,提供可路由的模制引線框架101,其包含具有以下各者的引線框架101:通過第一層壓層110暴露於外部的第一表面修整層411(如上文所描述,其還充當傳導圖案);以及通過第二層壓層120暴露於外部的第二表面修整層224。根據本實施例,第一表面修整層411在可路由的模制引線框架101的製造過程的初始階段形成,且第二表面修整層224在可路由的模制引線框架101的製造過程的最後階段形成。
如圖9C中所說明,半導體晶粒130定位於可路由的模制引線框架101上且由傳導凸塊結構(例如,微凸塊435)電連接到由銅(Cu)製成的第一表面修整層411。更具體地說,在可路由的模制引線框架101中,半導體晶粒130以倒裝晶片型配置連接到第一層壓層110的第一表面修整層411。在一些實施例中,半導體晶粒130及微凸塊435使用如先前所描述的囊封物150加以囊封。
在一些實施例中,傳導凸塊並不分離地形成於凸塊墊122上,且先前形成的第二表面修整層224暴露於外部。因此,本實施例提供倒裝晶片可路由的模制引線框架柵格陣列封裝。在一替代性實施例中,傳導凸塊還可形成於第二表面修整層224上。
根據所有上述內容,所屬技術領域中具有通常知識者可確定,根據一個實施例,半導體裝置包含:第一層壓層,其包含第一表面修整層、連接到第一表面修整層或與第一表面修整層隔開的第一傳導圖案、形成於第一傳導圖案上的導通孔,及覆蓋第一表面修整層、第一傳導圖案
及導通孔的第一樹脂層;第二層壓層,其包含形成於導通孔中的第二傳導圖案、形成於第二傳導圖案上的凸塊墊,及覆蓋第一樹脂層、第二傳導圖案及凸塊墊的第二樹脂層;半導體晶粒,其連接到第一層壓層的第一表面修整層;及囊封物,其覆蓋第一層壓層及半導體晶粒。
根據所有上述內容,所屬技術領域中具有通常知識者可確定,根據另一實施例,半導體裝置的製造方法包含:在載體上形成第一表面修整層;在載體及第一表面修整層中的每一者上形成第一傳導圖案;在第一傳導圖案上形成導通孔且在載體、第一表面修整層、第一傳導圖案及導通孔上塗布第一樹脂層;在導通孔上形成第二傳導圖案及凸塊墊且在第一樹脂層、第二傳導圖案及凸塊墊上塗布第二樹脂層;從第一表面修整層、第一傳導圖案及第一樹脂層移除載體;以及將半導體晶粒連接到第一表面修整層且使用囊封物囊封半導體晶粒。
根據所有上述內容,所屬技術領域中具有通常知識者可確定,根據另一實施例,經封裝半導體裝置可進一步包括連接到第二傳導結構且暴露於第二樹脂層外部的第二表面修整層,其中第一表面修整層包括鎳/金(Ni/Au)、銀(Ag)或銅(Cu)中的一或多者;且第二表面修整層包括鎳/金(Ni/Au)、銀(Ag)或錫(Sn)中的一或多者。在經封裝半導體裝置的另一實施例中,半導體晶粒可通過傳導凸塊以倒裝晶片配置電耦合到第一表面修整層。在經封裝半導體裝置的又一實施例中,半導體晶粒附接到可路由囊封的傳導基板且通過連接線電耦合到第一表面修整層。
根據所有上述內容,所屬技術領域中具有通常知識者可確定,根據另一實施例,在製造具有可路由囊封的傳導基板的半導體裝置的
方法中,提供可路由囊封的傳導基板可包括提供包括銅的第一表面修整層;且電耦合半導體晶粒可包括以倒裝晶片配置與傳導凸塊耦合。在另一實施例中,電耦合半導體晶粒可包括以倒裝晶片配置與傳導凸塊耦合。
鑒於所有上述內容,顯而易見,已揭示製造使用可路由囊封的傳導基板以及結構的半導體封裝的新穎方法。包含可路由囊封的傳導基板以及其它特徵包含囊封在第一樹脂層內的第一傳導結構、囊封在第二樹脂層內的第二傳導結構,及安置在第一傳導結構的至少部分上的表面修整層。表面修整層暴露在第一樹脂層中,第一傳導結構電連接到第二傳導結構,且第二傳導結構的至少部分暴露於第二樹脂層外部。半導體晶粒電耦合到表面修整層,且囊封物覆蓋半導體晶粒及第一表面修整層。可路由囊封的傳導基板促進封裝級嵌入式傳導圖案的有效路由,且表面修整層在可路由囊封的傳導基板與半導體晶粒之間提供增強的連接可靠性。另外,可路由囊封的傳導基板支援對小型化及較高性能的電子裝置的需求,針對組裝的下一級支持各種互連方案,可在進一步組裝步驟之前製造以縮短製造週期時間,可容易地併入到製造流程中,且具成本效益。
雖然已特定地參考本發明的示例性實施例展示且描述了本發明,但所屬技術領域中具有通常知識者將理解,可進行形式及細節上的多種改變,而不脫離所附申請專利範圍第書所界定的本發明的精神及範圍。
如所附申請專利範圍第書所反映,本發明的方面可在於單個前述揭示的實施例的不到全部的特徵。因此,所附申請專利範圍在此明確地併入到此具體實施方式中,其中每一申請專利範圍本身獨立地作為本發明的單獨實施例。此外,雖然本文中所描述的一些實施例包含其它實施例
中所包含的一些但非全部其它特徵,但如所屬技術領域中具有通常知識者將理解,不同實施例的特徵的組合意圖在本發明的範圍內且意圖形成不同的實施例。
100:半導體裝置
101:可路由囊封的傳導基板/可路由的模制引線框架
110:第一層壓層/第一囊封層
111:第一表面修整層/第一接合層/第一可線接合修整層
112:第一傳導圖案
113:導通孔/傳導導通孔/傳導柱
114:第一樹脂層
120:第二層壓層/第二囊封層
121:第二傳導圖案
122:凸塊墊
123:第二樹脂層
130:半導體晶粒
135:黏著劑
140:傳導連接結構/導線
150:囊封物
160:傳導凸塊
Claims (12)
- 一種半導體裝置,其包括:第一層壓層,其包括:第一表面修整層;多個第一傳導圖案,其包括連接到所述第一表面修整層的多個第一部分及與所述多個第一部分側向地隔開的多個第二部分,其中所述多個第二部分沒有所述第一表面修整層;多個傳導導通孔,其連接到所述多個第一傳導圖案的所述多個第一部分;及第一樹脂層,其覆蓋所述多個第一傳導圖案、所述多個傳導導通孔及所述第一表面修整層的一部分,其中所述第一表面修整層暴露在所述第一樹脂層的第一表面中且所述多個傳導導通孔暴露在所述第一樹脂層的第二表面中;第二層壓層,其鄰近於所述第一層壓層且包括:多個第二傳導圖案,其連接到所述多個傳導導通孔;多個傳導墊,其連接到所述多個第二傳導圖案;及第二樹脂層,其覆蓋所述第一樹脂層、所述多個第二傳導圖案及所述多個傳導墊的至少一部分,其中所述多個傳導墊暴露在所述第二樹脂層的第一表面中;半導體晶粒,其電耦合到所述第一表面修整層;及囊封物,其覆蓋所述第一層壓層及所述半導體晶粒的至少一部分。
- 根據申請專利範圍第1項所述的半導體裝置,其中: 所述多個傳導墊的多個表面在所述第二樹脂層中的多個開口內凹陷;且所述半導體裝置進一步包括連接到所述多個傳導墊的多個傳導凸塊。
- 根據申請專利範圍第1項所述的半導體裝置,其中:所述第一表面修整層包括鎳/金(Ni/Au)、銀(Ag)或銅(Cu)中的一或多者;所述第一表面修整層及所述半導體晶粒由導線電耦合;所述半導體裝置進一步包括連接到所述多個傳導墊的第二表面修整層;且所述第二表面修整層包括鎳/金(Ni/Au)、銀(Ag)或錫(Sn)中的一或多者。
- 根據申請專利範圍第1項所述的半導體裝置,其中:所述第一表面修整層包括銅(Cu);且所述第一表面修整層及所述半導體晶粒由多個傳導凸塊電耦合;且所述第一樹脂層、所述第二樹脂層及所述囊封物包括模制化合物材料。
- 根據申請專利範圍第1項所述的半導體裝置,其中:所述第一樹脂層、所述第二樹脂層及所述囊封物包括具有相似熱膨脹係數的多個模制化合物材料;所述第一表面修整層基本上與所述第一樹脂層共面;且所述第一傳導圖案的所述第二部分的表面在所述第一樹脂層的所述第一表面下方凹陷。
- 一種經封裝半導體裝置,其包括: 可路由囊封的傳導基板,其包括:第一傳導結構,其囊封在第一樹脂層內;第二傳導結構,其電耦合到所述第一傳導結構且囊封在第二樹脂層內;及第一表面修整層,其安置在所述第一傳導結構的至少部分上,其中:所述第一表面修整層暴露在所述第一樹脂層中;且所述第二傳導結構的至少部分暴露在所述第二樹脂層中;半導體晶粒,其電耦合到所述第一表面修整層;及囊封物,其囊封所述半導體晶粒及所述第一表面修整層。
- 根據申請專利範圍第6項所述的經封裝半導體裝置,其中:所述第一傳導結構包括連接到第一傳導圖案的多個傳導導通孔;所述第二傳導結構包括連接到傳導凸塊的第二傳導圖案;且所述第一表面修整層連接到所述第一傳導圖案的至少部分。
- 根據申請專利範圍第6項所述的經封裝半導體裝置,其中:所述第一傳導結構包括多個傳導導通孔;所述第一表面修整層經配置為第一傳導圖案;所述第一傳導圖案的至少一部分連接到所述多個傳導導通孔;所述第一表面修整層包括銀(Ag)或銅(Cu)中的一或多者;且所述經封裝半導體裝置進一步包括連接到所述第二傳導結構的多個傳導凸塊。
- 一種製造具有可路由囊封的傳導基板的半導體裝置的方法,其包括: 提供包括以下各者的所述可路由囊封的傳導基板:第一傳導結構,其囊封在第一樹脂層內;第二傳導結構,其電耦合到所述第一傳導結構且囊封在第二樹脂層內;及第一表面修整層,其安置在所述第一傳導結構的至少部分上,其中:所述第一表面修整層暴露在所述第一樹脂層中;且所述第二傳導結構的至少部分暴露在所述第二樹脂層中;將半導體晶粒電耦合到所述第一表面修整層;及形成覆蓋所述半導體晶粒及所述第一表面修整層的囊封物。
- 根據申請專利範圍第9項所述的方法,其中提供所述可路由囊封的傳導基板包括:在載體上提供所述第一表面修整層;提供在所述載體及所述第一表面修整層中的每一者上包括多個第一傳導圖案且在所述多個第一傳導圖案的至少部分上包括多個傳導導通孔的所述第一傳導結構;提供覆蓋所述載體、所述第一表面修整層、所述多個第一傳導圖案及所述多個傳導導通孔的所述第一樹脂層;提供包括連接到所述多個傳導導通孔的多個第二傳導圖案及多個傳導墊的所述第二傳導結構;提供覆蓋所述第一樹脂層、所述多個第二傳導圖案及所述多個傳導墊的所述第二樹脂層;及移除所述載體。
- 根據申請專利範圍第10項所述的方法,其進一步包括:在提供所述第二傳導結構之前移除所述第一樹脂層的一部分以將所述多個傳導導通孔暴露於外部;及將多個傳導凸塊連接到所述多個傳導墊,其中:所述第一表面修整層包括鎳/金(Ni/Au)、銀(Ag)或銅(Cu)中的一或多者;在橫截面圖中所述多個第一傳導圖案的至少部分的多個表面在所述第一樹脂層的主表面下方凹陷;且所述第一表面修整層基本上與所述第一樹脂層的所述主表面共面。
- 根據申請專利範圍第10項所述的方法,其進一步包括:移除所述第二樹脂層的一部分以將所述多個傳導墊暴露於外部;及形成連接到所述多個傳導墊的第二表面修整層,其中:所述第二表面修整層包括鎳/金(Ni/Au)、銀(Ag)或錫(Sn)中的一或多者;且所述第二表面修整層基本上與所述第二樹脂層的主表面共面。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2015-0126935 | 2015-09-08 | ||
KR1020150126935A KR101706470B1 (ko) | 2015-09-08 | 2015-09-08 | 표면 마감층을 갖는 반도체 디바이스 및 그 제조 방법 |
US15/173,379 US10049954B2 (en) | 2015-09-08 | 2016-06-03 | Semiconductor package having routable encapsulated conductive substrate and method |
US15/173,379 | 2016-06-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201711144A TW201711144A (zh) | 2017-03-16 |
TWI706519B true TWI706519B (zh) | 2020-10-01 |
Family
ID=58121096
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW105119098A TWI706519B (zh) | 2015-09-08 | 2016-06-17 | 具有可路由囊封的傳導基板的半導體封裝及方法 |
Country Status (4)
Country | Link |
---|---|
US (4) | US10049954B2 (zh) |
KR (1) | KR101706470B1 (zh) |
CN (3) | CN206059367U (zh) |
TW (1) | TWI706519B (zh) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9418928B2 (en) | 2014-01-06 | 2016-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protrusion bump pads for bond-on-trace processing |
US9275967B2 (en) * | 2014-01-06 | 2016-03-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protrusion bump pads for bond-on-trace processing |
KR102117477B1 (ko) * | 2015-04-23 | 2020-06-01 | 삼성전기주식회사 | 반도체 패키지 및 반도체 패키지의 제조방법 |
KR101706470B1 (ko) * | 2015-09-08 | 2017-02-14 | 앰코 테크놀로지 코리아 주식회사 | 표면 마감층을 갖는 반도체 디바이스 및 그 제조 방법 |
US10236245B2 (en) * | 2016-03-23 | 2019-03-19 | Dyi-chung Hu | Package substrate with embedded circuit |
US10446515B2 (en) * | 2017-03-06 | 2019-10-15 | Advanced Semiconductor Engineering, Inc. | Semiconductor substrate and semiconductor packaging device, and method for forming the same |
US10325868B2 (en) * | 2017-04-24 | 2019-06-18 | Advanced Semiconductor Engineering, Inc. | Semiconductor package device and method of manufacturing the same |
JP6964477B2 (ja) * | 2017-09-20 | 2021-11-10 | 新光電気工業株式会社 | 半導体素子用基板及びその製造方法、半導体装置及びその製造方法 |
US11021786B2 (en) * | 2018-12-04 | 2021-06-01 | Texas Instruments Incorporated | Copper passivation |
US11637057B2 (en) * | 2019-01-07 | 2023-04-25 | Qualcomm Incorporated | Uniform via pad structure having covered traces between partially covered pads |
US11616006B2 (en) * | 2019-02-27 | 2023-03-28 | Semiconductor Components Industries, Llc | Semiconductor package with heatsink |
JP7271337B2 (ja) * | 2019-06-27 | 2023-05-11 | 新光電気工業株式会社 | 電子部品装置及び電子部品装置の製造方法 |
DE102019117789B4 (de) * | 2019-07-02 | 2023-06-01 | Infineon Technologies Ag | Halbleitervorrichtung mit galvanisch isolierten Halbleiterchips |
US11081472B2 (en) * | 2019-09-18 | 2021-08-03 | Texas Instruments Incorporated | Stacked die multichip module package |
CN112701055B (zh) * | 2020-12-22 | 2022-04-22 | 杰群电子科技(东莞)有限公司 | 一种埋置元件的封装方法及封装结构 |
WO2022178806A1 (en) * | 2021-02-26 | 2022-09-01 | Yangtze Memory Technologies Co., Ltd. | Semiconductor package structure and packaging method thereof |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7256495B2 (en) * | 2003-02-24 | 2007-08-14 | Samsung Electro-Mechanics Co., Ltd. | Package substrate manufactured using electrolytic leadless plating process, and method for manufacturing the same |
US7317245B1 (en) * | 2006-04-07 | 2008-01-08 | Amkor Technology, Inc. | Method for manufacturing a semiconductor device substrate |
US7435680B2 (en) * | 2004-12-01 | 2008-10-14 | Shinko Electric Industries Co., Ltd. | Method of manufacturing a circuit substrate and method of manufacturing an electronic parts packaging structure |
TW201236228A (en) * | 2011-02-18 | 2012-09-01 | Bridge Semiconductor Corp | Semiconductor chip assembly with post/base/post heat spreader and asymmetric posts |
TW201314804A (zh) * | 2011-09-21 | 2013-04-01 | Stats Chippac Ltd | 半導體裝置以及形成用於傳導互連結構之保護和支撐結構之方法 |
US8716873B2 (en) * | 2010-07-01 | 2014-05-06 | United Test And Assembly Center Ltd. | Semiconductor packages and methods of packaging semiconductor devices |
TW201445653A (zh) * | 2013-03-14 | 2014-12-01 | United Test & Assembly Ct Lt | 半導體封裝及封裝半導體裝置之方法 |
TW201501226A (zh) * | 2013-03-14 | 2015-01-01 | United Test & Assembly Ct Lt | 半導體封裝及封裝半導體裝置之方法 |
Family Cites Families (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100335658B1 (ko) * | 2000-07-25 | 2002-05-06 | 장석규 | 플라스틱 패캐지의 베이스 및 그 제조방법 |
JP3492348B2 (ja) * | 2001-12-26 | 2004-02-03 | 新光電気工業株式会社 | 半導体装置用パッケージの製造方法 |
JP2003309241A (ja) | 2002-04-15 | 2003-10-31 | Dainippon Printing Co Ltd | リードフレーム部材とリードフレーム部材の製造方法、及び該リードフレーム部材を用いた半導体パッケージとその製造方法 |
WO2005024912A2 (en) * | 2003-09-09 | 2005-03-17 | Intel Corporation | Methods of processing thick ild layers using spray coating or lamination for c4 wafer level thick metal integrated flow |
JP2007194436A (ja) * | 2006-01-19 | 2007-08-02 | Elpida Memory Inc | 半導体パッケージ、導電性ポスト付き基板、積層型半導体装置、半導体パッケージの製造方法及び積層型半導体装置の製造方法 |
US7911038B2 (en) * | 2006-06-30 | 2011-03-22 | Renesas Electronics Corporation | Wiring board, semiconductor device using wiring board and their manufacturing methods |
US20080079127A1 (en) * | 2006-10-03 | 2008-04-03 | Texas Instruments Incorporated | Pin Array No Lead Package and Assembly Method Thereof |
JP5101169B2 (ja) * | 2007-05-30 | 2012-12-19 | 新光電気工業株式会社 | 配線基板とその製造方法 |
KR101204092B1 (ko) | 2008-05-16 | 2012-11-22 | 삼성테크윈 주식회사 | 리드 프레임 및 이를 구비한 반도체 패키지와 그 제조방법 |
JP5231340B2 (ja) * | 2009-06-11 | 2013-07-10 | 新光電気工業株式会社 | 配線基板の製造方法 |
JP2012049250A (ja) | 2010-08-25 | 2012-03-08 | Ngk Spark Plug Co Ltd | 配線基板の製造方法 |
US9006580B2 (en) * | 2011-06-09 | 2015-04-14 | Ngk Spark Plug Co., Ltd. | Method of manufacturing multilayer wiring substrate, and multilayer wiring substrate |
KR101434003B1 (ko) * | 2011-07-07 | 2014-08-27 | 삼성전기주식회사 | 반도체 패키지 및 그 제조 방법 |
TWI475935B (zh) * | 2011-07-08 | 2015-03-01 | Unimicron Technology Corp | 無核心層之封裝基板及其製法 |
US9312214B2 (en) * | 2011-09-22 | 2016-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages having polymer-containing substrates and methods of forming same |
TWI557855B (zh) * | 2011-12-30 | 2016-11-11 | 旭德科技股份有限公司 | 封裝載板及其製作方法 |
CN104112673B (zh) * | 2013-04-19 | 2017-06-23 | 碁鼎科技秦皇岛有限公司 | 芯片封装基板及其制作方法 |
JP2014236102A (ja) * | 2013-05-31 | 2014-12-15 | 凸版印刷株式会社 | 貫通電極付き配線基板、その製造方法及び半導体装置 |
CN107170689B (zh) * | 2013-06-11 | 2019-12-31 | 唐山国芯晶源电子有限公司 | 芯片封装基板 |
US9418928B2 (en) * | 2014-01-06 | 2016-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protrusion bump pads for bond-on-trace processing |
CN105097758B (zh) * | 2014-05-05 | 2018-10-26 | 日月光半导体制造股份有限公司 | 衬底、其半导体封装及其制造方法 |
KR102254874B1 (ko) * | 2014-05-30 | 2021-05-24 | 삼성전기주식회사 | 패키지 기판 및 패키지 기판 제조 방법 |
TWI581386B (zh) * | 2014-06-16 | 2017-05-01 | 恆勁科技股份有限公司 | 封裝裝置及其製作方法 |
TWI474417B (zh) * | 2014-06-16 | 2015-02-21 | Phoenix Pioneer Technology Co Ltd | 封裝方法 |
TWI655727B (zh) * | 2014-06-17 | 2019-04-01 | 恆勁科技股份有限公司 | 封裝基板及包含該封裝基板的覆晶封裝電路 |
CN204088305U (zh) * | 2014-06-30 | 2015-01-07 | 江苏长电科技股份有限公司 | 新型高密度可堆叠封装结构 |
JP2016051834A (ja) * | 2014-09-01 | 2016-04-11 | イビデン株式会社 | プリント配線基板およびその製造方法 |
TWI582861B (zh) * | 2014-09-12 | 2017-05-11 | 矽品精密工業股份有限公司 | 嵌埋元件之封裝結構及其製法 |
KR102194722B1 (ko) * | 2014-09-17 | 2020-12-23 | 삼성전기주식회사 | 패키지 기판, 패키지 기판의 제조 방법 및 이를 포함하는 적층형 패키지 |
TWI570816B (zh) * | 2014-09-26 | 2017-02-11 | 矽品精密工業股份有限公司 | 封裝結構及其製法 |
CN105931997B (zh) * | 2015-02-27 | 2019-02-05 | 胡迪群 | 暂时性复合式载板 |
US9589920B2 (en) * | 2015-07-01 | 2017-03-07 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. | Chip package |
KR101706470B1 (ko) * | 2015-09-08 | 2017-02-14 | 앰코 테크놀로지 코리아 주식회사 | 표면 마감층을 갖는 반도체 디바이스 및 그 제조 방법 |
-
2015
- 2015-09-08 KR KR1020150126935A patent/KR101706470B1/ko active IP Right Grant
-
2016
- 2016-06-03 US US15/173,379 patent/US10049954B2/en active Active
- 2016-06-17 TW TW105119098A patent/TWI706519B/zh active
- 2016-07-19 CN CN201620763639.XU patent/CN206059367U/zh active Active
- 2016-07-19 CN CN201610571284.9A patent/CN106505045B/zh active Active
- 2016-07-19 CN CN202111213887.9A patent/CN113948479A/zh active Pending
-
2018
- 2018-07-11 US US16/032,295 patent/US10685897B2/en active Active
-
2020
- 2020-04-29 US US16/861,405 patent/US11508635B2/en active Active
-
2022
- 2022-11-18 US US17/989,894 patent/US20230083412A1/en active Pending
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7256495B2 (en) * | 2003-02-24 | 2007-08-14 | Samsung Electro-Mechanics Co., Ltd. | Package substrate manufactured using electrolytic leadless plating process, and method for manufacturing the same |
US7435680B2 (en) * | 2004-12-01 | 2008-10-14 | Shinko Electric Industries Co., Ltd. | Method of manufacturing a circuit substrate and method of manufacturing an electronic parts packaging structure |
US7317245B1 (en) * | 2006-04-07 | 2008-01-08 | Amkor Technology, Inc. | Method for manufacturing a semiconductor device substrate |
US8716873B2 (en) * | 2010-07-01 | 2014-05-06 | United Test And Assembly Center Ltd. | Semiconductor packages and methods of packaging semiconductor devices |
TW201236228A (en) * | 2011-02-18 | 2012-09-01 | Bridge Semiconductor Corp | Semiconductor chip assembly with post/base/post heat spreader and asymmetric posts |
TW201314804A (zh) * | 2011-09-21 | 2013-04-01 | Stats Chippac Ltd | 半導體裝置以及形成用於傳導互連結構之保護和支撐結構之方法 |
TW201445653A (zh) * | 2013-03-14 | 2014-12-01 | United Test & Assembly Ct Lt | 半導體封裝及封裝半導體裝置之方法 |
TW201501226A (zh) * | 2013-03-14 | 2015-01-01 | United Test & Assembly Ct Lt | 半導體封裝及封裝半導體裝置之方法 |
Also Published As
Publication number | Publication date |
---|---|
US10685897B2 (en) | 2020-06-16 |
US20180323129A1 (en) | 2018-11-08 |
US10049954B2 (en) | 2018-08-14 |
CN206059367U (zh) | 2017-03-29 |
CN106505045A (zh) | 2017-03-15 |
US20200258803A1 (en) | 2020-08-13 |
US20170069558A1 (en) | 2017-03-09 |
US20230083412A1 (en) | 2023-03-16 |
KR101706470B1 (ko) | 2017-02-14 |
CN113948479A (zh) | 2022-01-18 |
US11508635B2 (en) | 2022-11-22 |
TW201711144A (zh) | 2017-03-16 |
CN106505045B (zh) | 2021-10-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI706519B (zh) | 具有可路由囊封的傳導基板的半導體封裝及方法 | |
US10804232B2 (en) | Semiconductor device with thin redistribution layers | |
US11935856B2 (en) | Semiconductor device having a redistribution layer | |
TWI772672B (zh) | 晶片封裝方法及晶片結構 | |
KR101690549B1 (ko) | 내장 칩 패키지 | |
US8445323B2 (en) | Semiconductor package with semiconductor core structure and method of forming same | |
US8093711B2 (en) | Semiconductor device | |
US20200118993A1 (en) | Semiconductor package and method of manufacturing the semiconductor package | |
US8647924B2 (en) | Semiconductor package and method of packaging semiconductor devices | |
TW201108335A (en) | Semiconductor device and method of forming dam material around periphery of die to reduce warpage | |
KR20180065907A (ko) | 매립된 인덕터 또는 패키지를 갖는 집적 sip 모듈을 형성하는 반도체 소자 및 방법 | |
JP4115326B2 (ja) | 半導体パッケージの製造方法 | |
JP2017017300A (ja) | チップパッケージ | |
KR100959606B1 (ko) | 스택 패키지 및 그의 제조 방법 | |
JP6637769B2 (ja) | 樹脂封止型半導体装置およびその製造方法 | |
US8796867B2 (en) | Semiconductor package and fabrication method thereof | |
TWI512925B (zh) | 焊線結構及形成焊線結構的方法 | |
KR101394647B1 (ko) | 반도체 패키지 및 그 제조방법 | |
TWI712134B (zh) | 半導體裝置及製造方法 | |
KR101807457B1 (ko) | 표면 마감층을 갖는 반도체 디바이스 및 그 제조 방법 | |
US9786515B1 (en) | Semiconductor device package and methods of manufacture thereof | |
TW202013659A (zh) | 電子裝置及其製造方法 | |
TW202349575A (zh) | 半導體裝置和用於先進散熱的方法 |