TW202013659A - 電子裝置及其製造方法 - Google Patents
電子裝置及其製造方法 Download PDFInfo
- Publication number
- TW202013659A TW202013659A TW107144940A TW107144940A TW202013659A TW 202013659 A TW202013659 A TW 202013659A TW 107144940 A TW107144940 A TW 107144940A TW 107144940 A TW107144940 A TW 107144940A TW 202013659 A TW202013659 A TW 202013659A
- Authority
- TW
- Taiwan
- Prior art keywords
- conductor
- layer
- conductive
- semiconductor package
- diffusion barrier
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 168
- 239000004020 conductor Substances 0.000 claims abstract description 147
- 230000004888 barrier function Effects 0.000 claims abstract description 74
- 238000009792 diffusion process Methods 0.000 claims abstract description 69
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 38
- 239000010410 layer Substances 0.000 description 188
- 239000000463 material Substances 0.000 description 69
- 238000000034 method Methods 0.000 description 53
- 229910052751 metal Inorganic materials 0.000 description 52
- 239000002184 metal Substances 0.000 description 52
- 230000008569 process Effects 0.000 description 38
- 239000011810 insulating material Substances 0.000 description 18
- 229920002120 photoresistant polymer Polymers 0.000 description 17
- 229910000679 solder Inorganic materials 0.000 description 16
- 229910000765 intermetallic Inorganic materials 0.000 description 14
- 230000000903 blocking effect Effects 0.000 description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- 239000010949 copper Substances 0.000 description 10
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000011241 protective layer Substances 0.000 description 9
- 238000012360 testing method Methods 0.000 description 6
- 238000009713 electroplating Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 238000009736 wetting Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 239000002131 composite material Substances 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 238000005553 drilling Methods 0.000 description 3
- 230000004907 flux Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000012795 verification Methods 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000004070 electrodeposition Methods 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 229920002577 polybenzoxazole Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000002861 polymer material Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- 229910001152 Bi alloy Inorganic materials 0.000 description 1
- 229910000925 Cd alloy Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910000846 In alloy Inorganic materials 0.000 description 1
- 229910001245 Sb alloy Inorganic materials 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 229910001297 Zn alloy Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1076—Shape of the containers
- H01L2225/1082—Shape of the containers for improving alignment between containers, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
提供一種電子裝置及其製造方法。電子裝置包括半導體晶粒、與半導體晶粒電耦接的導電結構、包封半導體晶粒和導電結構的絕緣包封件以及設置在絕緣包封件上和半導體晶粒的重佈線結構。導電結構包括第一導體、第二導體和在第一導體與第二導體之間的擴散阻擋層。重佈線結構電連接到半導體晶粒和導電結構的第一導體。
Description
本發明的實施例是有關於一種電子裝置及其製造方法,特別是有關於一種包括擴散阻擋層的電子裝置及其製造方法。
半導體裝置用於各種電子應用,如個人電腦、手機、數位照相機等電子裝置。隨著對電子裝置縮小的需求不斷增長,人們開始需要更小及更具創造性的半導體晶粒包裝技術。因此,已經開始開發諸如晶圓級封裝(wafer level packaging,WLP)的封裝,其中積體電路(integrated circuit,IC)被放置在具有連接件的載體上,用於連接到IC和其他電子元件。為了進一步增加電路密度,開發了一些堆疊封裝(package-on-package,POP)結構,其包括整合扇出型封裝件和至少一個堆疊在整合扇出型封裝件上的儲存裝置,並且因其緊湊性而變得越來越流行。隨著對微型化的需求,最近增長更高的速度和更大的頻寬,以及更低的功率消耗和延遲的需求,並已增長對於POP結構的更小和更有創意的封裝技術的需求。
根據一些實施例,電子裝置包括半導體晶粒、電耦接到半導體晶粒的導電結構、包封半導體晶粒和導電結構的絕緣包封件以及設置在絕緣包封件和半導體晶粒上的重佈線結構。導電結構包括第一導體、第二導體和在第一導體與第二導體之間的擴散阻擋層。重佈線結構電連接到半導體晶粒和導電結構的第一導體。
根據一些實施例,提供了一種電子裝置的製造方法。所述方法至少包括以下步驟。形成絕緣包封件以包封多層結構和半導體晶粒,其中多層結構包括第一導體、形成在第一導體上的擴散阻擋層以及形成在擴散阻擋層上的金屬層,絕緣包封件至少暴露出半導體晶粒的一部分和多層結構的第一導體的一部分。重佈線結構形成在絕緣包封件、半導體晶粒和多層結構的第一導體上。移除多層結構的金屬層,以在絕緣包封件中形成凹陷。在擴散阻擋層上的凹陷中形成第二導體,其中第一導體、擴散阻擋層和第二導體形成導電結構,導電結構藉由重佈線結構與半導體晶粒電耦接。
根據一些實施例,提供了一種電子裝置的製造方法。所述方法至少包括以下步驟。提供第一半導體封裝件,其中第一半導體封裝件包括半導體晶粒、電耦合到半導體晶粒的多層導體和側向地包封半導體晶粒和多層導體的絕緣包封件,多層導體包括位於絕緣包封件的兩個相對表面之間的阻擋表面。第二半導體封裝件藉由在多層導體的阻擋表面上形成第二導體而安裝在第一半導體封裝件上,使得第一半導體封裝件和第二半導體封裝件電連接。
以下公開內容提供許多不同的實施例或實例以用於實施本發明的實施例的不同特徵。以下闡述元件及配置形式的具體實例以簡化本公開內容。當然,這些僅為實例而並非旨在進行限制。舉例來說,以下說明中將第一特徵形成在第二特徵“之上”或第二特徵“上”可包括其中第一特徵與第二特徵被形成為直接接觸的實施例,且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外,本公開內容可能在各種實例中重複使用參考編號及/或字母。這種重複使用是出於簡明及清晰的目的,而自身並不表示所論述的各種實施例及/或配置之間的關係。
此外,為易於說明,本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。設備可具有其他取向(例如,旋轉90度或處於其他取向)且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
另外,為易於說明,本文中可能使用例如“第一”、“第二”等用語來闡述圖中所示出的相似或不同的元件或特徵且可依據存在的次序或說明的上下文而互換地使用。
其他特徵和製程也可能包括在內。例如可以包括測試結構以説明3D包裝或3DIC裝置的驗證測試。測試結構可以包括,例如形成在重佈線層中或基底上的測試接墊,其允許測試3D封裝或3DIC,探針及/或探針卡的使用等。驗證測試可以在中間結構以及最終結構上進行。另外,本文公開的結構和方法可以與包含已知良好晶粒的中間驗證的測試方法結合使用,以增加良率並降低成本。
圖1A至圖1N是根據本公開的一些示例性實施例的電子裝置的製造方法中的各種階段的示意剖面圖。參照圖1A,可以使用物理氣相沉積(例如濺鍍、電鍍或蒸發等)、化學氣相沉積或其他合適的製程在臨時載體50上形成晶種材料SD’。在一些實施例中,晶種材料SD’是導電層,其可以是單層或複合層,複合層包括由不同材料形成的若干子層。舉例來說,晶種材料SD’包括鈦層和在所述鈦層上的銅層。在一些實施例中,臨時載體50可包括可在半導體加工期間提供結構支撐的任何合適的材料。舉例來說,臨時載體50的材料包括金屬(例如鋼)、玻璃、陶瓷、矽(例如塊狀矽)、其組合、其多層等。在一些實施例中,在形成晶種材料SD’之前,可以在臨時載體50上形成離型層52。離型層52的材料可以是任何適於將臨時載體50與形成在其上的結構接合和剝離的材料。舉例來說,離型層52包括光熱轉換層(light-to-heat-conversion,LTHC)離型塗佈層和相關的黏合層(例如紫外線可固化的黏合層或可熱固化黏合層)或類似物。
參照圖1B至圖1D,金屬層M1、擴散阻擋層110和第一導體120可以依序地形成在晶種材料SD’上。舉例來說,參照圖1B,一旦形成了晶種材料SD’,就可以在晶種材料SD’上形成圖案化的光阻層PR。圖案化的光阻層PR可包括由聚合物材料形成的乾式膜光阻。舉例來說,圖案化的光阻層PR是藉由在晶種材料SD’上沉積或層壓光阻材料而形成的,然後可以使用諸如微影(即曝光和顯影製程)或其他合適的技術將光阻材料圖案化,以形成圖案化的光阻層PR。在一些實施例中,圖案化的光阻層PR覆蓋了晶種材料SD’的一部分,並且圖案化的光阻層PR包括多個開口OP,開口OP暴露了晶種材料SD'的其他預定部分。在一些實施例中,在形成圖案化的光阻層PR之後,藉由沉積或其他合適的技術,金屬層M1在圖案化的光阻層PR的開口OP中形成,以與晶種材料SD’物理接觸。舉例來說,其上形成有晶種材料SD’和圖案化的光阻層PR的臨時載體50可以浸入電鍍浴的電鍍液中,這樣一來,在由圖案化的光阻層PR的開口OP顯露的晶種材料SD’的預定部分上電鍍金屬材料,從而形成金屬層M1。金屬層M1的材料可包括銅、銀、金、鋁、其合金或其他合適的導電材料。電鍍可以在較低的電流密度下進行,從而形成具有更均勻的高度的金屬層M1。在一些實施例中,為了形成金屬層M1,電鍍在約為1 ASD至20 ASD的電流密度下進行。
繼續參照圖1C,在形成金屬層M1之後,可以將擴散阻擋層110沉積在圖案化的光阻層PR的開口OP中,以與金屬層M1物理接觸。在一些實施例中,擴散阻擋層110可以在回焊(reflow)溫度下與焊料材料具有良好的濕潤性(wettability)。可以由在隨後的製程中而形成的可靠的金屬間化合物(intermetallic compound,IMC)介面的材料來形成擴散阻擋層110,稍後將結合附圖詳細描述。在一些實施例中,擴散阻擋層110可包括在回焊溫度下可濕潤或溶解到焊料中的材料。擴散阻擋層110可以是單層或複合層,複合層包括由不同材料形成的多重子層。舉例來說,擴散阻擋層110的材料包括金屬或金屬合金,例如鎳、鈷、金、鈀、鉑或其合金等。在一些實施例中,在某些蝕刻溶液(例如H2
SO4
+H2
O2
+H2
O)中,擴散阻擋層110的蝕刻速率可低於銅的蝕刻速率。
繼續參照圖1D,第一導體120可以形成在圖案化的光阻層PR的開口OP中,以與擴散阻擋層110物理接觸。第一導體120的材料可包括金屬或金屬合金,例如銅、銀、金、鋁或其合金。在一些實施例中,第一導體120的電沉積在比金屬層M1的電沉積操作更高的電流密度下操作。舉例來說,第一導體120的電鍍可以在約10 ASD至約60 ASD範圍的電流密度下完成。
參照圖1E,在形成第一導體120之後,藉由剝離製程(例如蝕刻或其他合適的去除技術)去除圖案化的光阻層PR。此後,藉由使用在晶種材料SD’上形成的結構(例如金屬層M1/擴散阻擋層110/第一導體120)作為硬質光罩,未被這種結構覆蓋的晶種材料SD’的部分藉由蝕刻製程或其它合適的技術去除,使得金屬層M1下面的晶種材料SD’的剩餘部分被保留在臨時載體50上,以形成晶種層SD。在一些實施例中,在去除部分晶種材料SD’之後,晶種層SD、金屬層M1、擴散阻擋層110、第一導體120被統稱為多層結構100A。應注意,圖1E中所示的多層結構100A的數量僅用作示例性說明,本公開不限於此。
參照圖1F,在一些實施例中,在形成多層結構100A之後,可以提供半導體晶粒200並將其設置在臨時載體50上。舉例來說,半導體晶粒200被拾取、放置並藉由晶粒貼附材料60附著在臨時載體50上。半導體晶粒200可以包括數位晶粒(digital die)、類比晶粒(analog die)或混合訊號晶粒,如感測器晶粒或邏輯晶粒(例如應用積體電路(application-specific integrated circuit,ASIC)或系統級晶片(System-on-Chip,SoC)等),但不限於此。應注意,基於說明目的,圖1F僅示出一個半導體晶粒200。然而,應當理解,根據產品要求,半導體晶粒200的數量可以多於一個,本公開不限於此。在一些實施例中,放置在臨時載體50上的半導體晶粒200可以佈置成陣列,並且多個多層結構100A可以圍繞半導體晶粒200。舉例來說,多個多層結構100A可以被分類為群組,並且半導體晶粒200的數量對應於多層結構100A的群組的數量。
在一些實施例中,半導體晶粒200藉由前段(front end of line,FEOL)製程製造,但不限於此。舉例來說,半導體晶粒200包括半導體基板210、多個連接墊220、多個連接柱230和保護層240。半導體基板210可以是矽基底,其包括形成在其中的主動元件(例如二極體、電晶體等)和被動元件(例如電阻器、電容器、電感器等)。連接墊220可以由鋁或其合金等製成。在一些實施例中,連接柱230分別設置在連接墊220上並且電連接到連接墊220,其中連接柱230物理地接觸連接墊220。連接柱230可包括銅柱、銅合金柱或其他合適的金屬柱。連接柱230可包括基於鉛的材料或無鉛材料,在頂部形成或不形成附加雜質,但不限於此。
在一些實施例中,保護層240覆蓋連接墊220和連接柱230。也就是說,保護層240防止在半導體晶粒200的移轉期間在連接柱230的表面上發生的任何可能的損壞。保護層240可以由聚苯並惡唑(polybenzoxazole,PBO),聚酰亞胺(polyimide,PI)或合適的聚合物或無機材料製成。連接墊220和連接柱230的數量可以根據需要選擇,本公開不限於此。應當理解,在所有圖中半導體晶粒200和其他元件的圖示是示意性的並且不是按比例的。在一些實施例中,晶粒貼附材料60可以接合到半導體晶粒200的後表面上,該後表面與連接柱230分佈的一側相對。舉例來說,晶粒貼附材料60可以是晶粒附著膜(die attached film,DAF)、黏合膜(adhesive bonding film,ABF)等。晶粒貼附材料60可用其他與半導體加工環境相容的合適的黏合材料。
繼續參照圖1F,在設置半導體晶粒200之後,可以在臨時載體50上形成絕緣材料300’。在一些實施例中,絕緣材料300’是由模塑成型製程形成的模塑化合物。舉例來說,包覆成型絕緣材料300’,以包封多層結構100A、半導體晶粒200和晶粒貼附材料60。換句話說,半導體晶粒200的多層結構100A和保護層240未被絕緣材料300’顯露並且被絕緣材料300’良好保護。絕緣材料300’可包括環氧樹脂或其他合適的介電材料。
參照圖1G,可以減小絕緣材料300’的厚度,以露出多層結構100A的第一導體120的至少一部分和半導體晶粒200的連接柱230的部分。舉例來說,研磨絕緣材料300’,直到露出多層結構100A的頂面、連接柱230的頂面和保護層240的頂面。在一些實施例中,絕緣材料300’藉由機械研磨製程及/或化學機械拋光(chemical mechanical polishing,CMP)製程研磨。在一些實施例中,在研磨製程期間,不僅絕緣材料300’,而且保護層240及/或連接柱230及/或多層結構100A的第一導體120的部分被略微研磨。在減小絕緣材料300’的厚度之後,在臨時載體50上形成具有第一表面S1和與第一表面S1相對的第二表面S2的絕緣包封件300。在一些實施例中,絕緣包封件300面向臨時載體50的第二表面S2與離型層52接觸。如圖1G所示,絕緣包封件300側向地包封半導體晶粒200的側壁和多層結構100A的側壁,並且絕緣包封件300被多層結構100A穿透。在一些實施例中,多層結構100A的頂面、絕緣包封件300的第一表面S1與半導體晶粒200的連接柱230的頂面實質上共面。在其他實施例中,由於研磨速率的差異,多層結構100A的頂面、絕緣包封件300的第一表面S1與半導體晶粒200的連接柱230的頂面可能不共面。
在一些替代實施例中,可以在形成絕緣材料300’之後形成多層結構100A。舉例來說,半導體晶粒200藉由晶粒貼附材料60附著在臨時載體50上,然後在臨時載體50上形成絕緣材料300’以包封半導體晶粒200和晶粒貼附材料60。接下來,可以在絕緣材料300’上執行鑽孔製程(例如雷射鑽孔、機械鑽孔或其他合適的製程),以在絕緣材料300’中形成孔。隨後,晶種層SD、金屬層M1、擴散阻擋層110和第一導體120可以依序地填充在絕緣材料300’的孔中。絕緣材料300’、第一導體120和半導體晶粒200可以進一步地被平坦化,以形成絕緣包封件300和多層結構100A。
參照圖1H,在形成絕緣包封件300之後,可以在絕緣包封件300、半導體晶粒200和多層結構100A的第一導體120上形成重佈線結構400。舉例來說,電連接到半導體晶粒200的連接柱230和第一導體120的重佈線結構400被形成在第一導體120的頂面、絕緣包封件300的第一表面S1、連接柱230的頂面和保護層240的頂面上。在一些實施例中,由於連接到半導體晶粒200的重佈線結構400重新路由半導體晶粒200的電訊號,並且比半導體晶粒200的尺寸擴展得更寬,所以重佈線結構400可以被稱為扇出(fan-out)重佈線結構。
在一些實施例中,重佈線結構400包括交替堆疊的多個圖案化的介電層410和多個圖案化的導電層420,並且圖案化的導電層420電連接到半導體晶粒200的連接柱230和嵌入絕緣包封件300中的多層結構100A。連接柱230的頂面和多層結構100A的第一導體120的頂面被最底部的圖案化的介電層410部分地覆蓋。在一些實施例中,最外層的圖案化的導電層420可以包括多個接墊,並且這些接墊可以在隨後的植球(ball mounting)製程中用作為凸塊下金屬(under-ball metallurgy,UBM)接墊。應注意,UBM接墊的數量在本公開中不受限制。
參考圖1I,可以在重佈線結構400上形成多個導電端子500。舉例來說,導電端子500設置在最外層的圖案化的導電層420的暴露的頂面上。在一些實施例中,導電端子500是放置在最外層的圖案化的導電層420的UBM接墊上的焊球或球柵陣列(ball grid array,BGA)。可選擇性地執行回焊(reflow)製程以增強導電端子500和重佈線結構400之間的黏合。在一些實施例中,藉由重佈線結構400,一些導電端子500與半導體晶粒200和多層結構100A電連接。在一些其他實施例中,被動半導體元件(未示出)可以安裝到最外層的圖案化的介電層410上,並電連接到最外面的圖案化的導電層420,並且根據產品要求,被動半導體元件被導電端子500圍繞。
參照圖1J,在一些實施例中,在形成導電端子500之後,移除臨時載體50和離型層52以露出絕緣包封件300的第二表面S2。舉例來說,臨時載體50藉由剝離製程與絕緣包封件300、多層結構100A和晶粒貼附材料60分離。在一些實施例中,可以將諸如UV雷射、可見光線或熱量的外部能量施加到離型層52,使得可以去除臨時載體50。在一些實施例中,當對臨時載體50進行剝離時,多層結構100A的晶種層SD可以與離型層52一起被去除,以暴露出金屬層M1。在一些實施例中,結構可以被翻轉(例如上下顛倒)並且放置在載具70上,以執行在絕緣包封件300的第二表面S2上形成的後續製程。舉例來說,在翻轉製程之後,導電端子500設置在載具70上或附接到載具70。根據製程設計要求,可以在臨時載體50的移除製程之前或之後執行翻轉製程。
圖2A和圖2B是根據本公開的一些不同示例性實施例的圖1K中繪示的虛線框A的放大示意剖面圖。參照圖2A、圖2B和圖1K,可以去除多層結構100A的金屬層M1,以在絕緣包封件300中形成凹陷R。在一些實施例中,在去除金屬層M1之後,擴散阻擋層110可以被凹陷R暴露出來。舉例來說,可以回蝕金屬層M1直到露出擴散阻擋層110,因此擴散阻擋層110可以被視為蝕刻停止層。在一些實施例中,在去除金屬層M1之後,結構的剩餘部分(例如包括擴散阻擋層110和第一導體120)可以統稱為多層導體100B。在一些實施例中,多層導體100B的阻擋表面BS被凹陷R暴露出來。舉例來說,阻擋表面BS位於絕緣包封件300的第一表面S1和第二表面S2之間。阻擋表面BS可以實質上平行於絕緣包封件300的第一表面S1及/或第二表面S2。在一些實施例中,在去除金屬層M1之後,可以執行表面清洗製程,以去除凹陷R內的阻擋表面BS上不期望地存在的殘餘物及/或副產物,以確保在阻擋表面BS上形成另外的導電材料是乾淨的,並且由此可以使電阻最小化。在一些實施例中,圖1K中所示的載具70上提供的結構被視為第一半導體封裝件10。
在一些其他實施例中,在去除金屬層M1之後,金屬層M1的一部分含金屬的殘留物RS可以保留在擴散阻擋層110上,如圖2A所示。在某些實施例中,含金屬的殘留物RS可以是含銅的殘留物。含金屬的殘留物RS可以是覆蓋擴散阻擋層110的薄層。舉例來說,金屬層M1的含金屬的殘留物RS的最大厚度範圍約為0.5 μm至5 μm。在一些實施例中,在去除金屬層M1並執行表面清洗製程之後,擴散阻擋層110被暴露出來,其中擴散阻擋層110可以包括多個子層,並且與第一導體120相對的最外面的子層可以由具有良好濕潤性的材料(例如金)製成。在這種實施例中,擴散阻擋層110的最外層子層的表面被視為阻擋表面BS。在其他實施例中,在去除金屬層M1之後,擴散阻擋層110被暴露出來,然後可以在凹陷R內部的擴散阻擋層110的頂部上形成濕潤層WT,以與擴散阻擋層110物理接觸,以獲得更好的濕潤性,如圖2B所示。在這種實施例中,濕潤層WT的表面被視為阻擋表面BS。舉例來說,濕潤層WT的厚度範圍為約0.01 μm至約1 μm。
參照圖1L,導電材料130’可以使用印刷製程、電鍍製程或其他合適的技術形成在凹陷R內的多層導體100B的阻擋表面BS上。舉例來說,具有多個開孔TH的擋版80放置在絕緣包封件300的第二表面S2上。擋版80的開孔TH可以與第一半導體封裝件10的凹陷R實質上對齊。隨後,導電材料130’可以塗覆在藉由擋版80而被暴露出來的多層導體100B的阻擋表面BS上。在一些實施例中,導電材料130’不同於第一導體120的材料。導電材料130’可以是焊料膏及/或助焊劑(flux),其包括銀、錫、鋅、銅、銻、鎘、銦、鉍或其組合等的合金或其他合適的金屬材料。在一些實施例中,在此階段,凹陷R可以不被導電材料130’填充。
參照圖1M,提供第二半導體封裝件20並將其安裝在第一半導體封裝件10上,使得第一半導體封裝件10和第二半導體封裝件20電連接。舉例來說,第二半導體封裝件20可以是具有至少一個半導體晶粒(未示出)的封裝件,其具有大部分配置用於記憶體儲存陣列功能或執行處理器功能等的主動裝置。第二半導體封裝件20中的半導體晶粒可以是記憶體晶片(例如動態隨機存取記憶體晶片),應用積體電路(ASIC)晶片或具有不同功能的各種組合晶片的形式。在一些實施例中,第二半導體封裝件20包括設置在第二半導體封裝件20的前側S3上的重佈線電路層20A以及連接到重佈線電路層20A的多個導電特徵。第二半導體封裝件20中的半導體晶粒可以藉由重佈線電路層20A電耦合到導電特徵。在第一半導體封裝件10上設置第二半導體封裝件20之後,第二半導體封裝件20的前側S3可面向第一半導體封裝件10。在一些實施例中,第二半導體封裝件20的導電特徵可以與第一半導體封裝件10的凹陷R實質地對齊,以用於接合製程。舉例來說,第二半導體封裝件20的導電特徵的材料包括焊料。
繼續參照圖1M,第二半導體封裝件20的導電特徵和凹陷R中的導電材料130’彼此接合。舉例來說,可以對第二半導體封裝件20及/或導電材料130’的導電特徵進行熱處理製程。在一些實施例中,第二半導體封裝件20的導電特徵及/或導電材料130’可以經受回焊製程,然後導致導電特徵變形為導電接點20B並且導致導電材料130'變形為在第一半導體封裝件10的凹陷R中的第二導體130。回焊製程可以在有或沒有可選的助焊步驟的情況下進行。助焊劑是一種化學清潔劑,其可以防止在回焊製程過程中焊料的氧化,舉例來說,在助焊步驟完成後,然後從第二半導體封裝件20和第一半導體封裝件10之間的空間清除助焊劑。
在一些實施例中,在接合製程之後,由絕緣包封件300側向地包封的導電材料(例如焊料)的一部分可以被視為第一半導體封裝件10的第二導體130,覆蓋在第二導體130上並且在此階段被絕緣包封件300暴露出來的導電材料的另一部分(例如焊料),可以被視為第二半導體封裝件20的導電接點20B。換句話說,第一半導體封裝件10可以包括設置在第一導體120上並被絕緣包封件300側向地包封的第二導體130,並且擴散阻擋層110被夾在第一導體120和第二導體130之間。第二導體130和導電接點20B由相同的材料製成。舉例來說,第二導體130可以比多層導體100B(例如包括擴散阻擋層110和第一導體120)要薄。在一些實施例中,第一導體120、擴散阻擋層110和第二導體130可以共同表示為導電結構100。在一些實施例中,第一導體120、擴散阻擋層110和第二導體130由不同的材料製成。在一些其他實施例中,藉由重佈線結構400電耦合到半導體晶粒200並且被絕緣包封件300包封的導電結構100可以被稱為絕緣通孔(through insulating vias,TIV)或整合扇出(integrated fan-out,InFO)通孔。如上所述的示例性的第一半導體封裝件10可以被稱為整合扇出(InFO)半導體封裝件。
在一些實施例中,由於第二導體130和導電接點20B由相同或相似的材料製成並且在同一製程期間形成,所以實現了第一半導體封裝件10與第二半導體封裝件20之間的更好連接,從而提高了裝置的可靠度。在一些實施例中,由於在回焊製程期間焊接材料的總體積不會變化,所以第二導體130可以填充在凹陷R中,並且由焊接材料的其餘部分形成的相應的導電接點20B可以被擠出比覆蓋第二導體130的凹陷R的寬度還要寬,如圖3的放大圖所示。在一些實施例中,由於焊料的材料特性,導電接點20B可以具有光滑圓形的側壁輪廓。
繼續參照圖1M,在一些實施例中,在接合製程之後,第二導體130與相應的導電接點20B結合具有總直立高度(total standoff height)SH。舉例來說,總直立高度SH是從第一半導體封裝件10內的阻擋表面BS測量到第二半導體封裝件20的前側S3。也就是說,總直立高度SH包括第二導體130的第一直立高度SH1和相應的導電接點20B的第二直立高度SH2。隨著對縮小電子裝置的需求增加,降低總直立高度SH可滿足微型化的要求。舉例來說,第一直立高度SH1與第二直立高度SH2的比例範圍為約0.4至約1.5。一般來說,如果焊料接點太薄(即直立高度較低),半導體封裝件之間的連接則不太穩固而更容易產生裂紋;但是如果焊料接點很厚(即更高的直立高度),則半導體封裝件的整個的厚度會增加。因此,藉由在第一半導體封裝件10的凹陷R中形成第二導體130,第二導體130與相應的導電接點20B的組合可以具有足夠在半導體封裝件之間提供良好連接的總直立高度SH,從而在不損害第一半導體封裝件10和第二半導體封裝件20的整個厚度的情況下實現可靠度。
也就是說,可以藉由縮短第二半導體封裝件20的前側S3與第一半導體封裝件10的絕緣包封件300的第二表面S2之間的間隙,來減小第一半導體封裝件10和第二半導體封裝件20的總厚度,從而滿足微型化的要求。在一些實施例中,絕緣包封件300的厚度T1實質上等於半導體晶粒200和晶粒貼附材料60的總厚度T2。在一些實施例中,絕緣包封件300的厚度T1實質上等於導電結構100的厚度T3。舉例來說,擴散阻擋層110可具有約0.5 μm至5 μm的厚度。擴散阻擋層110的厚度與絕緣包封件300的厚度T1的比例可以在約0.2 %至4 %的範圍內。在一些實施例中,第一導體120的厚度可以大於第二導體130的厚度。第一導體120可以實質上更厚,以提供所形成的封裝件較低的電氣電阻。舉例來說,第一導體120的厚度與第二導體130的第一直立高度SH1(例如厚度)的比例範圍從約55 %到約175 %,儘管該比例會有所不同,並且會隨半導體製程而縮放。應當理解,第一導體120的厚度和第一直立高度SH1會隨裝置大小或製程技術而變化,並且這些第一導體120的高度或厚度並不限於此。
圖3是根據本公開的一些示例性實施例的圖1M中繪示的虛線框B的放大示意剖面圖。參照圖3和圖1M,在熱處理製程之後,可以在第二導體130和擴散阻擋層110之間形成IMC介面IF。在一些實施例中,擴散阻擋層110可以在導電結構100和絕緣包封件300之間延緩IMC成長速度。也就是說,在沒有擴散阻擋層110的情況下,當形成第二導體130時,焊接材料可以與第一導體120反應,以在第一導體120和絕緣包封件300之間形成不期望的IMC,這可能導致在導電結構100和絕緣包封件300之間產生分層(delamination)或界面強度減低的問題。因此,由於擴散阻擋層110的存在,可以消除導電結構100和絕緣包封件300之間由IMC形成引起的界面強度及可靠度問題。
在含金屬的殘留物RS保留在擴散阻擋層110上的一些實施例中,含金屬的殘留物RS的部分與第二導體130和擴散阻擋層110的材料反應,以在第二導體130和擴散阻擋層110之間形成IMC介面IF。銅的存在可能影響導電結構100中的各層之間的黏合。舉例來說,使用含金屬的殘留物RS(例如,含銅殘留物)、擴散阻擋層110(例如,包括鎳)和第二導體130(例如,包括錫-焊料)。在一些實施例中,導電結構100的擴散阻擋層110可阻擋銅從第一導體120擴散到第二導體130。在沒有擴散阻擋層110的情況下,在第一導體120與第二導體130之間的介面處可能形成不期望的較厚的IMC,並且這種較厚的IMC會削弱導電結構100的強度並導致較差的黏合。換句話說,由於擴散阻擋層110的存在,在導電結構100之中形成的IMC介面IF可以提供良好的介面黏合,從而改善可靠度。在一些替代實施例中,具有良好濕潤性的一些材料(例如金)位於擴散阻擋層110的頂部。舉例來說,濕潤層WT形成在擴散阻擋層110上或者擴散阻擋層110包括由具有良好濕潤性的材料製成的最外層子層。在某些實施例中,在熱處理製程期間,這種具有良好濕潤性的材料可以擴散到焊接材料中。
參照圖1N,在一些實施例中,在第二半導體封裝件20安裝到第一半導體封裝件10之後,在第一半導體封裝件10和第二半導體封裝件20之間的間隙中形成底部填充層30。可以沿著切割線(未示出)執行單體化(切割)製程,以形成多個單獨且分開的電子裝置40。在一些實施例中,單體化(切割)製程包括機械鋸切或雷射切割。到此,就完成了電子裝置40的製造。
在一些實施例中,在第二半導體封裝件20的前側S3和絕緣包封件300的第二表面S2之間分配或注入底部填充材料。隨後,可以固化底部填充材料,以形成包封第二半導體封裝件20的導電接點20B的底部填充層30。底部填充層30的材料和絕緣包封件300的材料可以相同或不同,本公開不限於此。在一些實施例中,底部填充層30可以覆蓋第二半導體封裝件20的導電接點20B和重佈線電路層20A。舉例來說,底部填充層30可以覆蓋前側S3並且還側向地覆蓋第二半導體封裝件20的側壁的一部分,以增強電子裝置40的可靠度。
根據一些實施例,電子裝置包括半導體晶粒、電耦接到半導體晶粒的導電結構、包封半導體晶粒和導電結構的絕緣包封件以及設置在絕緣包封件和半導體晶粒上的重佈線結構。導電結構包括第一導體、第二導體和在第一導體與第二導體之間的擴散阻擋層。重佈線結構電連接到半導體晶粒和導電結構的第一導體。
在一些實施例中,電子裝置還包括設置在第二導體和擴散阻擋層之間的金屬間化合物介面。在一些實施例中,擴散阻擋層的厚度在約0.5 μm至約5 μm的範圍內。在一些實施例中,第一導體的材料與第二導體的材料不同。在一些實施例中,電子裝置還包括半導體封裝件,半導體封裝件包括連接到導電結構的第二導體的導電接點。在一些實施例中,半導體封裝件的導電接點和導電結構的第二導體由相同的材料製成。在一些實施例中,電子裝置還包括設置在半導體封裝件和絕緣包封件之間的底部填充層以包封半導體封裝件的導電接點。
根據一些實施例,提供了一種電子裝置的製造方法。所述方法至少包括以下步驟。形成絕緣包封件以包封多層結構和半導體晶粒,其中多層結構包括第一導體、形成在第一導體上的擴散阻擋層以及形成在擴散阻擋層上的金屬層,絕緣包封件至少暴露出半導體晶粒的一部分和多層結構的第一導體的一部分。重佈線結構形成在絕緣包封件、半導體晶粒和多層結構的第一導體上。移除多層結構的金屬層,以在絕緣包封件中形成凹陷。在擴散阻擋層上的凹陷中形成第二導體,其中第一導體、擴散阻擋層和第二導體形成導電結構,導電結構藉由重佈線結構與半導體晶粒電耦接。
在一些實施例中,所述方法還包括在晶種材料上依次形成金屬層、擴散阻擋層和第一導體,以及去除晶種材料的一部分以形成金屬層下面的晶種層,其中在去除金屬層之前去除晶種層。在一些實施例中,在去除晶種層和金屬層之後,暴露擴散阻擋層,並在擴散阻擋層上形成濕潤層。在一些實施例中,在去除金屬層之後,一部分含金屬的殘留物保留在擴散阻擋層上。在一些實施例中,當形成第二導體時,在第二導體和擴散阻擋層之間形成金屬間化合物介面。在一些實施例中,所述方法還包括在絕緣包封件和半導體晶粒上設置半導體封裝件,其中半導體封裝件包括連接到導電結構的第二導體的導電接點。在一些實施例中,所述方法還包括在半導體封裝件和絕緣包封件之間形成底部填充層,以包封半導體封裝件的導電接點。
根據一些實施例,提供了一種電子裝置的製造方法。所述方法至少包括以下步驟。提供第一半導體封裝件,其中第一半導體封裝件包括半導體晶粒、電耦合到半導體晶粒的多層導體和側向地包封半導體晶粒和多層導體的絕緣包封件,多層導體包括位於絕緣包封件的兩個相對表面之間的阻擋表面。第二半導體封裝件藉由在多層導體的阻擋表面上形成第二導體而安裝在第一半導體封裝件上,使得第一半導體封裝件和第二半導體封裝件電連接。
在一些實施例中,第二半導體封裝件包括導電特徵,並且安裝第二半導體封裝件包括在多層導體的阻擋表面上形成導電材料,以及在第一半導體封裝件上設置第二半導體封裝件和接合導電特徵和導電材料,以形成第二導體和第二導體連接的第二半導體封裝件的導電接點,其中絕緣包封件側向包封第二導體,並且絕緣包封件暴露出導電接點。在一些實施例中,提供第一半導體封裝件包括在晶種層上依次形成金屬層、擴散阻擋層和第一導體,以及移除晶種層和金屬層以在第一半導體封裝件中形成凹陷。在一些實施例中,在去除金屬層之後,一部分含金屬的殘留物保留在擴散阻擋層上,並且當形成第二導體時,部分含金屬的殘留物與導電材料反應,以在第二導體和擴散阻擋層之間形成金屬間化合物介面。在一些實施例中,所述方法還包括在第二半導體封裝件和絕緣包封件之間形成底部填充層。在一些實施例中,提供第一半導體封裝件包括形成多層結構;用絕緣包封件包封多層結構和半導體晶粒;移除多層結構的一部分,以形成多層導體;以及在多層導體上形成第二導體,以形成電耦接半導體晶粒的導電結構,其中第二導體比多層導體薄。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10:第一半導體封裝件20:第二半導體封裝件20A:重佈線電路層20B:導電接點30:底部填充層40:電子裝置50:臨時載體52:離型層60:晶粒貼附材料70:載具80:擋版100:導電結構100A:多層結構100B:多層導體110:擴散阻擋層120:第一導體130:第二導體130’:導電材料200:半導體晶粒210:半導體基板220:連接墊230:連接柱240:保護層300:絕緣包封件300’:絕緣材料400:重佈線結構410:圖案化的介電層420:圖案化的導電層500:導電端子A、B:虛線框BS:阻擋表面IF:IMC介面M1:金屬層OP:開口PR:圖案化的光阻層R:凹陷RS:含金屬的殘留物SD:晶種層SD’:晶種材料SH:總直立高度SH1:第一直立高度SH2:第二直立高度T1、T3:厚度T2:總厚度TH:開孔WT:濕潤層S1:第一表面S2:第二表面S3:前側
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。 圖1A至圖1N是本公開的一種示例性實施例的電子裝置的製造方法中各種階段的示意剖面圖。 圖2A是根據本公開的一些示例性實施例的圖1K中繪示的虛線框A的放大示意剖面圖。 圖2B是根據本公開的一些示例性實施例的圖1K中繪示的虛線框A的放大示意剖面圖。 圖3是根據本公開的一些示例性實施例的圖1M中繪示的虛線框B的放大示意剖面圖。
10:第一半導體封裝件
20:第二半導體封裝件
20B:導電接點
30:底部填充層
40:電子裝置
100:導電結構
110:擴散阻擋層
120:第一導體
130:第二導體
200:半導體晶粒
300:絕緣包封件
400:重佈線結構
500:導電端子
S2:第二表面
S3:前側
Claims (1)
- 一種電子裝置,包括: 半導體晶粒; 導電結構,電耦接到所述半導體晶粒並包括: 第一導體; 第二導體;以及 擴散阻擋層,在所述第一導體與第二導體之間; 絕緣包封件,包封所述半導體晶粒和所述導電結構;以及 重佈線結構,設置在所述絕緣包封件和所述半導體晶粒上,並且所述重佈線結構電連接到所述半導體晶粒和所述導電結構的所述第一導體。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/134,966 | 2018-09-19 | ||
US16/134,966 US10867919B2 (en) | 2018-09-19 | 2018-09-19 | Electronic device and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202013659A true TW202013659A (zh) | 2020-04-01 |
TWI756499B TWI756499B (zh) | 2022-03-01 |
Family
ID=69772306
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW107144940A TWI756499B (zh) | 2018-09-19 | 2018-12-13 | 電子裝置及其製造方法 |
Country Status (3)
Country | Link |
---|---|
US (3) | US10867919B2 (zh) |
CN (1) | CN110931442A (zh) |
TW (1) | TWI756499B (zh) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11257747B2 (en) * | 2019-04-12 | 2022-02-22 | Powertech Technology Inc. | Semiconductor package with conductive via in encapsulation connecting to conductive element |
KR20220158177A (ko) * | 2021-05-21 | 2022-11-30 | 삼성전자주식회사 | 반도체 패키지 |
US20220384306A1 (en) * | 2021-05-26 | 2022-12-01 | Intel Corporation | Thermal interface structure for integrated circuit device assemblies |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8269345B2 (en) * | 2007-10-11 | 2012-09-18 | Maxim Integrated Products, Inc. | Bump I/O contact for semiconductor device |
EP3843133A1 (en) * | 2009-05-14 | 2021-06-30 | QUALCOMM Incorporated | System-in packages |
US8592995B2 (en) * | 2009-07-02 | 2013-11-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for adhesion of intermetallic compound (IMC) on Cu pillar bump |
US8609526B2 (en) * | 2009-10-20 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Preventing UBM oxidation in bump formation processes |
US9048233B2 (en) | 2010-05-26 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers |
US9064879B2 (en) | 2010-10-14 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and structures using a die attach film |
US8797057B2 (en) | 2011-02-11 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Testing of semiconductor chips with microbumps |
US9000584B2 (en) | 2011-12-28 | 2015-04-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor device with a molding compound and a method of forming the same |
US8823180B2 (en) * | 2011-12-28 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package devices and methods of packaging semiconductor dies |
US9111949B2 (en) | 2012-04-09 | 2015-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus of wafer level package for heterogeneous integration technology |
US8872326B2 (en) * | 2012-08-29 | 2014-10-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three dimensional (3D) fan-out packaging mechanisms |
US9287245B2 (en) * | 2012-11-07 | 2016-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contoured package-on-package joint |
US9368438B2 (en) * | 2012-12-28 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package (PoP) bonding structures |
US9263511B2 (en) | 2013-02-11 | 2016-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package with metal-insulator-metal capacitor and method of manufacturing the same |
US9048222B2 (en) | 2013-03-06 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating interconnect structure for package-on-package devices |
US9368460B2 (en) | 2013-03-15 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out interconnect structure and method for forming same |
US9281254B2 (en) | 2014-02-13 | 2016-03-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming integrated circuit package |
US9496189B2 (en) | 2014-06-13 | 2016-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked semiconductor devices and methods of forming same |
US9461018B1 (en) * | 2015-04-17 | 2016-10-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out PoP structure with inconsecutive polymer layer |
WO2017052605A1 (en) * | 2015-09-25 | 2017-03-30 | Intel Corporation | Redistribution layer diffusion barrier |
TWI597811B (zh) * | 2015-10-19 | 2017-09-01 | 碁鼎科技秦皇島有限公司 | 晶片封裝方法及晶片封裝結構 |
US9508664B1 (en) * | 2015-12-16 | 2016-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device structure comprising a plurality of metal oxide fibers and method for forming the same |
US10381541B2 (en) * | 2016-10-11 | 2019-08-13 | Massachusetts Institute Of Technology | Cryogenic electronic packages and methods for fabricating cryogenic electronic packages |
US10529690B2 (en) * | 2016-11-14 | 2020-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods of forming the same |
US10153222B2 (en) * | 2016-11-14 | 2018-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods of forming the same |
US10529671B2 (en) * | 2016-12-13 | 2020-01-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and method for forming the same |
-
2018
- 2018-09-19 US US16/134,966 patent/US10867919B2/en active Active
- 2018-12-13 TW TW107144940A patent/TWI756499B/zh active
-
2019
- 2019-02-15 CN CN201910115893.7A patent/CN110931442A/zh active Pending
-
2020
- 2020-12-14 US US17/120,298 patent/US11670593B2/en active Active
-
2023
- 2023-04-25 US US18/306,989 patent/US20230260911A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
US20230260911A1 (en) | 2023-08-17 |
US20200091077A1 (en) | 2020-03-19 |
CN110931442A (zh) | 2020-03-27 |
TWI756499B (zh) | 2022-03-01 |
US11670593B2 (en) | 2023-06-06 |
US10867919B2 (en) | 2020-12-15 |
US20210098386A1 (en) | 2021-04-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11721559B2 (en) | Integrated circuit package pad and methods of forming | |
US12068212B2 (en) | Package structure with through via extending through redistribution layer and method of manufacturing the same | |
US10395946B2 (en) | Electronic package and manufacturing method thereof | |
US11282761B2 (en) | Semiconductor packages and methods of manufacturing the same | |
US9831219B2 (en) | Manufacturing method of package structure | |
US11557561B2 (en) | Package structure and method of fabricating the same | |
US11291116B2 (en) | Integrated circuit structure | |
US10510732B2 (en) | PoP device and method of forming the same | |
US11670593B2 (en) | Package-on-package (POP) electronic device and manufacturing method thereof | |
US20190139847A1 (en) | Package structure and method of manufacturing the same | |
US20200335456A1 (en) | Semiconductor package and manufacturing method thereof |