JP6797521B2 - ダイパッケージ及びダイパッケージを作製する方法 - Google Patents
ダイパッケージ及びダイパッケージを作製する方法 Download PDFInfo
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- JP6797521B2 JP6797521B2 JP2015205229A JP2015205229A JP6797521B2 JP 6797521 B2 JP6797521 B2 JP 6797521B2 JP 2015205229 A JP2015205229 A JP 2015205229A JP 2015205229 A JP2015205229 A JP 2015205229A JP 6797521 B2 JP6797521 B2 JP 6797521B2
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- dielectric
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- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000010410 layer Substances 0.000 claims description 121
- 239000010949 copper Substances 0.000 claims description 52
- 229910052802 copper Inorganic materials 0.000 claims description 51
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 40
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 34
- 229920002120 photoresistant polymer Polymers 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 29
- 239000003989 dielectric material Substances 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 26
- 229920000642 polymer Polymers 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 229910052759 nickel Inorganic materials 0.000 claims description 16
- 239000010931 gold Substances 0.000 claims description 15
- 239000010936 titanium Substances 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 12
- 229910052719 titanium Inorganic materials 0.000 claims description 12
- 238000002161 passivation Methods 0.000 claims description 11
- 238000007747 plating Methods 0.000 claims description 10
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 9
- 239000011651 chromium Substances 0.000 claims description 9
- 239000012790 adhesive layer Substances 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 239000000853 adhesive Substances 0.000 claims description 7
- 230000001070 adhesive effect Effects 0.000 claims description 7
- 229910052804 chromium Inorganic materials 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 7
- 239000003755 preservative agent Substances 0.000 claims description 7
- 230000002335 preservative effect Effects 0.000 claims description 7
- 229910000679 solder Inorganic materials 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 4
- 229910052763 palladium Inorganic materials 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 238000010330 laser marking Methods 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 238000009736 wetting Methods 0.000 claims description 3
- 235000013405 beer Nutrition 0.000 claims description 2
- 239000000969 carrier Substances 0.000 claims description 2
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims description 2
- 239000003365 glass fiber Substances 0.000 description 8
- 235000012431 wafers Nutrition 0.000 description 8
- 239000004721 Polyphenylene oxide Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 239000011159 matrix material Substances 0.000 description 6
- 229920001955 polyphenylene ether Polymers 0.000 description 6
- 229920006380 polyphenylene oxide Polymers 0.000 description 6
- 238000003491 array Methods 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 3
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229920003192 poly(bis maleimide) Polymers 0.000 description 3
- 229920002430 Fibre-reinforced plastic Polymers 0.000 description 2
- 239000011151 fibre-reinforced plastic Substances 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 238000013021 overheating Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229920006254 polymer film Polymers 0.000 description 2
- 239000011253 protective coating Substances 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 238000002845 discoloration Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000013467 fragmentation Methods 0.000 description 1
- 238000006062 fragmentation reaction Methods 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229920005597 polymer membrane Polymers 0.000 description 1
- 239000002952 polymeric resin Substances 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
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- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Description
ポリマーフレームによって囲まれたソケットのグリッドを入手し;
ダイソケットのグリッドをテープ上に載置し;
グリッドのソケット内に、下向きにダイ(フリップダイ)を載置し;
ダイ及びグリッド上に誘電材料を積層し;
誘電体上にキャリアを塗布し;
チタニウム、タンタル、タングステン、クロム及び/又はニッケルの少なくとも1つを含む接着/バリア層を堆積し、続いて新たに露出した表面上に銅のシード層を堆積し;
フォトレジストの第1層の層を塗布して、フィーチャ層でパターンを現像し;
フィーチャを形成するために、銅を、パターンに電気めっきし;
フォトレジストの第1層を剥離し;
ビアピラーのパターンでパターニングされたフォトレジストの第2層を塗布し;
ビアピラーを形成するために、銅をパターンに電気めっきし;
フォトレジストの第2層を剥離し;
接着層と銅シード層の露出部分をエッチング除去し;
銅フィーチャ、ピラー及び、ダイの下側を被覆する誘電性バリア層を塗布し;
キャリアを除去し;
ダイのアレイ裏面上に薄層の黒色誘電体を積層し;
銅ピラーを露出するために、誘電体を薄くし、
終端部を塗布し;
グリッドを、個別の実装ダイにダイシングする、方法に向けられる。
正方形又は長方形であること;
外面は、無電解ニッケル/無電解パラジウム/無電解金(ENEPIG)、無電解ニッケル/無電解金(ENIG)又は電解ニッケル−金(Ni/Au)終端技術を含む最終金属めっきが施されること;
任意には、周囲の誘電体から最大10ミクロン突出することを特徴とする。
周囲の誘電体に対して最大10ミクロン陥凹されること;
半田ボールを湿潤し易くするための円形端部を有する筒状であること;及び
有機半田付け性保存剤(Organic Solderability Preservative: OSP)でコーティングされること、の少なくとも1つを特徴とする。
6 フレーム
8、108 電子ダイパッケージ
10、110 ダイ
12、112 ピラー
14、114 パッシベーション層
16、26、116、126 誘電材料
18、118 パッド
20、22、24 ランドグリッドアレイ(LGA)
28、128 黒色誘電体
30 テープ
32 キャリア
34 接着層
36、38 フォトレジスト
120、122、124 ボールグリッドアレイ(BGA)
130 有機半田付け性保存剤
Claims (21)
- パッシベーション層に存在するダイ接触パッドを有するダイと、
接着/バリア層によってダイ接触パッドが第1側に結合されるフィーチャ層と、
前記フィーチャ層の第2側から延伸するピラーの層と、
前記ダイ、前記フィーチャ層及び前記ピラーの層を封入する誘電体層とを備えたダイパッケージであって、
前記ピラーの層は、前記ダイを基板に結合させる接点として機能するパッドのグリッドアレイを含み、
前記パッドのグリッドアレイは、前記誘電体層より最大10ミクロン延出又は陥凹しており、それによりLGAパッドを提供する、ダイパッケージ。 - 前記ダイ接触パッドは、アルミニウムピラーである、請求項1に記載の埋め込みダイパッケージ。
- 前記パッシベーション層は、PI又はSiNのどちらかを含む、請求項1に記載の埋め込みダイパッケージ。
- 前記接着/バリア層は、Ti/Cu、Ti/W/Cu、Ti/Ta/Cu、Cr/Cu及びNi/Crから成る群から選択される、請求項1に記載の埋め込みダイパッケージ。
- 前記接着/バリア層の厚さは、0.05ミクロン〜1ミクロンの範囲にある、請求項4に記載の埋め込みダイパッケージ。
- 前記フィーチャ層は、銅を含む、請求項1に記載の埋め込みダイパッケージ。
- 前記フィーチャ層の厚さは、1ミクロン〜25ミクロンの範囲にある、請求項6に記載の埋め込みダイパッケージ。
- 前記ピラーの層の高さは、15ミクロン〜50ミクロンの範囲にある、請求項6に記載の埋め込みダイパッケージ。
- 前記フィーチャ層は、ファンアウト形状を有する、請求項1に記載の埋め込みダイパッケージ。
- 前記フィーチャ層は、ファンイン形状を有する、請求項1に記載の埋め込みダイパッケージ。
- 前記ダイと前記ピラーの層が、異なるポリマー誘電材料内に埋め込まれる、請求項1に記載の埋め込みダイパッケージ。
- 前記基板は、PCBである、請求項1に記載の埋め込みダイパッケージ。
- 前記基板は、Package on Package(PoP)を作製するためのパッケージである、請求項1に記載の埋め込みダイパッケージ。
- 前記パッドのグリッドアレイは、電解Ni/Au、ENIG又はENEIGから成る群から選択される終端部で終端される、請求項1に記載の埋め込みダイパッケージ。
- 前記パッドのグリッドアレイは、有機半田付け性保存剤(Organic Solderability Preservative: OSP)で終端される、請求項1に記載の埋め込みダイパッケージ。
- ダイパッケージを作製する方法であって、
ポリマーフレームによって囲まれたソケットのグリッドを入手し;
前記ソケットのグリッドをテープ上に載置し;
前記グリッドの前記ソケット内に、下向きにダイ(フリップダイ)を載置し;
前記ダイ及び前記グリッド上に誘電材料を積層して誘電体を形成し;
前記誘電体上にキャリアを塗布し;
チタニウム、タンタル、タングステン、クロム及び/又はニッケルの少なくとも1つを含む接着層/バリア層を堆積し、続いて新たに露出した表面上に銅シード層を堆積し;
フォトレジストの第1層の層を塗布して、フィーチャ層でパターンを現像し;
フィーチャを形成するために、銅を、前記パターンに電気めっきし;
前記フォトレジストの第1層を剥離し;
ビアピラーのパターンでパターニングされたフォトレジストの第2層を塗布し;
ビアピラーを形成するために、銅を前記パターンに電気めっきし;
前記フォトレジストの第2層を剥離し;
前記接着層と前記銅シード層の露出部分をエッチング除去し;
前記フィーチャ、前記ビアピラー及び、前記ダイの下側を被覆する誘電性バリア層を塗布し;
キャリアを除去し;
前記ダイのアレイ裏面上に薄層の黒色誘電体を積層し;
前記ビアピラーを露出するために、前記誘電体を薄くし、
終端部を塗布し;
前記グリッドを、個別の実装ダイにダイシングする、方法。 - 前記黒色誘電体をレーザマーキングする更なるステップが続く、請求項16に記載の方法。
- ダイのアレイは、各ソケット内に配置される、請求項16に記載の方法。
- ウエハ上にダイのアレイを有するウエハは、各ソケット内に配置される、請求項16に記載の方法。
- 前記ビアピラーは、ランドグリッドアレイ(LGA)を含み、少なくとも1つの以下の制限:
正方形又は長方形とすること;
外面は、無電解ニッケル/無電解パラジウム/無電解金(ENEPIG)、無電解ニッケル/無電解金(ENIG)又は電解ニッケル−金(Ni/Au)終端技術を含む最終金属めっきが施されること;
任意には、周囲の誘電体から最大10ミクロン突出することを特徴とする、請求項16に記載の方法。 - 前記ビアピラーは、パッドのボールグリッドアレイ(BGA)を含み、
周囲の誘電体に対して最大10ミクロン陥凹されること;
半田ボールを湿潤し易くするための円形端部を有する筒状であること;及び
有機半田付け性保存剤(Organic Solderability Preservative: OSP)でコーティングされること、の少なくとも1つを特徴とする、請求項16に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/789,165 | 2015-07-01 | ||
US14/789,165 US9779940B2 (en) | 2015-07-01 | 2015-07-01 | Chip package |
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JP2017017300A JP2017017300A (ja) | 2017-01-19 |
JP6797521B2 true JP6797521B2 (ja) | 2020-12-09 |
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JP2015205229A Active JP6797521B2 (ja) | 2015-07-01 | 2015-10-19 | ダイパッケージ及びダイパッケージを作製する方法 |
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US (1) | US9779940B2 (ja) |
JP (1) | JP6797521B2 (ja) |
KR (2) | KR101713643B1 (ja) |
CN (1) | CN106328604B (ja) |
TW (1) | TWI715567B (ja) |
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CN108305864B (zh) * | 2017-01-12 | 2020-08-18 | 珠海越亚半导体股份有限公司 | 端子 |
JP6432639B2 (ja) * | 2017-04-28 | 2018-12-05 | 日亜化学工業株式会社 | 発光装置 |
TWI628756B (zh) * | 2017-08-22 | 2018-07-01 | 鳳凰先驅股份有限公司 | 封裝結構及其製作方法 |
CN207134353U (zh) * | 2017-08-31 | 2018-03-23 | 深圳市江波龙电子有限公司 | 移动终端及其芯片封装结构 |
US11610855B2 (en) * | 2017-11-29 | 2023-03-21 | Pep Innovation Pte. Ltd. | Chip packaging method and package structure |
WO2020087253A1 (en) * | 2018-10-30 | 2020-05-07 | Yangtze Memory Technologies Co., Ltd. | Ic package |
CN109257874A (zh) * | 2018-11-16 | 2019-01-22 | 深圳市和美精艺科技有限公司 | 一种在pcb板制作过程中芯片埋入的方法及其结构 |
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