TW201703212A - 晶片封裝 - Google Patents

晶片封裝 Download PDF

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Publication number
TW201703212A
TW201703212A TW105111634A TW105111634A TW201703212A TW 201703212 A TW201703212 A TW 201703212A TW 105111634 A TW105111634 A TW 105111634A TW 105111634 A TW105111634 A TW 105111634A TW 201703212 A TW201703212 A TW 201703212A
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Taiwan
Prior art keywords
wafer
layer
dielectric material
package
embedded
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TW105111634A
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English (en)
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TWI715567B (zh
Inventor
Hurwitz Dror
Alex Shi-Fu Huang
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Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co Ltd
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Publication of TW201703212A publication Critical patent/TW201703212A/zh
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Publication of TWI715567B publication Critical patent/TWI715567B/zh

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    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
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Abstract

一種嵌入式晶片封裝，其包括晶片，所述晶片具有在鈍化層中的晶片接觸焊盤，所述晶片接觸焊盤通過粘附/阻擋層連接至特徵層的第一面，從所述特徵層的第二面延伸出通孔柱層，所述晶片、特徵層和通孔柱層被介電材料包封。

Description

晶片封裝
本發明涉及電子晶片封裝及其製造方法。
消費電子產品，例如電腦和電信設備，包含有積體電路晶片。
實現晶片與外界連接的常規方法是將IC基板作為晶片封裝的一部分。封裝晶片具有諸如球柵陣列BGA或觸點柵格陣列LGA的連接件，用於連接到印刷電路板PCB等基板上，而這些基板則連接其它元件。
IC基板要求具有高平整度、高強度和抗翹曲性以確保與PCB及其它基礎基板具有良好的接觸。具體而言，對於IC基板和晶片封裝的總體要求是可靠性和合適的電氣性能、厚度、硬度、平整度，良好的散熱性以及有競爭力的單價。
引線框架(lead frame)是一種完善且常見的晶片封裝類型，其價格相對低廉並且能夠實現IC電路與外界連接。引線框架使用延伸出殼體外的金屬引線。引線框架技術回到了DIP晶片的初期，但仍然被廣泛應用于許多種封裝中。
引線框架作為IC封裝的“骨架”，其在晶片組裝成最終產品的過程中為晶片提供機械支撐。引線框架包括晶片附著其上的晶片焊盤以及作為連接至外界的外部電連接裝置的引線。晶片經由導線通過導線接合或帶式自動接合的方式連接至引線。
在利用連接導線連接至引線框架後，晶片被稱為模塑膠的塑膠保護材料覆蓋。
用於製造更先進的多層基板的技術包括連接焊盤的層或嵌入介電材料內的特徵結構。提供穿過介電材料的通孔，用以將不同層中的特徵結構電連接在一起。
用於製造此類通孔的一種方法是鑽填法，其中通常利用鐳射鑽出穿過介電材料的孔，並且利用導電材料例如銅來填充該孔以形成通孔。
製造通孔的另一種方法是通過在適當波長的光(通常是紫外光)下選擇性曝光光刻膠形成的圖案內沉積銅或其它金屬，其中通過在燈下經由模版選擇性曝光形成圖案或利用鐳射劃線創建圖案。這種在光刻膠顯影形成的圖案中進行電鍍的技術稱為“圖案鍍覆”。隨後移除光刻膠，並且在直立的通孔柱上層壓介電材料，該介電材料優選為聚合物浸漬增強玻璃纖維墊預浸料。
在圖案鍍覆中，首先沉積種子層。然後在其上沉積光刻膠層並隨後曝光以創建圖案，其中光刻膠被選擇性移除以形成暴露出種子層的溝槽。通過在光刻膠溝槽中沉積銅而形成通孔柱。隨後移除殘餘的光刻膠，蝕刻掉種子層，並且在其上及其周圍再次層壓通常為聚合物浸漬玻璃纖維墊預浸料的介電材料以包圍通孔柱。然後可以採用各種技術和工藝來減薄介電材料，將其平坦化，並暴露出通孔柱的頂部，由此允許導電連接至接地面或參考面，用於在其上構建下一個金屬層。可以在其上沉積具有金屬導體和通孔柱的後續層，通過重複該過程來構建所期望的多層結構。
在一個可選但密切相關的下文稱為“面板鍍覆”的技術 中，在基板上沉積金屬或合金的連續層。在其上表面上沉積光刻膠層並在光刻膠中顯影出圖案。隨後，將被顯影的光刻膠選擇性剝除，選擇性地暴露出其下方的金屬，該暴露的金屬可以隨後被蝕刻掉。未顯影光刻膠保護其下方的金屬不被蝕刻，並且留下直立的特徵結構和通孔的圖案。在未顯影光刻膠被剝除之後，可以在直立的銅特徵結構和/或通孔柱上及其周圍層壓介電材料，例如聚合物浸漬玻璃纖維墊。在其它變化方案中，未顯影光刻膠圖案被剝除，保留顯影光刻膠作為掩膜。
通過圖案鍍覆或面板鍍覆方法形成的通孔層，例如上文所述的那些，通常被稱為“通孔柱”。特徵層可以採用類似的技術來製造。
一種製造高密度互連的靈活技術是構建由介電基質中的金屬通孔或特徵結構構成的圖案或面板鍍覆的多層結構。用於通孔和特徵結構的金屬可以是銅，並且介電材料可以由纖維增強聚合物基質構成。通常，採用具有高玻璃化轉變溫度(Tg)的聚合物，例如聚醯亞胺。這些互連可以是有芯的或無芯的，並且可以包括用於堆疊元件的空腔。它們可以具有奇數或偶數的層數。授予Amitec Advanced Multilayer Interconnect Technologies Ltd.的在先專利，例如Hurwitz等人的題為“Advanced Multilayer Coreless Support Structures and Method for their Fabrication”的US 7,682,972中描述的實施技術公開了一種製造自支援膜的方法，所述膜包括在介電材料中的通孔陣列，用作構建優良電子支撐結構的構造前體。該方法包括在犧牲載體上的介電材料圍繞物中製造導電通孔膜以及從犧牲載體上分離所述膜以形成一個自支持的層壓陣列的步驟。可以通過將該層壓陣列減薄和平坦化並隨後將通孔端子化來形成基於該自支援膜的電子基 板。該出版物通過引用全文併入本文。
Hurwitz等人的題為“Integrated Circuit Support Structures and their Fabrication”的US 7,635,641描述了一種製造電子件的方法，包括以下步驟：(A)選擇第一基層；(B)在第一基層上沉積第一抗蝕阻擋層；(C)構建由交替的導電層和絕緣層構成的第一半堆疊體，導電層經由穿過絕緣層的通孔互連；(D)在第一半堆疊體上施加第二基層；(E)在第二基層上施加光刻膠保護塗層；(F)蝕刻掉第一基層；(G)移除光刻膠保護塗層；(H)移除第一抗蝕阻擋層；(I)構建由交替的導電層和絕緣層構成的第二半堆疊體，導電層經由穿過絕緣層的通孔互連，其中第二半堆疊體具有與第一半堆疊體基本對稱的層；(J)在由交替的導電層和絕緣層構成的第二半堆疊體上施加絕緣層；(K)移除第二基層；和(L)通過在堆疊體的外表面上暴露出通孔端部並對其施加端子來對基板進行端子化。該出版物通過引用全文併入本文。
多層基板實現了更高密度的互連並且被用於更為複雜的IC晶片。它們比簡單的單層引線框架更為昂貴，並且對於許多電子應用而言，更經濟的引線框架才是適用的。
即使用於封裝相對簡單的晶片，儘管單層就足夠，但是引線框架技術仍有其局限性。晶片通過導線接合連接至引線框架，連接導線越長則導線斷裂、產生短路從而導致失效的危險性就越高。此外，導線在一起排列得越緊密，則短路的可能性就越大。
介電材料中的通孔柱方法適合用於多層基板，但通常過於單薄而無法應用于單層中，因為應該認識到，翹曲和彎曲會導致接觸不良、 不可靠和短路。
Hurwitz等人的題為“Single Layer Coreless Substrate”的US 8,866,286描述了一種電子晶片封裝，包括與外掛程式佈線層接合的至少一個晶片，所述外掛程式佈線層包括佈線層和通孔柱層，其中通孔柱層被介電材料包圍，介電材料包括在聚合物樹脂中的玻璃纖維，並且晶片和佈線層嵌入在第二介電材料層中，該第二介電材料層包封晶片和佈線層。在這種封裝技術中，通孔柱的銅端部與介電材料齊平。
該封裝相當堅固，但是可能會過熱。此外，這種封裝可能會由於導線接合而導致具有雜散電感，並且可能會由於組裝過程以及晶片附著、導線接合和成型所需的材料導致製造成本高昂。
仍然存在對於薄、可靠且低成本的晶片封裝的需求，本發明的實施方案滿足了這一需求。
本發明的實施方案涉及提供一種新型晶片封裝解決方案。
本發明第一方面涉及一種嵌入式晶片封裝，其包括晶片，所述晶片具有在鈍化層中的晶片接觸焊盤，所述晶片接觸焊盤通過粘附/阻擋層連接至特徵層的第一面，從所述特徵層的第二面延伸出通孔柱，所述晶片、特徵層和通孔柱被介電材料包封。
通常，所述晶片接觸焊盤包括鋁。
通常，所述鈍化層包括PI(聚醯亞胺)或SiN。
一般而言，所述粘附/阻擋層選自Ti/Cu、Ti/W/Cu、Ti/Ta/Cu、Cr/Cu、Ni/Cu和Cr/Ni/Cu。
通常，所述粘附/阻擋層的厚度為0.05微米至1微米。
通常，所述特徵層包括銅。
通常，所述特徵層的厚度為1微米至25微米。
在一些實施方案中，所述特徵層具有扇出形式。
在一些實施方案中，所述特徵層具有扇入形式。
在一些實施方案中，所述晶片和通孔柱嵌入在不同的聚合物介電材料內。
在一些實施方案中，通孔柱層提供焊盤的柵格陣列，用作晶片與基板連接的接觸。
任選地，所述基板是印刷電路板。
任選地，所述基板是用於製造封裝上封裝(PoP)的封裝。
通常，根據工業標準將所述焊盤柵格陣列端子化。
在一些實施方案中，通孔柱的柵格陣列延伸超出介電材料至多10微米或是與介電材料齊平，從而提供LGA焊盤。
任選地，通孔柱的柵格陣列利用選自Ni/Au、ENIG或ENEIG的端子進行端子化。
在一些實施方案中，通孔柱的柵格陣列凹陷低於介電材料至多10微米或者與介電材料齊平，由此提供BGA焊盤。
在一些實施方案中，通孔柱的柵格陣列利用有機保焊劑(OSP)進行端子化。
本發明第二方面涉及一種製造如本文所述的新型晶片封裝的方法，包括：
‧獲得由聚合物框架包圍的晶片插座柵格；
‧將所述晶片插座柵格放置在膠帶上；
‧將晶片面朝下(倒裝晶片)放入柵格的插座中；
‧在所述晶片和柵格上層壓介電材料；
‧在所述介電材料上施加載體；
‧沉積粘附/阻擋層，所述粘附/阻擋層包括選自鈦、鉭、鎢、鉻和/或鎳中的至少其一，隨後在新暴露的表面上沉積銅種子層；
‧施加第一光刻膠層，並顯影出具有特徵層的圖案；
‧在所述圖案中電鍍銅，形成特徵結構；
‧剝除所述第一光刻膠層；
‧施加第二光刻膠層，並將其圖案化形成通孔柱圖案；
‧在所述通孔柱圖案中電鍍銅以形成通孔柱；
‧剝除第二光刻膠層；
‧蝕刻掉粘附/阻擋層和銅種子層的暴露部分；
‧施加介電材料阻擋層以覆蓋銅特徵結構、通孔柱和晶片的底面；
‧移除載體；
‧在晶片陣列的背面上層壓黑色介電材料薄層；
‧減薄介電材料以暴露出銅通孔柱；
‧施加端子；和
‧將所述柵格切割成獨立的封裝晶片。
‧任選地，晶片陣列被定位在每個插座內。
在一個變型的製造路線中，將其上具有晶片陣列的晶片定位在每個插座內。
在一些實施方案中，銅通孔柱包括LGA(觸點柵格陣列)並且其特徵在於以下限制條件中的至少其一：‧正方形或長方形的形狀；‧外表面鍍有最終金屬鍍層，包括化學鍍鎳/化學鍍鈀/浸金(ENEPIG)或化學鍍鎳/浸金(ENIG)或電解鎳和金(Ni/Au)的端子化技術，以及‧任選從周圍介電材料突起至多10微米。
在一些實施方案中，銅通孔柱包括焊盤BGA(球柵陣列)，其特徵在於以下至少其一：‧相對于周圍介電材料凹陷至多10微米；‧具有圓形端部的圓柱體形狀，以易於被焊料潤濕；和‧塗有OSP(有機保焊劑)。
通常，在所述黑色介電材料上進行鐳射標記。
4‧‧‧晶片插座
6‧‧‧聚合物框架
8‧‧‧電子晶片封裝
10‧‧‧晶片
12‧‧‧鋁柱
14‧‧‧鈍化層
16‧‧‧第一介電材料、填料
18‧‧‧焊盤、銅特徵結構
20、22、24‧‧‧觸點柵格陣列(LGA)、銅通孔柱
26‧‧‧介電材料
28‧‧‧黑色介電材料薄層
30‧‧‧最終金屬鍍層、端子、膠帶
32‧‧‧載體
34‧‧‧粘附金屬、粘附層
36‧‧‧光刻膠層
38‧‧‧第二光刻膠層
108‧‧‧電子晶片封裝
110‧‧‧晶片
112‧‧‧鋁柱
114‧‧‧鈍化層
116‧‧‧介電材料
118‧‧‧焊盤
120、122、124‧‧‧BGA(球柵陣列)、銅柱
126‧‧‧介電材料
128‧‧‧黑色介電材料薄層
130‧‧‧OSP(有機保焊劑)
為了更好地理解本發明並示出本發明的實施方式，純粹以舉例的方式參照附圖。
現在具體參照附圖，必須強調的是，具體圖示僅為示例且出於示意性討論本發明優選實施方案的目的，提供圖示的原因是確信附圖是最有用且易於理解本發明的原理和概念的說明。就此而言，沒有試圖將本發明的結構細節以超出對本發明基本理解所必需的詳細程度來圖示；參照 附圖的說明使本領域技術人員能夠知曉本發明的幾種實施方式可如何實施。在附圖中：圖1是根據一個實施方案的電子晶片封裝的簡化截面圖，其中實現封裝晶片與基板通過觸點柵格陣列(LGA)的連接；圖2是根據一個實施方案的電子晶片封裝的簡化截面圖，其中實現封裝晶片與基板通過球柵陣列(BGA)的連接；圖3是示出圖1的電子晶片封裝的製造方法的流程圖；圖3(a)-3(u)是對應於圖3流程圖的各個步驟的中間結構的附屬側視圖；在各個附圖中，相同的附圖標記指示相同的要素。
術語“微米”是指1 x 10-6米，並可表示為“μm”。
在下文的說明中，所涉及的是支撐結構，其由介電材料中的金屬通孔，特別是在聚合物基質中的銅通孔柱構成，所述介電材料例如是玻璃纖維增強的聚醯亞胺、環氧樹脂或BT(雙馬來醯亞胺/三嗪)、聚苯醚(PPE)或其共混物。
參照圖1，示出根據一個實施方案的電子晶片封裝的簡化截面圖，該封裝實現了晶片10與基板通過觸點柵格陣列(LGA)20、22、24的連接。
電子晶片封裝8包括晶片10以及在鈍化層14中的鋁柱12，鈍化層14包含PI或氮化矽。
晶片10和在鈍化層14中的鋁柱12通過層壓第一介電材料16 而被包封，第一介電材料16具有聚合物基質，例如聚醯亞胺、環氧樹脂或BT(雙馬來醯亞胺/三嗪)、聚苯醚(PPE)、聚苯醚(PPO)或它們的共混物，該聚合物基質作為膜提供或者作為玻璃纖維增強預浸料提供以增加強度。
焊盤18與鋁柱12連接。
在焊盤18的設置有IC晶片10的一面相反的另一面上製造銅柱層20、22、24。
有用的是，焊盤18扇出，並且這些柱22、24中的一個或多個設置為超出IC晶片10的周邊，這通常稱為扇出構造，以便於連接到基板，如具有較大規模觸點的印刷電路板。
這些柱20中的一個或多個可以是晶片下方的大柱，它們除了提供連接選定的柱12的電連接外，還可以將多個柱12連接到一起，也可以接地，還用作散熱器，帶走晶片10的熱量並使其在大體積上耗散。應當指出的是，介電材料16、26通常是良好的熱絕緣體，即差的熱導體，因此倒裝晶片構造會遭受過熱，從而引起資料損壞或雜訊。
作為扇出構造的替代，應該認識到在技術上可以根據需要提供扇入構造。此外，在切割之前，如果加工的是“在晶圓上”的多個晶片而不是獨立晶片，則通常不可能採用扇出構造。
焊盤18和柱20、22、24可以包封在介電材料26中，介電材料26可以是與包封晶片10的介電材料16不同的介電材料。可以在晶片封裝8上層壓黑色介電材料薄層28以利於鐳射標記的可視性。黑色介電材料層28可以作為預浸料或作為聚合物膜提供。
為了利用觸點柵格陣列(LGA)連接到基板如印刷電路板(PCB)，柱20、22、24通常為正方形或長方形，不過也可以具有其它形狀，例如可以是圓形的。
為了易於附著到基板，柱20、22、24的端部可突起超出介電材料至多10微米。柱20、22、24的暴露端部通常在其外表面上塗覆最終金屬鍍層30，包括電解Ni/Au(有時稱為化學鍍鎳浸金)或Ni/Pd/Au(在金的下方和鎳的上方具有鈀層)，該工藝稱為ENEPIG。
參照圖2，示出根據一個實施方案的電子晶片封裝108的第二簡化截面圖，該封裝實現了將晶片110與基板通過球柵陣列(BGA)120、122、124連接。
電子晶片封裝108包括晶片110以及在鈍化層114中的鋁柱112，該鈍化層114包含PI或SiN。
晶片110和在鈍化層114中的鋁柱112通過層壓第一介電材料116而被包封，第一介電材料16具有聚合物基質，例如聚醯亞胺、環氧樹脂或BT(雙馬來醯亞胺/三嗪)、聚苯醚(PPE)、聚苯醚(PPO)或它們的共混物，該聚合物基質作為膜提供或者作為玻璃纖維增強預浸料提供以增加強度。
焊盤118連接鋁柱112。
在焊盤118的設置有IC晶片110的一面相反的另一面上製造銅柱層120、122、124。
有用的是，焊盤118扇出，並且這些柱122、124中的一個或多個設置為超出IC晶片110的周邊，這通常稱為扇出構造，以便於連接到基 板，如具有較大規模觸點的印刷電路板。這些柱120中的一個或多個可以是晶片下方的大柱，它們除了提供連接選定的柱112的電連接外，還可以將多個柱112連接到一起，也可以接地，還用作散熱器，帶走晶片110的熱量並使其在大體積上耗散。應當指出的是，介電材料116、126通常是良好的熱絕緣體，即差的熱導體，因此倒裝晶片構造會遭受過熱，從而引起資料損壞或雜訊。
作為扇出構造的替代，應該認識到在技術上可以根據需要提供扇入構造。此外，在切割之前，如果多個晶片在晶片上被封裝和端子化，則通常不可能採用扇出構造。
焊盤118和柱120、122、124可以包封在介電材料126中，介電材料126可以是與包封晶片110的介電材料116不同的介電材料。可以在晶片封裝108上層壓黑色介電材料薄層128以利於鐳射標記的可視性。黑色介電材料層128可以作為預浸料或作為聚合物膜提供。
為了利用球柵陣列(BGA)連接到基板如印刷電路板(PCB)，在焊料球附著至柱的端部並展開成半球形帽時，柱120、122、124通常是具有圓形截面的圓柱體以易於被焊料球潤濕，然而，柱120、122、124也可以具有其它形狀，例如可以是橢圓形、正方形或長方形。
與圖1中的柱20、22、24的突起端部不同，對於BGA而言，柱120、122、124的端部通常埋入介電材料126中，介電材料126延伸超出柱120、122、124的端部至多10微米，這有助容納後續施加在封裝上的焊料球。為了防止在施加球柵陣列(BGA)之前焊料球變色，柱120、122、124的端部通常塗覆有有機保焊劑(OSP)130的表面塗層。
此外，應當指出的是，分別用作圖1和圖2中描述的封裝中的LGA和BGA焊盤的兩個銅柱具有柱結構，通常具有至少200微米的寬度(或直徑)以及通常為15微米至50微米的厚度。銅柱的尺寸還可以有助於減少對於進出晶片的電流的直流電阻-由此增加了晶片的功能範圍和整體封裝可靠性-尤其是對於高功率晶片的應用。
參照圖3的流程圖以及示出在聚合物框架4中的插座6的陣列和嵌入其中並連接的晶片10的截面的示意側視圖的圖3(a)-3(u)，下文具體說明一種製造圖1和2的結構的方法。
首先，獲取由聚合物框架4包圍的插座6的柵格-步驟3(a)。圖3(a)示出一對相鄰的插座。以下說明描述了將一對獨立的晶片拾取和放置在單晶片插座中的處理過程。在實踐中，可以對插座的大二維陣列一起處理。此外，在一個變型過程中，可利用單個插座來處理其上具有晶片柵格的晶片，隨後可以將該晶片切割。
框架6可包括作為聚合物片材施加的聚合物，或者該聚合物可以是作為預浸料施加的玻璃纖維增強聚合物。框架6可具有一個或多個層。貫穿插座4可以是衝壓成型的，或者框架6可製造在犧牲銅樁上，犧牲銅樁隨後被溶解而提供貫穿插座4。
珠海越亞的面板可為21"×25"，並且封裝晶片可為5mm×5mm。因此，這種製造技術能夠實現在單個面板上封裝10000個晶片。
然而，應該理解的是，並不是面板的所有區塊都需要相同尺寸的晶片插座。此外，不僅一個或多個區塊可用於不同尺寸的插座以容納不同尺寸的晶片，而且任意尺寸的任意子陣列可用於製造任意特定的晶片 封裝，所以儘管生產量很大，但是可以製造少量少批的晶片封裝，使得能夠為特定客戶同時加工處理不同的晶片封裝或為不同的客戶製造不同的封裝。因此，面板可包括用於容納一種類型晶片的具有第一組尺寸的插座的至少一個區域以及具有用於容納第二類型晶片的具有第二組尺寸的插座的第二區域。此外，在一個或多個晶片上的晶片陣列可設置在該面板中具有晶片尺寸大小的插座中，並且晶片可以隨後被封裝，然後進行晶片切割。
如圖所示3(a)所示，每個晶片插座4被聚合物框架6包圍。晶片插座柵格4放置在膠帶30上-步驟3(b)，圖3(b)。晶片10面朝下(倒裝晶片)放置在框架6的插座4中-步驟3(c)，圖3(c)，使得鈍化層14中的鋁觸點12(參見圖1及圖2)接觸膠帶30。
在晶片10和柵格6上層壓介電材料16，通常為聚合物膜或纖維增強聚合物預浸料-步驟3(d)，圖3(d)。
接著，在介電材料16上施加載體32-步驟3(e)，圖3(e)。然後移除膠帶30-步驟3(f)，圖3(f)，暴露出晶片觸點12。在新暴露出的表面上沉積粘附層34，其包括鈦、鉭、鎢、鉻和/或鎳中的至少其一，然後沉積銅種子層-步驟3(g)，圖3(g)。通常採用物理氣相沉積(PVD)。粘附金屬34的選擇取決於聚合物6和鈍化層14。粘附層34的典型組合是Ti/Cu、Ti/W/Cu、Ti/Ta/Cu和Cr/Cu，厚度範圍為0.05微米至1微米。
施加並圖案化光刻膠層36以形成特徵層-步驟3(h)，圖3(h)。然後，在該圖案中電鍍銅以形成特徵結構18-步驟3(i)，圖3(i)。通常，特徵結構18的厚度範圍為1微米至25微米。特徵結構18可從晶片扇出或可向內扇入。某些特徵結構可向外扇出並且某些特徵結構可向內扇入。當加工 處理晶片上的晶片陣列時，一般不可能採用扇出構造。
剝除光刻膠層36-步驟3(j)，圖3(j)，並且施加第二光刻膠層38並圖案化形成具有通孔柱的圖案-步驟3(k)，圖3(k)。在該圖案中電鍍銅以形成通孔柱層20、22、24-步驟3(l)，圖3(l)。通常，通孔柱20的長度範圍為15微米至50微米。
剝除第二光刻膠層38-步驟3(m)，圖3(m)，並且濺射具有Ti、Ta、Ni、Cr、W中的一種或多種的粘附層34，隨後蝕刻掉銅種子層3(n)。
接著，施加介電材料阻擋層26以覆蓋銅特徵結構18和通孔柱20、22、24以及晶片10的底面-步驟3(o)，圖3(o)。
接下來，移除載體32。通常，載體是銅並且簡單地蝕刻掉。載體可以是兩層銅載體，包括厚層和可剝離地附著在厚層上的薄層，在這種情況下，厚層被剝離而薄層被蝕刻掉-步驟3(p)，圖3(p)。
聚合物可以通過拋光、研磨或通過化學機械拋光(CMP)進行減薄。
在該階段，可以在框架6和晶片陣列10的背面層壓黑色介電材料28的薄層(膜或預浸料)-步驟3(r)，圖3(r)。
將光刻膠或其它聚合物介電材料26減薄，以暴露出銅通孔柱20、22、24-步驟3(s)，圖3(s)。
施加端子30-步驟3(t)，圖(t)，然後將陣列分割(切割)成單個封裝晶片8-步驟3(u)，圖3(u)。
如圖3(u)和圖1所示，銅通孔柱20、22、24包括用作LGA(觸點柵格陣列)的觸點的焊盤柵格陣列和銅通孔柱20、22、24的上表面，銅 通孔柱20、22、24的上表面可與其周圍的介電材料齊平(圖u)或可突出超過介電材料背面至多約10微米(圖1)，在其外表面上鍍覆有最終金屬鍍層，包括化學鍍鎳/化學鍍鈀/浸金(ENEPIG)或化學鍍鎳/浸金(ENIG)或電解鎳和金(Ni/Au)的端子化技術。在觸點柵格陣列結構中，通孔柱20、22、24可以是正方形或長方形的。
綜上，已經示出了製造圖1結構的方法。其特徵在於，晶片封裝可以包括2種或3種不同的介電材料，框架6與填料16可以是相同或不同的聚合物或纖維增強聚合物，包圍通孔柱柱26的介電材料是第三介電材料。
應當理解的是，由圖3的方法得到的圖3(u)所示的結構可以進一步改進，使得銅柱層包括用作BGA(球柵陣列)形式觸點的焊盤柵格陣列。在這種實施方案中，如圖2所示，銅通孔柱120、122、124的外表面可與周圍的介電材料126齊平，或者可以從周圍介電材料126的表面處凹陷至多10微米。用於BGA的通孔柱通常是具有圓形端部的圓柱體，以利於被焊料球潤濕。
當構造為球柵陣列時，通孔柱端部通常塗覆有OSP 130(有機保焊劑)。
本領域技術人員將會認識到，本發明不限於上文中具體圖示和描述的內容。而且，本發明的範圍由所附請求項限定，包括上文所述的各個技術特徵的組合和子組合以及其變化和改進，本領域技術人員在閱讀前述說明後將會預見到這樣的組合、變化和改進。
在專利說明書中，術語“包括”及其變體例如“包含”、“含有”等是指所列舉的元件被包括在內，但一般不排除其他元件。
8‧‧‧電子晶片封裝
10‧‧‧晶片
12‧‧‧鋁柱
14‧‧‧鈍化層
16‧‧‧第一介電材料、填料
18‧‧‧焊盤、銅特徵結構
20、22、24‧‧‧觸點柵格陣列(LGA)、銅通孔柱
26‧‧‧介電材料
28‧‧‧黑色介電材料薄層
30‧‧‧最終金屬鍍層、端子、膠帶

Claims (24)

  1. 一種嵌入式晶片封裝，其包括晶片，所述晶片具有在鈍化層中的晶片接觸焊盤，所述晶片接觸焊盤通過粘附/阻擋層連接至特徵層的第一面，從所述特徵層的第二面延伸出通孔柱層，所述晶片、特徵層和通孔柱層被介電材料包封。
  2. 如權利要求1所述的嵌入式晶片封裝，其中所述晶片接觸焊盤包括鋁。
  3. 如權利要求1所述的嵌入式晶片封裝，其中所述鈍化層包括聚醯亞胺或SiN。
  4. 如權利要求1所述的嵌入式晶片封裝，其中所述粘附/阻擋層選自Ti/Cu、Ti/W/Cu、Ti/Ta/Cu、Cr/Cu和Ni/Cr。
  5. 如權利要求4所述的嵌入式晶片封裝，其中所述粘附/阻擋層的厚度範圍為0.05~1微米。
  6. 如權利要求1所述的嵌入式晶片封裝，其中所述特徵層包括銅。
  7. 如權利要求6所述的嵌入式晶片封裝，其中所述特徵層的厚度範圍為1~25微米。
  8. 如權利要求6所述的嵌入式晶片封裝，其中所述通孔柱層的高度範圍為15~50微米。
  9. 如權利要求1所述的嵌入式晶片封裝，其中所述特徵層具有扇出形式。
  10. 如權利要求1所述的嵌入式晶片封裝，其中所述特徵層具有扇入形式。
  11. 如權利要求1所述的嵌入式晶片封裝，其中所述晶片和所述通孔柱層嵌入在不同的聚合物介電材料中。
  12. 如權利要求1所述的嵌入式晶片封裝，其中所述通孔柱層包括焊盤柵格陣列，所述焊盤柵格陣列用作連接所述晶片與基板的觸點。
  13. 如權利要求12所述的嵌入式晶片封裝，其中所述基板是印刷電路板。
  14. 如權利要求12所述的嵌入式晶片封裝，其中所述基板是用於製造封裝上封裝的封裝。
  15. 如權利要求12所述的嵌入式晶片封裝，其中所述焊盤柵格陣列延伸超出介電材料至多10微米或者與所述介電材料齊平，從而提供LGA焊盤。
  16. 如權利要求15所述的嵌入式晶片封裝，其中所述焊盤柵格陣列採用選自電解Ni/Au、ENIG或ENEIG的端子進行端子化。
  17. 如權利要求12所述的嵌入式晶片封裝，其中所述焊盤柵格陣列凹陷低於所述介電材料至多10微米或者與所述介電材料齊平，從而提供BGA焊 盤。
  18. 如權利要求17所述的嵌入式晶片封裝，其中所述焊盤柵格陣列採用有機保焊劑OSP進行端子化。
  19. 一種製造嵌入式晶片封裝的方法，包括：‧獲得由聚合物框架包圍的晶片插座柵格；‧將所述晶片插座柵格放置在膠帶上；‧將晶片面朝下(倒裝晶片)放入所述晶片插座柵格的插座中；‧在所述晶片和晶片插座柵格上層壓介電材料；‧在所述介電材料上施加載體；‧沉積粘附/阻擋層，所述粘附/阻擋層包括選自鈦、鉭、鎢、鉻和/或鎳中的至少其一，隨後在新暴露的表面上沉積銅種子層；‧施加第一光刻膠層，並顯影出具有特徵層的圖案；‧在所述具有特徵層的圖案中電鍍銅，形成銅特徵結構；‧剝除所述第一光刻膠層；‧施加第二光刻膠層，並將其圖案化形成通孔柱圖案；‧在所述通孔柱圖案中電鍍銅以形成通孔柱；‧剝除所述第二光刻膠層；‧蝕刻掉所述粘附/阻擋層和所述銅種子層的暴露部分；‧施加介電材料阻擋層以覆蓋所述銅特徵結構、通孔柱和晶片的底面；‧移除載體；‧在晶片陣列的背面上層壓黑色介電材料薄層；‧減薄所述介電材料阻擋層以暴露出銅通孔柱；‧施加端子；和‧將所述柵格切割成單獨的封裝晶片。
  20. 如權利要求19所述的方法，還包括鐳射標記所述黑色介電材料的附加步驟。
  21. 如權利要求19所述的方法，其中晶片陣列被定位在每個插座內。
  22. 如權利要求19所述的方法，其中其上具有晶片陣列的晶圓被定位在每個插座內。
  23. 如權利要求19所述的方法，其中所述通孔柱包括觸點柵格陣列LGA，其特徵在於以下限制條件中的至少其一：‧正方形或長方形的形狀； ‧外表面鍍有最終金屬鍍層，包括化學鍍鎳/化學鍍鈀/浸金(ENEPIG)或化學鍍鎳/浸金(ENIG)或電解鎳和金(Ni/Au)的端子化技術，以及‧任選從周圍介電材料突起至多10微米。
  24. 如權利要求19所述的方法，其中所述銅通孔柱包括球柵陣列BGA，其特徵在於以下限制條件中的至少其一：‧相對于周圍介電材料凹陷至多10微米；‧具有圓形端部的圓柱形狀，以易於被焊料潤濕；和‧塗有有機保焊劑OSP。
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