TWI584410B - 晶片封裝結構及其製造方法 - Google Patents
晶片封裝結構及其製造方法 Download PDFInfo
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Description
本發明係關於一種晶片封裝結構及其製造方法,且特別是關於一種具有多個半導體晶粒的晶片封裝結構及其製造方法。
晶片封裝結構不僅提供晶片對環境污染的防護,也提供封裝於其內的晶片的一連接介面。隨著小型電子產品需求成長,製造商及其他電子產業持續尋求縮小用於電子產品內積體電路的尺寸的方法。據此,已發展出三維積體電路封裝技術並開始實行。
堆疊封裝結構設計,例如堆疊式封裝層疊(package-on-package,以下簡稱為PoP)封裝技術已逐漸普及。顧名思義,PoP是半導體封裝的創新,其指將一封裝體堆疊(stacking)至另一封裝體的頂部。PoP裝置可做相互垂直結合,例如分離的記憶體(discrete memory)及邏輯封裝體。
現已發展出新的封裝技術以改善半導體裝置的密度(density)及功能。這些用於半導體裝置的相關的新式封裝技術面臨了製造上的挑戰。
根據一些實施例,本發明提供一種晶片封裝結
構。晶片封裝結構包括一第一封裝體,其包括至少一半導體晶粒、圍繞半導體晶粒的一介電結構以及穿過介電結構並圍繞半導體晶粒的複數導電結構。晶片封裝結構亦包括位於第一封裝體上方的一中介層基底以及位於中介層基底內或中介層基底上方的複數導電特徵部件。晶片封裝結構更包括位於中介層基底上方的一第二封裝體,且第一封裝體經由導電結構及導電特徵部件電性耦接第二封裝體。
根據一些實施例,本發明提供一種晶片封裝結構的製造方法。此方法包括提供一第一封裝體。第一封裝體包括至少一半導體晶粒、圍繞半導體晶粒的一介電結構、以及穿過介電結構並圍繞半導體晶粒的複數導電結構。此方法亦包括將一中介層基底接合至第一封裝體上方。此方法更包括將一第二封裝體接合至中介層基底上方。
10、20、30、40、50、60‧‧‧封裝結構
102、102’、122‧‧‧封裝體
103、124‧‧‧半導體晶粒
104、104’、105‧‧‧介電結構
106‧‧‧導電結構
108、126‧‧‧介電層
110、128‧‧‧重佈線層
112、116、116’、120、120’‧‧‧導電部件
114‧‧‧中介層基底
118‧‧‧導電特徵部件
502、504‧‧‧底膠材料
D1、D2‧‧‧距離
第1圖係繪示出根據一些實施例之封裝結構剖面示意圖。
第2圖係繪示出根據一些實施例之封裝結構剖面示意圖。
第3圖係繪示出根據一些實施例之封裝結構剖面示意圖。
第4圖係繪示出根據一些實施例之封裝結構剖面示意圖。
第5圖係繪示出根據一些實施例之封裝結構剖面示意圖。
第6圖係繪示出根據一些實施例之封裝結構剖面示意圖。
以下說明本發明實施例之製作與使用。然而,可輕易了解本發明實施例可實施於廣泛的各種特定背景。所揭示
的特定實施例僅僅用於說明以特定方法製作及使用本發明,並非用以侷限本發明的範圍。
要瞭解的是本說明書以下的揭露內容提供許多不同的實施例或範例,以實施本發明的不同特徵。而本說明書以下的揭露內容是敘述各個特徵部件及其排列方式的特定範例,以求簡化發明的說明。當然,這些特定的範例並非用以限定本發明。再者,在以下敘述提及在第二製程前進行第一製程,可包括第二製程於第一製程之後立刻進行之實施例,且亦可包括附加製程於第一製程與第二製程之間進行的實施例。為了簡化與清楚化,許多特徵部件可能被任意地繪製成不同的尺寸比例。再者,以下述及一第一特徵部件位於一第二特徵部件上或之上時,包括第一特徵部件與第二特徵部件直接接觸之實施例,且亦可包括附加特徵部件形成於第一特徵部件與第二特徵部件之間的實施例,使得第一特徵部件與第二特徵部件可能不彼此直接接觸。
以下說明實施例的不同變化。全文中圖式及實施例說明中使用相同或相似的標號來表示相同或相似的部件。
請參照第1圖,其繪示出根據一些實施例之封裝結構10剖面示意圖。提供一封裝體102。在一些實施例中,封裝體102包括至少一半導體晶粒,例如半導體晶粒103。封裝體102亦包括一介電結構104,其圍繞半導體晶粒103。封裝體102更包括一或多個導電結構106,其穿過介電結構104且圍繞半導體晶粒103。在一些實施例中,局部去除介電結構104以形成穿孔。之後,在穿孔內填入一或多個導電材料以形成導電結構
106。在一些實施例中,利用雷射鑽孔製程(laser drilling process)、光學微影(photolithography)及蝕刻製程(etching process)或其他合適製程或其組合來形成穿孔。
在一些實施例中,半導體晶粒103包括一或多個邏輯裝置。在一些實施例中,介電結構104包括一模塑成型材料(molding compound)。在一些實施例中,導電結構106由銅、鋁、鎢、鎳、鈦、金、鉑或其他合適的導電材料或其組合所構成。
如第1圖所示,根據一些實施例,封裝體102包括一介電層108及一重佈線層110,介電層108及重佈線層110位於介電結構104、導電結構106及半導體晶粒103下方。重佈線層110構成與導電結構106及與半導體晶粒103的接墊(未繪示)的電性連接。因此,半導體晶粒103的導電路徑係扇出(fan out)且引導至(led to)半導體晶粒103的相對側。在一些實施例中,使用多道沉積(multiple deposition)及圖案化製程(patterning process)以形成介電層108及重佈線層110。
在一些實施例中,介電層108包括多個堆疊層(stacked layer)。在一些實施例中,介電層108由聚醯亞胺(polyimide)、氧化矽、氮化矽、環氧樹脂基材料或其他適合的介電材料或其組合所構成。在一些實施例中,重佈線層110包括多個導電線及導電通孔(via)。在一些實施例中,重佈線層110由銅、鋁、鉑、鎢、鈦、鎳、金、或其他合適的導電材料或其組合所構成。
如第1圖所示,根據一些實施例,若干的導電部件
112形成於重佈線層110及介電層108下方。每一導電部件112電性連接於至少一重佈線層110。在一些實施例中,導電部件112由焊料材料所構成。在一些實施例中,導電部件112包括金屬柱(post)或金屬柱型體(pillar)。舉例來說,導電部件112包括銅柱及/或銅柱型體。在一些實施例中,藉由焊球植入(solder ball placement)製程、電鍍製程或其他合適的製程或其組合來形成導電部件112。
封裝體102可使用各種不同的方法來製作。在一些實施例中,利用晶圓級封裝製程(wafer-level packaging process)形成封裝體102。在一些實施例中,複數半導體晶粒放置於一承載基底上,例如玻璃晶圓、半導體晶圓等等。之後,在半導體晶粒及承載基底上方施加晶圓模塑材料以固定半導體晶粒。接著,介電層108及重佈線層110形成於半導體晶粒上方。重佈線層110對應並電性連接至半導體晶粒。導電部件112接著形成於重佈線層110上。之後,移除承載基底,並將另一承載體貼附至導電部件112。另一晶圓模塑材料可施加於半導體晶粒上以形成介電結構104。導電結構106接著形成於介電結構104內。之後,進行一切割製程(dicing process)以形成複數封裝體102。於變化實施例中,此階段亦可不進行切割製程。然而,可以理解的是本揭露並不局限於此。在一些實施例中,以不同的方式來進行晶圓級封裝製程。
如第1圖所示,根據一些實施例,一中介層基底114接合至封裝體102上方。在一些實施例中,中介層基底114未直接接觸封裝體102。在一些實施例中,中介層基底114與封裝體
102隔開。舉例來說,中介層基底114與封裝體102的上表面相隔一距離D1。距離D1在10微米至40微米的範圍。在其他一些實施例中,距離D1在15微米至30微米的範圍。在其他一些實施例中,中介層基底114由介電材料所構成。介電材料包括環氧樹脂、氰酸酯(cyanate ester)、聚醯亞胺、聚四氟乙烯(polytetrafluoroethylene)、烯丙基化聚苯醚(allylated polyphenylene ether)或其他合適的介電材料、或其組合。在一些實施例中,中介層基底114包括纖維散佈於介電材料內。舉例來說,將玻璃纖維加入於介電材料內。
如第1圖所示,根據一些實施例,藉由位於中介層基底114與封裝體102之間的複數導電部件116將中介層基底114接合至封裝體102上方。在一些實施例中,每一導電部件116電性連接於至少一導電結構106。在一些實施例中,導電部件116由一或多個焊料材料或其他合適的導電材料或其組合所構成。在一些實施例中,藉由焊球植入製程(solder ball placement process)、電鍍製程(plating process)、或其他合適的製程、或其組合來形成導電部件116。在一些實施例中,進行一回流製程(reflow process)以藉由導電部件116將中介層基底114與封裝體102接合。
如第1圖所示,根據一些實施例,複數導電特徵部件118形成於中介層基底114內及/或上方。導電特徵部件118提供設置於中介層基底114相對側(opposite side)上的部件電性連接之用。在一些實施例中,導電特徵部件118由銅、鋁、鎢、鈦、金、鉑、鎳或其他合適的導電材料或其組合所構成。在一
些實施例中,中介層基底114與導電特徵部件118一同構成一電路板。在一些實施例中,藉由一合適於形成印刷電路板的製程來形成中介層基底114與導電特徵部件118。然而,可理解的是本揭露並未侷限於此。在一些其他實施例中,可使用不同的材料及/或製程來形成中介層基底114與導電特徵部件118。
如第1圖所示,根據一些實施例,提供一封裝體122並接合至中介層基底114上方。在一些實施例中,封裝體122包括一半導體晶粒124。在一些實施例中,半導體晶粒124包括一或多個記憶體裝置。在一些實施例中,半導體晶粒124包括一或多個邏輯裝置。根據一些實施例,如第1圖所示,一介電層126及多個重佈線層128形成於半導體晶粒124下方。在一些實施例中,介電層126包括多個堆疊層。在一些實施例中,介電層126由聚醯亞胺、氧化矽、氮化矽、環氧樹脂基材料、或其他適合的介電材料、或其組合所構成。在一些實施例中,重佈線層128包括多個導電線及導電通孔。在一些實施例中,重佈線層128由銅、鋁、鉑、鎢、鈦、鎳、金、或其他合適的導電材料或其組合所構成。
本揭露的實施例具有許多不同的變化。舉例來說,並未侷限在將中介層基底114接合至封裝體102之後,將封裝體122接合至中介層基底114上方。在一些其他實施例中,封裝體122接合至中介層基底114上方。之後,中介層基底114接合至封裝體102上方。
在一些實施例中,中介層基底114未直接接觸封裝體122。在一些實施例中,中介層基底114與封裝體122隔開。
舉例來說,中介層基底114與封裝體122的下表面相隔一距離D2。距離D2在10微米至50微米的範圍。在一些實施例中,距離D2在15微米至40微米的範圍。在一些實施例中,距離D2大於距離D1。
如第1圖所示,根據一些實施例,藉由位於中介層基底114與封裝體122之間的複數導電部件120將封裝體122接合至中介層基底114上方。在一些實施例中,每一導電部件120電性連接於至少一導電特徵部件118。在一些實施例中,每一導電部件120穿過(penetrating through)介電結構104電性連接於至少一導電結構106。例如,每一導電部件120透過導電特徵部件118電性連接於至少一導電結構106。在一些實施例中,導電部件120由一或多個焊料材料或其他合適的導電材料或其組合所構成。在一些實施例中,藉由焊球植入製程、電鍍製程或其他合適的製程或其組合來形成導電部件120。在一些實施例中,進行一回流製程以藉由導電部件120將封裝體122與中介層基底114接合。
本發明的實施例利用中介層基底114於中介層基底114的相對側的封裝體102與122之間建構電性連接。在一些情形中,中介層基底114與封裝體102及/或封裝體122之間的接合不佳而必須進行重工(rework)製程。由於中介層基底114未直接接觸封裝體102及122兩者,因此能更輕易地進行重工製程。在重工製程期間可防止或明顯降低對封裝體102及122的損害。在一些實施例中,中介層基底114提供更堅固的機械性支撐。如此一來,能以更可靠的方式來進行製程,例如接合製程。
本發明的實施例具有許多變化。第2圖係繪示出根據一些實施例之封裝結構20剖面示意圖。封裝體20相似於第1圖所示的封裝結構10。提供相似於封裝體102的一封裝體102’。在一些實施例中,封裝體102’包括一介電結構105及一介電結構104’。如第2圖所示,介電結構105圍繞半導體晶粒103,且介電結構104’圍繞介電結構105及半導體晶粒103。在一些實施例中,介電材料104’及105的材質彼此不同。在一些實施例中,介電材料105由模塑成型材料(molding compound material)所構成。在一些實施例中,介電材料104’由相似於印刷電路板的材料所構成。在一些實施例中,局部去除一印刷電路板以形成一凹口(recess),接著在其中放置半導體晶粒103。之後,將一模塑成型材料施加於凹口內以形成介電材料105,其圍繞並覆蓋半導體晶粒103。
如第2圖所示,根據一些實施例,導電結構106形成於介電結構104’內。相似地,介電結構104’內的導電結構106用於封裝體102’與122之間的電性橋接。
本發明的實施例具有許多變化。第3圖係繪示出根據一些實施例之封裝結構30剖面示意圖。封裝體30相似於第1圖所示的封裝結構10。如第3圖所示,導電部件116’及120’用於將中介層基底114與封裝體102及122分別接合。在一些實施例中,導電部件116’包括金屬柱型體。舉例來說,金屬柱型體為銅柱型體。在一些實施例中,導電部件116’由不同於銅的金屬所構成。在一些實施例中,金屬柱型體透過接合材料接合至導電結構106。舉例來說,接合材料包括焊料材料。相似地,金
屬柱型體透過接合材料,例如焊料材料,接合至導電特徵部件118。
在一些實施例中,導電部件120’包括金屬柱型體。舉例來說,金屬柱型體為銅柱型體。在一些實施例中,導電部件120’由不同於銅的金屬所構成。在一些實施例中,金屬柱型體透過接合材料接合至重佈線層128。舉例來說,接合材料包括焊料材料。在一些實施例中,每一導電部件120’大於每一導電部件116’。
第4圖係繪示出根據一些實施例之封裝結構40剖面示意圖。封裝體40相似於第2圖所示的封裝結構20。相似於第3圖的實施例,根據一些實施例,導電部件116’及120’用於將中介層基底114與封裝體102及122接合,如第4圖所示。
本發明的實施例具有許多變化。第5圖係繪示出根據一些實施例之封裝結構50剖面示意圖。封裝體50相似於第1圖所示的封裝結構10。如第5圖所示,根據一些實施例,底膠材料502形成於中介層基底114與封裝體102之間。如第5圖所示,根據一些實施例,底膠材料504形成於中介層基底114與封裝體122之間。底膠材料502及504分別保護導電部件116及120。在一些實施例中,底膠材料502及504用以保護第3圖所示的導電部件116’及120’。
本發明的實施例具有許多變化。第6圖係繪示出根據一些實施例之封裝結構60剖面示意圖。封裝體60相似於第2圖所示的封裝結構20。如第6圖所示,根據一些實施例,底膠材料502形成於中介層基底114與封裝體102’之間。如第6圖所
示,根據一些實施例,底膠材料504形成於中介層基底114與封裝體122之間。底膠材料502及504分別保護導電部件116及120。在一些實施例中,底膠材料502及504用以保護第4圖所示的導電部件116’及120’。
本發明的實施例使用一中介層基底將二個或更多封裝體接合在一起。中介層基底於中介層基底相對側上的封裝體之間建構電性連接。中介層基底提供封裝體較大的製程容許度及較堅固的支撐。舉例來說,若有需要,可更容易地進行重工製程。如此一來,可明顯降低相關的製程成本及製程時間。
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作更動、替代與潤飾。舉例來說,任何所屬技術領域中具有通常知識者可輕易理解此處所述的許多特徵、功能、製程及材料可在本發明的範圍內作更動。再者,本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟,任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟,只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此,本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外,每一申請專利範圍構成個別的實施例,且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
10‧‧‧封裝結構
102、122‧‧‧封裝體
103、124‧‧‧半導體晶粒
104‧‧‧介電結構
106‧‧‧導電結構
108、126‧‧‧介電層
110、128‧‧‧重佈線層
112、116、120‧‧‧導電部件
114‧‧‧中介層基底
118‧‧‧導電特徵部件
D1、D2‧‧‧距離
Claims (19)
- 一種晶片封裝結構,包括:一第一封裝體,其中該第一封裝體包括:至少一半導體晶粒;一介電結構,圍繞該半導體晶粒;複數導電結構,穿過該介電結構且圍繞該半導體晶粒;以及一重佈線層,位於該介電結構、該等導電結構及該半導體晶粒下方;一中介層基底,位於該第一封裝體上方;複數導電特徵部件,位於該中介層基底內或位於該中介層基底上方;以及一第二封裝體,位於該中介層基底上方,其中該第一封裝體經由該等導電結構及該等導電特徵部件電性耦接該第二封裝體。
- 如申請專利範圍第1項所述之晶片封裝結構,其中該中介層基底與該第一封裝體隔開。
- 如申請專利範圍第2項所述之晶片封裝結構,更包括複數導電部件,位於該中介層基底與該第一封裝體之間,其中每一導電部件電性連接於至少一導電結構。
- 如申請專利範圍第3項所述之晶片封裝結構,其中該等導電部件包括一焊料材料。
- 如申請專利範圍第3項所述之晶片封裝結構,其中該等導電部件包括銅柱型體。
- 如申請專利範圍第3項所述之晶片封裝結構,更包括一底膠材料,位於該中介層基底與該第一封裝體之間且圍繞該等導電部件。
- 如申請專利範圍第3項所述之晶片封裝結構,其中該中介層基底與該第二封裝體隔開。
- 如申請專利範圍第7項所述之晶片封裝結構,更包括複數第二導電部件,位於該中介層基底與該第二封裝體之間,其中每一第二導電部件電性連接於至少一導電結構。
- 如申請專利範圍第8項所述之晶片封裝結構,其中該等第二導電部件包括焊料材料。
- 如申請專利範圍第8項所述之晶片封裝結構,其中該等第二導電部件包括銅柱型體。
- 如申請專利範圍第8項所述之晶片封裝結構,更包括一第二底膠材料,位於該中介層基底與該第一封裝體之間且圍繞該等第二導電部件。
- 如申請專利範圍第1項所述之晶片封裝結構,其中該第二封裝體包括至少一記憶體裝置。
- 如申請專利範圍第1項所述之晶片封裝結構,其中該第一封裝體包括至少一邏輯裝置。
- 如申請專利範圍第1項所述之晶片封裝結構,其中該介電結構包括一模塑成型材料。
- 如申請專利範圍第1項所述之晶片封裝結構,更包括一第二介電結構,圍繞該半導體晶粒,其中該介電結構圍繞該第二介電結構。
- 如申請專利範圍第15項所述之晶片封裝結構,其中該介電結構及該第二介電結構的材料彼此不同。
- 如申請專利範圍第16項所述之晶片封裝結構,其中該第二介電結構包括一模塑成型材料。
- 一種晶片封裝結構之製造方法,包括:一提供一第一封裝體,其中該第一封裝體包括:至少一半導體晶粒;一介電結構,圍繞該半導體晶粒;複數導電結構,穿過該介電結構且圍繞該半導體晶粒;以及一重佈線層,位於該介電結構、該等導電結構及該半導體晶粒下方;將一中介層基底接合至該第一封裝體上方,其中該中介層基底內或該中介層基底上方具有複數導電特徵部件;以及將一第二封裝體接合至該中介層基底上方,其中該第一封裝體經由該等導電結構及該等導電特徵部件電性耦接該第二封裝體。
- 如申請專利範圍第18項所述之晶片封裝結構之製造方法,其中該中介層基底通過複數第一導電部件接合至該第一封裝體上方,而該第二封裝體通過複數第二導電部件接合至該中介層基底上方。
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US10784206B2 (en) | 2015-09-21 | 2020-09-22 | Mediatek Inc. | Semiconductor package |
US9761534B2 (en) | 2015-09-21 | 2017-09-12 | Mediatek Inc. | Semiconductor package, semiconductor device using the same and manufacturing method thereof |
US9761535B1 (en) * | 2016-06-27 | 2017-09-12 | Nanya Technology Corporation | Interposer, semiconductor package with the same and method for preparing a semiconductor package with the same |
CN106558574A (zh) * | 2016-11-18 | 2017-04-05 | 华为技术有限公司 | 芯片封装结构和方法 |
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