CN105702648A - 芯片封装结构及其制造方法 - Google Patents
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Abstract
本发明提供一种芯片封装结构及其制造方法。该芯片封装结构包括︰第一封装体,其中,该第一封装体包括:至少一半导体晶片;介电结构,围绕该半导体晶片;以及多个导电结构,穿过该介电结构且围绕该半导体晶片;中介层基底,位于该第一封装体上方;多个导电特征元件,位于该中介层基底内或位于该中介层基底上方;以及第二封装体,位于该中介层基底上方,其中,该第一封装体经由该多个导电结构及该多个导电特征元件电性耦接该第二封装体。本发明提供的芯片封装结构及其制造方法可明显降低相关的制程成本及制程时间。
Description
【技术领域】
本发明关于芯片封装技术领域,特别关于一种芯片封装结构及其制造方法。
【背景技术】
芯片封装结构不仅提供芯片对环境污染的防护,也提供封装于其内的芯片的一连接接口。随着小型电子产品需求的成长,制造商及其他电子产业持续寻求缩小用于电子产品内集成电路的尺寸的方法。据此,已发展出三维集成电路封装技术并开始实行。
堆栈封装结构设计,例如堆栈式封装层迭(package–on-package,以下简称为PoP)封装技术已逐渐普及。顾名思义,PoP是半导体封装的创新,其指将一封装体堆栈(stacking)至另一封装体的顶部。PoP装置可做相互垂直结合,例如分离的内存(discretememory)及逻辑封装体。
现已发展出新的封装技术以改善半导体装置的密度(density)及功能。这些用于半导体装置的相关的新式封装技术面临了制造上的挑战。
【发明内容】
为了解决上述问题,本发明提出了一种芯片封装结构及其制造方法。
根据本发明的第一方面,提供一种芯片封装结构,包括︰第一封装体,其中,该第一封装体包括:至少一半导体晶片;介电结构,围绕该半导体晶片;以及多个导电结构,穿过该介电结构且围绕该半导体晶片;中介层基底,位于该第一封装体上方;多个导电特征元件,位于该中介层基底内或位于该中介层基底上方;以及第二封装体,位于该中介层基底上方,其中,该第一封装体经由该多个导电结构及该多个导电特征元件电性耦接该第二封装体。
根据本发明的第二方面,提供一种芯片封装结构的制造方法,包括︰提供第一封装体,其中该第一封装体包括:至少一半导体晶片;介电结构,围绕该半导体晶片;以及多个导电结构,穿过该介电结构且围绕该半导体晶片;将中介层基底接合至该第一封装体上方;以及将第二封装体接合至该中介层基底上方。
本发明提供的芯片封装结构及其制造方法可明显降低相关的制程成本及制程时间。
【附图说明】
图1是根据本发明实施例的封装结构剖面示意图。
图2是根据本发明实施例的封装结构剖面示意图。
图3是根据本发明实施例的封装结构剖面示意图。
图4是根据本发明实施例的封装结构剖面示意图。
图5是根据本发明实施例的封装结构剖面示意图。
图6是根据本发明实施例的封装结构剖面示意图。
【具体实施方式】
下面的描述是实施本发明的较佳预期模式。这种描述是为了说明本发明的一般原理的目的,而不应被理解成具有限制性的意义。但是应当理解,实施例可以利用软件、硬件、固件、或其任何组合来实现。
以下说明本发明实施例的制作与使用。然而,可轻易了解本发明实施例可实施于广泛的各种特定背景。所揭示的特定实施例仅仅用于说明以特定方法制作及使用本发明,并非用以局限本发明的范围。
要了解的是本说明书以下的揭露内容提供许多不同的实施例或范例,以实施本发明的不同特征。而本说明书以下的揭露内容是叙述各个特征元件及其排列方式的特定范例,以求简化发明的说明。当然,这些特定的范例并非用以限定本发明。再者,在以下叙述提及在第二制程前进行第一制程,可包括第二制程于第一制程之后立刻进行的实施例,且也可包括附加制程于第一制程与第二制程之间进行的实施例。为了简化与清楚化,许多特征元件可能被任意地绘制成不同的尺寸比例。再者,以下述及一第一特征元件位于一第二特征元件上或之上时,包括第一特征元件与第二特征元件直接接触的实施例,且也可包括附加特征元件形成于第一特征元件与第二特征元件之间的实施例,使得第一特征元件与第二特征元件可能不彼此直接接触。
以下说明实施例的不同变化。全文中图式及实施例说明中使用相同或相似的标号来表示相同或相似的元件。
请参考图1,其是根据本发明实施例的封装结构10剖面示意图。提供一封装体102。在一些实施例中,封装体102包括至少一半导体晶片,例如半导体晶片103。封装体102也包括一介电结构(dielectricstructure)104,其围绕半导体晶片103。封装体102更包括一或多个导电结构106,其穿过介电结构104且围绕半导体晶片103。在一些实施例中,局部去除介电结构104以形成穿孔(throughhole)。之后,在穿孔内填入一或多个导电材料以形成导电结构106。在一些实施例中,利用雷射钻孔制程(laserdrillingprocess)、光学微影(photolithography)及蚀刻制程(etchingprocess)或其他合适制程或其组合来形成穿孔。
在一些实施例中,半导体晶片103包括一或多个逻辑设备。在一些实施例中,介电结构104包括一模塑成型材料(moldingcompound)。在一些实施例中,导电结构106由铜、铝、钨、镍、钛、金、铂或其他合适的导电材料或其组合所构成。
如图1所示,根据一些实施例,封装体102包括一介电层108及一重布线层110,介电层108及重布线层110位于介电结构104、导电结构106及半导体晶片103下方。重布线层110构成与导电结构106及与半导体晶片103的接垫(未绘示)的电性连接。因此,半导体晶片103的导电路径是扇出(fanout)且引导至(ledto)半导体晶片103的相对侧。在一些实施例中,使用多道沉积(multipledeposition)及图案化制程(patterningprocess)以形成介电层108及重布线层110。
在一些实施例中,介电层108包括多个堆栈层(stackedlayer)。在一些实施例中,介电层108由聚酰亚胺(polyimide)、氧化硅、氮化硅、环氧树脂基材料或其他适合的介电材料或其组合所构成。在一些实施例中,重布线层110包括多个导电线及导电通孔(via)。在一些实施例中,重布线层110由铜、铝、铂、钨、钛、镍、金、或其他合适的导电材料或其组合所构成。
如图1所示,根据一些实施例,若干的导电元件112形成于重布线层110及介电层108下方。每一导电元件112电性连接于至少一重布线层110。在一些实施例中,导电元件112由焊料材料所构成。在一些实施例中,导电元件112包括金属柱(post)或金属柱型体(pillar)。举例来说,导电元件112包括铜柱及/或铜柱型体。在一些实施例中,通过焊球植入(solderballplacement)制程、电镀制程或其他合适的制程或其组合来形成导电元件112。
封装体102可使用各种不同的方法来制作。在一些实施例中,利用晶圆级封装制程(wafer-levelpackagingprocess)形成封装体102。在一些实施例中,多个半导体晶片放置于一承载基底上,例如:玻璃晶圆、半导体晶圆等等。之后,在半导体晶片及承载基底上方施加晶圆模塑材料以固定半导体晶片。接着,介电层108及重布线层110形成于半导体晶片上方。重布线层110对应并电性连接至半导体晶片。导电元件112接着形成于重布线层110上。之后,移除承载基底,并将另一承载体贴附至导电元件112。另一晶圆模塑材料可施加于半导体晶片上以形成介电结构104。导电结构106接着形成于介电结构104内。之后,进行一切割制程(dicingprocess)以形成多个封装体102。于变化实施例中,此阶段也可不进行切割制程。然而,可以理解的是本发明并不局限于此。在一些实施例中,可以不同的方式来进行晶圆级(waferlevel)封装制程。
如图1所示,根据一些实施例,中介层基底114接合至封装体102上方。在一些实施例中,中介层基底114未直接接触封装体102。在一些实施例中,中介层基底114与封装体102隔开。举例来说,中介层基底114与封装体102的上表面相隔一距离D1。距离D1在10微米至40微米的范围。在其他一些实施例中,距离D1在15微米至30微米的范围。在其他一些实施例中,中介层基底114由介电材料所构成。介电材料包括环氧树脂、氰酸酯(cyanateester)、聚酰亚胺、聚四氟乙烯(polytetrafluoroethylene)、烯丙基化聚苯醚(allylatedpolyphenyleneether)或其他合适的介电材料、或其组合。在一些实施例中,中介层基底114包括纤维散布于介电材料内。举例来说,将玻璃纤维加入于介电材料内。
如图1所示,根据一些实施例,通过位于中介层基底114与封装体102之间的多个导电元件116将中介层基底114接合至封装体102上方。在一些实施例中,每一导电元件116电性连接于至少一导电结构106。在一些实施例中,导电元件116由一或多个焊料材料或其他合适的导电材料或其组合所构成。在一些实施例中,通过焊球植入制程(solderballplacementprocess)、电镀制程(platingprocess)、或其他合适的制程、或其组合来形成导电元件116。在一些实施例中,进行一回流制程(reflowprocess)以通过导电元件116将中介层基底114与封装体102接合。
如图1所示,根据一些实施例,多个导电特征元件118形成于中介层基底114内及/或上方。导电特征元件118提供设置于中介层基底114相对侧(oppositeside)上的元件电性连接之用。在一些实施例中,导电特征元件118由铜、铝、钨、钛、金、铂、镍或其他合适的导电材料或其组合所构成。在一些实施例中,中介层基底114与导电特征元件118一同构成一电路板。在一些实施例中,通过一合适于形成印刷电路板的制程来形成中介层基底114与导电特征元件118。然而,可理解的是本发明并未局限于此。在一些其他实施例中,可使用不同的材料及/或制程来形成中介层基底114与导电特征元件118。
如图1所示,根据一些实施例,提供一封装体122并接合至中介层基底114上方。在一些实施例中,封装体122包括一半导体晶片124。在一些实施例中,半导体晶片124包括一或多个内存装置。在一些实施例中,半导体晶片124包括一或多个逻辑设备。根据一些实施例,如图1所示,一介电层126及多个重布线层128形成于半导体晶片124下方。在一些实施例中,介电层126包括多个堆栈层。在一些实施例中,介电层126由聚酰亚胺、氧化硅、氮化硅、环氧树脂基材料、或其他适合的介电材料、或其组合所构成。在一些实施例中,重布线层128包括多个导电线及导电通孔。在一些实施例中,重布线层128由铜、铝、铂、钨、钛、镍、金、或其他合适的导电材料或其组合所构成。
本发明的实施例具有许多不同的变化。举例来说,并未局限在将中介层基底114接合至封装体102之后,将封装体122接合至中介层基底114上方。在一些其他实施例中,封装体122接合至中介层基底114上方。之后,中介层基底114接合至封装体102上方。
在一些实施例中,中介层基底114未直接接触封装体122。在一些实施例中,中介层基底114与封装体122隔开。举例来说,中介层基底114与封装体122的下表面相隔一距离D2。距离D2在10微米至50微米的范围。在一些实施例中,距离D2在15微米至40微米的范围。在一些实施例中,距离D2大于距离D1。
如图1所示,根据一些实施例,通过位于中介层基底114与封装体122之间的多个导电元件120将封装体122接合至中介层基底114上方。在一些实施例中,每一导电元件120电性连接于至少一导电特征元件118。在一些实施例中,每一导电元件120穿过(penetratingthrough)介电结构104电性连接于至少一导电结构106。例如,每一导电元件120透过导电特征元件118电性连接于至少一导电结构106。在一些实施例中,导电元件120由一或多个焊料材料或其他合适的导电材料或其组合所构成。在一些实施例中,通过焊球植入制程、电镀制程或其他合适的制程或其组合来形成导电元件120。在一些实施例中,进行一回流制程以通过导电元件120将封装体122与中介层基底114接合。
本发明的实施例利用中介层基底114于中介层基底114的相对侧的封装体102与122之间建构电性连接。在一些情形中,中介层基底114与封装体102及/或封装体122之间的接合不佳而必须进行重工(rework)制程。由于中介层基底114未直接接触封装体102及122两者,因此能更轻易地进行重工制程。在重工制程期间可防止或明显降低对封装体102及122的损害。在一些实施例中,中介层基底114提供更坚固的机械性支撑。如此一来,能以更可靠的方式来进行制程,例如接合制程。
本发明的实施例具有许多变化。图2是根据本发明实施例的封装结构20剖面示意图。封装体20相似于图1所示的封装结构10。提供相似于封装体102的一封装体102’。在一些实施例中,封装体102’包括一介电结构105及一介电结构104’。如图2所示,介电结构105围绕半导体晶片103,且介电结构104’围绕介电结构105及半导体晶片103。在一些实施例中,介电材料104’及105的材质彼此不同。在一些实施例中,介电材料105由模塑成型材料(moldingcompoundmaterial)所构成。在一些实施例中,介电材料104’由相似于印刷电路板的材料所构成。在一些实施例中,局部去除一印刷电路板以形成凹口(recess),接着在其中放置半导体晶片103。之后,将一模塑成型材料施加于凹口内以形成介电材料105,其围绕并覆盖半导体晶片103。
如图2所示,根据一些实施例,导电结构106形成于介电结构104’内。相似地,介电结构104’内的导电结构106用于封装体102’与122之间的导电桥(conductivebridge)。
本发明的实施例具有许多变化。图3是根据本发明实施例的封装结构30剖面示意图。封装体30相似于图1所示的封装结构10。如图3所示,导电元件116’及120’用于将中介层基底114与封装体102及122分别接合。在一些实施例中,导电元件116’包括金属柱型体。举例来说,金属柱型体为铜柱型体。在一些实施例中,导电元件116’由不同于铜的金属所构成。在一些实施例中,金属柱型体透过接合材料接合至导电结构106。举例来说,接合材料包括焊料材料。相似地,金属柱型体透过接合材料,例如焊料材料,接合至导电特征元件118。
在一些实施例中,导电元件120’包括金属柱型体。举例来说,金属柱型体为铜柱型体。在一些实施例中,导电元件120’由不同于铜的金属所构成。在一些实施例中,金属柱型体透过接合材料接合至重布线层128。举例来说,接合材料包括焊料材料。在一些实施例中,每一导电元件120’大于每一导电元件116’。
图4是根据本发明实施例的封装结构40剖面示意图。封装体40类似于图2所示的封装结构20。类似于图3的实施例,根据一些实施例,导电元件116’及120’用于将中介层基底114与封装体102及122接合,如图4所示。
本发明的实施例具有许多变化。图5是根据本发明实施例的封装结构50剖面示意图。封装体50相似于图1所示的封装结构10。如图5所示,根据一些实施例,底胶材料502形成于中介层基底114与封装体102之间。如图5所示,根据一些实施例,底胶材料504形成于中介层基底114与封装体122之间。底胶材料502及504分别保护导电元件116及120。在一些实施例中,底胶材料502及504用以保护图3所示的导电元件116’及120’。
本发明的实施例具有许多变化。图6是根据本发明实施例的封装结构60剖面示意图。封装体60相似于图2所示的封装结构20。如图6所示,根据一些实施例,底胶材料502形成于中介层基底114与封装体102’之间。如图6所示,根据一些实施例,底胶材料504形成于中介层基底114与封装体122之间。底胶材料502及504分别保护导电元件116及120。在一些实施例中,底胶材料502及504用以保护图4所示的导电元件116’及120’。
本发明的实施例使用一中介层基底将二个或更多封装体接合在一起。中介层基底于中介层基底相对侧上的封装体之间建构电性连接。中介层基底提供封装体较大的制程容许度及较坚固的支撑。举例来说,若有需要,可更容易地进行重工制程。如此一来,可明显降低相关的制程成本及制程时间。
虽然本发明已以较佳实施例揭露如上,然其并非用以限定本发明,任何所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,当可作更动、替代与润饰。举例来说,任何所属技术领域中具有通常知识者可轻易理解此处所述的许多特征、功能、制程及材料可在本发明的范围内作更动。再者,本发明的保护范围并未局限于说明书内所述特定实施例中的制程、机器、制造、物质组成、装置、方法及步骤,任何所属技术领域中具有通常知识者可从本发明揭示内容中理解现行或未来所发展出的制程、机器、制造、物质组成、装置、方法及步骤,只要可以在此处所述实施例中实施大体相同功能或获得大体相同结果皆可使用于本发明中。因此,本发明的保护范围包括上述制程、机器、制造、物质组成、装置、方法及步骤。另外,每一申请专利范围构成个别的实施例,且本发明的保护范围也包括各个申请专利范围及实施例的组合。
本发明虽以较佳实施例揭露如上,然其并非用以限定本发明的范围,任何本领域技术人员,在不脱离本发明的精神和范围内,当可做些许的更动与润饰,因此本发明的保护范围当视权利要求所界定者为准。
Claims (18)
1.一种芯片封装结构,其特征在于,包括︰
第一封装体,其中,该第一封装体包括:
至少一半导体晶片;
介电结构,围绕该半导体晶片;以及
多个导电结构,穿过该介电结构且围绕该半导体晶片;
中介层基底,位于该第一封装体上方;
多个导电特征元件,位于该中介层基底内或位于该中介层基底上方;以及
第二封装体,位于该中介层基底上方,其中,该第一封装体经由该多个导电结构及该多个导电特征元件电性耦接该第二封装体。
2.如权利要求1所述的芯片封装结构,其特征在于,该中介层基底与该第一封装体隔开。
3.如权利要求2所述的芯片封装结构,其特征在于,进一步包括多个导电元件,位于该中介层基底与该第一封装体之间,其中每一导电元件电性连接于至少一导电结构。
4.如权利要求3所述的芯片封装结构,其特征在于,该多个导电元件包括焊料材料或铜柱型体。
5.如权利要求3所述的芯片封装结构,其特征在于,进一步包括底胶材料,位于该中介层基底与该第一封装体之间且围绕该多个导电元件。
6.如权利要求3所述的芯片封装结构,其特征在于,该中介层基底与该第二封装体隔开。
7.如权利要求6所述的芯片封装结构,其特征在于,进一步包括多个第二导电元件,位于该中介层基底与该第二封装体之间,其中,每一第二导电元件电性连接于至少一导电结构。
8.如权利要求7所述的芯片封装结构,其特征在于,该多个第二导电元件包括焊料材料或铜柱型体。
9.如权利要求7所述的芯片封装结构,其特征在于,进一步包括第二底胶材料,位于该中介层基底与该第一封装体之间且围绕该多个第二导电元件。
10.如权利要求1所述的芯片封装结构,其特征在于,该第二封装体包括至少一内存装置。
11.如权利要求1所述的芯片封装结构,其特征在于,该第一封装体包括至少一逻辑设备。
12.如权利要求1所述的芯片封装结构,其特征在于,该介电结构包括一模塑成型材料。
13.如权利要求1所述的芯片封装结构,其特征在于,进一步包括第二介电结构,围绕该半导体晶片,其中该介电结构围绕该第二介电结构。
14.如权利要求13所述的芯片封装结构,其特征在于,该介电结构及该第二介电结构的材料彼此不同。
15.如权利要求14所述的芯片封装结构,其特征在于,该第二介电结构包括一模塑成型材料。
16.如权利要求1所述的芯片封装结构,其特征在于,进一步包括重布线层,位于该介电结构、该多个导电结构及该半导体晶片下方。
17.一种芯片封装结构的制造方法,其特征在于,包括︰
提供第一封装体,其中该第一封装体包括:
至少一半导体晶片;
介电结构,围绕该半导体晶片;以及
多个导电结构,穿过该介电结构且围绕该半导体晶片;
将中介层基底接合至该第一封装体上方;以及
将第二封装体接合至该中介层基底上方。
18.如权利要求17所述的芯片封装结构的制造方法,其特征在于,该中介层基底通过多个第一导电元件接合至该第一封装体上方,而该第二封装体通过多个第二导电元件接合至该中介层基底上方。
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CN106558574A (zh) * | 2016-11-18 | 2017-04-05 | 华为技术有限公司 | 芯片封装结构和方法 |
CN107546215A (zh) * | 2016-06-27 | 2018-01-05 | 南亚科技股份有限公司 | 中介物、其半导体封装及其半导体封装的制备方法 |
CN115332214A (zh) * | 2022-10-14 | 2022-11-11 | 北京华封集芯电子有限公司 | 一种用于芯片封装的中介层及制作方法 |
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KR20150091932A (ko) * | 2014-02-04 | 2015-08-12 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스 |
KR101640341B1 (ko) * | 2015-02-04 | 2016-07-15 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 |
US9761534B2 (en) | 2015-09-21 | 2017-09-12 | Mediatek Inc. | Semiconductor package, semiconductor device using the same and manufacturing method thereof |
US10784206B2 (en) | 2015-09-21 | 2020-09-22 | Mediatek Inc. | Semiconductor package |
KR102086364B1 (ko) * | 2018-03-05 | 2020-03-09 | 삼성전자주식회사 | 반도체 패키지 |
KR102448248B1 (ko) * | 2018-05-24 | 2022-09-27 | 삼성전자주식회사 | Pop형 반도체 패키지 및 그 제조 방법 |
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CN115332214A (zh) * | 2022-10-14 | 2022-11-11 | 北京华封集芯电子有限公司 | 一种用于芯片封装的中介层及制作方法 |
Also Published As
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TWI584410B (zh) | 2017-05-21 |
US10354974B2 (en) | 2019-07-16 |
EP3032582A2 (en) | 2016-06-15 |
EP3032582A3 (en) | 2016-07-27 |
US20160172334A1 (en) | 2016-06-16 |
TW201622065A (zh) | 2016-06-16 |
CN105702648B (zh) | 2018-12-21 |
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