TWI781101B - 包括互連結構之半導體系統及裝置封裝 - Google Patents

包括互連結構之半導體系統及裝置封裝 Download PDF

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TWI781101B
TWI781101B TW106115640A TW106115640A TWI781101B TW I781101 B TWI781101 B TW I781101B TW 106115640 A TW106115640 A TW 106115640A TW 106115640 A TW106115640 A TW 106115640A TW I781101 B TWI781101 B TW I781101B
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glass substrate
conductive
interconnect structure
hole
diameter
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TW201834174A (zh
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陳建樺
德章 李
張勇舜
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日月光半導體製造股份有限公司
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Abstract

本發明提供一種半導體裝置封裝，其包括：一半導體晶片；一玻璃基板，其具有面向該半導體晶片之一第一表面及與該第一表面對置之一第二表面，該玻璃基板界定自該第一表面貫穿該玻璃基板至該第二表面的一孔；一互連結構，其安置於該孔中；及一導電凸塊，其鄰近該互連結構安置且自該第二表面突出，其中該導電凸塊及該互連結構包括一相同材料。

Description

包括互連結構之半導體系統及裝置封裝
插入件已用在封裝積體電路(IC)中，充當可用以實施三維(3D)或二點五維(2.5D)積體電路或封裝上系統(system on package，SoP)平台的微型化印刷電路板(PCB)。矽穿孔(TSV)可在安裝於插入件之對置側上的晶粒之間提供穿過插入件的路由路徑。插入件可由玻璃製成。玻璃穿孔(TGV)可形成於玻璃插入件中，以在焊料凸塊及半導體晶片安裝於插入件之對置側上時將焊料凸塊電連接至半導體晶片。TGV可藉由將銅電鍍至玻璃基板的孔中而形成。然而，此電鍍製程可能效率低下。另外，在電鍍製程期間，尤其當孔之縱橫比(亦即，深度與寬度之比率)大時，可能形成空隙(例如，填充該孔之材料中的間隙)。因此，需要提供針對以上問題的解決方案。
在一些實施例中，根據一個態樣，一種半導體裝置封裝包括：一半導體晶片；一玻璃基板，其具有面向該半導體晶片之一第一表面及與該第一表面對置之一第二表面，該玻璃基板界定自該第一表面貫穿該玻璃基板至該第二表面的一孔；一互連結構，其安置於該孔中；及一導電凸塊，其鄰近該互連結構安置且自該第二表面突出，其中該導電凸塊及該互連結構包括一相同的材料。 在一些實施例中，根據另一態樣，一種半導體裝置封裝包括：一玻璃基板，其具有一第一表面及與該第一表面對置之一第二表面，該玻璃基板界定貫穿該玻璃基板的一孔且包含在該第一表面上之具有一第一直徑的一第一開口及在該第二表面上之具有一第二直徑的一第二開口；及一互連結構，其安置於該孔中，其中該第二直徑大於該第一直徑。 在一些實施例中，根據另一態樣，一種用於形成一互連結構之系統包括：一基板，其界定形成於該基板之一表面中之複數個孔；及一注入裝置，其安置於該基板上方，該注入裝置包括：一槽，其經組態以裝載有一導電材料；一泵送頭，其鄰近該槽之一頂部安置；及一填充頭，其鄰近該槽之一底部安置且經組態以填充該複數個孔之一選定孔以形成一互連結構，其中該泵送頭經組態以將氣體泵送至該槽中且藉此將該導電材料推入該選定孔中。
以下揭示內容提供用於實施本文中所描述的標的物之不同特徵的許多不同實施例或實例。下文出於解釋性目的描述組件之具體實例及組件之配置。所描述之組件及組件之配置係實例，且並不意欲為限制性的。舉例而言，在以下描述中對第一特徵形成於第二特徵上方或之上的描述可指代第一特徵與第二特徵直接接觸而形成的實施例，且亦可指代額外特徵可形成或安置於第一特徵與第二特徵之間以使得第一特徵與第二特徵可不直接接觸的實施例。另外，參考數字及/或字母可在下文提供之各種實例中重複。此重複係出於論述之目的，且意在促進簡單性及清晰度，而其自身並不指示所論述之各種實施例及/或組態之間的關係。 下文詳細論述本發明之實施例。然而，應瞭解，本發明之標的物可在廣泛多種情形下實施。所論述具體實施例僅為說明性的，且並不限制本發明之範疇。 此外，諸如「下方」、「以下」、「下部」、「以上」、「上部」、「高於」、「左」、「右」及其類似者之空間相對術語可在本文中為便於描述用於描述圖式中所說明之一個元件或特徵相對另外一或多個元件或特徵的關係。除圖式中所描繪之定向以外，空間相對術語意欲涵蓋裝置在使用或操作中之不同定向。設備可以其他方式定向(例如，旋轉90度或處於其他定向)，且本文中所使用之空間相對描述詞可同樣相應地予以解釋。應理解，當元件被稱作「連接至」或「耦接至」另一元件時，其可直接連接至或耦接至該另一元件，或該等連接的或耦接的元件之間可存在介入元件。 圖1為根據一些實施例之說明半導體裝置封裝100之一部分的橫截面圖。裝置封裝100為3D或2.5D封裝上系統(SoP)總成。半導體裝置封裝100包括玻璃基板102、整合被動裝置(IPD)結構104及半導體晶片106。玻璃基板102具有面向半導體晶片106之第一表面108及與第一表面108對置之第二表面110。IPD結構104安置於玻璃基板102與半導體晶片106之間。至少一個孔112係由玻璃基板102界定。具體言之，孔112自第一表面108貫穿玻璃基板102至第二表面110。互連結構114安置於孔112中。可與互連結構114相連之導電凸塊116自玻璃基板102突出(例如，導電凸塊116鄰近互連結構114安置且自玻璃基板102之第二表面110突出)。根據一些實施例，導電凸塊116係連續地連接至互連結構114。舉例而言，導電凸塊116與互連結構114可彼此一體地形成為單體結構。導電凸塊116及互連結構114可由相同材料或類似材料構成。舉例而言，導電凸塊116及互連結構114之材料可包括錫(Sn)或錫(Sn)與銀(Ag)之合金。導電凸塊116及互連結構114之材料可包括磁材料。在一些實施例中，玻璃基板102可置換為矽、SiO2 及/或其他矽基基板。 IPD結構104安置於玻璃基板102之第一表面108上。半導體晶片106安置於IPD結構104上。根據一些實施例，至少一個接合線118經配置以電連接半導體晶片106與IPD結構104。一些實施例不包括接合線118，且電連接可改為經由倒裝晶片實施而作出。舉例而言，IPD結構104可包括高密度溝槽電容器、金屬-絕緣體-金屬(MIM)電容器、電阻器、高Q電感器、PIN二極體或曾納(Zener)二極體。此等裝置及組件及半導體晶片106可整合於一個封裝中，此可幫助增大系統之功能可靠度。 根據一些實施例，孔112具有第一開口120 (其具有由第一表面108界定之第一直徑D1)及第二開口122 (其具有由第二表面110界定之第二直徑D2)，且第二直徑D2大於第一直徑D1。舉例而言，D2可比D1的約1.1倍大，或比D1的約1.2倍大。另外，孔112之直徑沿著自第二開口122至第一開口120之方向逐漸減小或單調減小。然而，並非所有實施例展現此特徵。根據一些實施例，第二直徑D2可實質上等於第一直徑D1。雖然圖1中所描繪的及本文中所描述的孔在橫截面形狀上大致為圓形，但在其他實施例中，該孔不必為圓形，且可為例如任何橢圓或多邊形形狀。此外，雖然此處使用術語「直徑」，但對於孔並非圓形之實施例，術語「寬度」或「最大寬度」可在適當時取代「直徑」。 根據一些實施例，孔112具有所量測之自第一開口120至第二開口122的深度D3，且深度D3與第二直徑D2之比率介於約5至約50的範圍內。孔112之此縱橫比與其他TGV相比相對較大。 另外，根據一些實施例，導電凸塊116之最大寬度大於第二直徑D2。具體言之，當導電凸塊116自玻璃基板102之第二表面110突出時，導電凸塊116具有與第二表面110直接接觸且黏接之平坦表面126，且平坦表面126具有大於第二直徑D2的寬度W。視實務實施而定，寬度W可為導電凸塊116之最大寬度。 孔112可經填充以形成互連結構114。根據一些實施例，互連結構114與孔112之內表面124直接接觸且黏接。藉由使用下文所描述之TGV形成方法以填充孔112從而形成互連結構114，可填充孔112，且空隙形成於互連結構114中之機會會減小。因此，與藉由電鍍製程形成之其他TGV的可靠度相比，本文中所描述之TGV的可靠度及TGV形成製程的可靠度得以改良。 圖2為根據一些實施例之說明互連結構202及導電凸塊204的圖。在所描繪之實施例中，由玻璃基板212界定之孔206自玻璃基板212的第一表面208貫穿玻璃基板212至玻璃基板212的第二表面210。孔206具有實質上恆定的直徑D4。互連結構202係連續地連接至導電凸塊204。導電凸塊204自玻璃基板212之第一表面208突出。導電凸塊204可具有大致半球形的形狀。導電凸塊204之一部分具有寬度W1，該部分之至少一部分與玻璃基板212之第一表面208直接接觸且黏接至該第一表面。在所描繪之實施例中，玻璃基板212之第一表面208曝露，除與導電凸塊204接觸的一部分以外。然而，在其他實施例中，第一表面208之其他部分或全部可不曝露。 圖3為根據一些實施例之說明互連結構302及導電凸塊304的圖。在所描繪之實施例中，由玻璃基板312界定之孔306自玻璃基板312的第一表面308貫穿玻璃基板312至玻璃基板312的第二表面310。孔306具有實質上恆定的直徑D5。互連結構302係連續地連接至導電凸塊304。導電凸塊304自玻璃基板312之第一表面308突出，且導電凸塊304可具有大致半球形形狀。導電凸塊304之一部分具有寬度W2，該部分之至少一部分與玻璃基板312之第一表面308直接接觸且黏接至該第一表面。在所描繪之實施例中，鈍化層314安置於第一表面308之未被導電凸塊304覆蓋的一部分上方或與該部分接觸。鈍化層314為絕緣層。導電凸塊304具有第一高度H1 (例如，所量測之自半球形導電凸塊304之平坦表面至對置彎曲表面的最大高度)，且鈍化層314具有第二高度H2，其自鈍化層314之與第一表面308接觸的第一表面鈍化層314之與鈍化層314的第一表面對置之第二表面而量測得。在所描繪之實施例中，第一高度H1大於第二高度H2。然而，在其他實施例中，第二高度H2可與第一高度H1相同或大於該第一高度。 圖4為根據一些實施例之說明互連結構402及導電凸塊404的圖。由玻璃基板412界定之孔406自玻璃基板412之第一表面408貫穿玻璃基板412至玻璃基板412的第二表面410。孔406具有實質上恆定的直徑D6。互連結構402係連續地連接至導電凸塊404。鈍化層414安置於玻璃基板412之第一表面408上。鈍化層414界定具有寬度416之開口，使得鈍化層414並未安置於孔406上方。寬度416大於孔406之直徑D6。鈍化層414具有與玻璃基板412之第一表面408接觸的第一表面，及與鈍化層414之第一表面對置的第二表面418。導電凸塊404經配置以自玻璃基板412之第一表面408突出且進一步自鈍化層414之第二表面418突出。導電凸塊404之第一部分具有寬度W3，其至少一部分直接接觸鈍化層414之第二表面418且黏接至該第二表面。導電凸塊404之第二部分具有等於寬度416的寬度，該第二部分之至少一部分直接接觸玻璃基板412的第一表面408且黏接至該第一表面。 圖5為根據一些實施例之展示形成半導體裝置封裝的方法500之操作的流程圖。在操作502中，提供界定複數個孔604的玻璃基板602，如圖6中所描繪。玻璃基板602具有第一表面606及與第一表面606對置之第二表面608，且孔604中之每一者在第一表面606處具有第一開口610 (其具有第一直徑d1)。根據一些實施例,孔604中之每一者具有楔形化形狀。每一孔604之第一開口610處的第一直徑d1是每一孔604之最大直徑。換言之，每一孔604在第一表面606處最寬。孔604之深度為d2，其在自第一表面606朝向第二表面608之方向上測得。孔604並不貫穿玻璃基板602之全部(例如，不到達第二表面608)。根據一些實施例，深度d2與第一直徑d1之比率係介於約5至約50之範圍內。 在操作504中，光阻層702被圖案化於玻璃基板602之第一表面606上，如圖7中所描繪。根據一些實施例，由光阻層702界定之對應於孔604的複數個開口704形成於光阻層702中，且可分別曝露孔604。光阻層702之每一開口704的直徑可大於對應之孔604的對應第一直徑d1。接著，導電材料經由光阻層702之開口704泵送至孔604中以在近真空環境(例如，壓力低之環境，諸如約10- 1 帕斯卡或以下、約10- 3 帕斯卡或以下、約10- 5 帕斯卡或以下、或約10- 7 帕斯卡或以下，或其中顆粒計數低)中形成複數個互連結構706。導電材料被泵送且溢出孔604及光阻層702之開口704，從而形成複數個導電凸塊708。由於互連結構706係藉由在近真空環境中將導電材料泵送至孔604而形成，因此導電材料可更完全填充孔604。該真空填充有助於防止空隙在形成製程期間形成於互連結構706中，如下文參考圖14更詳細地描述。 在操作506中，光阻層702經移除以曝露玻璃基板602之第一表面606及導電凸塊708，如圖8中所描繪。接著，黏接層802安置於玻璃基板602之第一表面606及導電凸塊708上方。根據一些實施例，黏接層802經配置以覆蓋導電凸塊708；在其他實施例中，導電凸塊708中之至少一者保留曝露。接著，載體804黏接至黏接層802以便承載且翻轉玻璃基板602。 根據一些實施例，互連結構706及導電凸塊708係藉由單個泵送製程形成。此有助於使本發明方法500成為形成半導體裝置封裝之相對流線型方法。 另外，因為導電凸塊708之直徑大於對應之互連結構706的直徑，所以對應導電凸塊708具有更大接觸面積以連接至外部墊。根據一些實施例，導電凸塊708之直徑可藉由選擇光阻層702之對應開口704的直徑來調試性地調整。 在操作508中，玻璃基板602藉由載體804翻轉，且玻璃基板602在第二表面608處經薄化(材料被移除)以形成第三表面902，如圖9中所描繪。第三表面902上之複數個第二開口904分別曝露互連結構706之底部部分。第二開口904中之每一者可具有第二直徑d3。由於孔604被楔形化，因此第二開口904之第二直徑d3小於第一開口610之第一直徑d1。薄化玻璃基板602現具有厚度d4。厚度d4小於深度d2。然而，厚度d4與第一直徑d1之比率可仍介於約5至約50之範圍內。 在操作510中，複數個被動裝置1008及導電結構1006形成於玻璃基板602之第三表面902上，如圖10中所描繪。導電結構1006分別經安置以使得其覆蓋玻璃基板602之各別開口904。被動裝置1008經安置以使得每一被動裝置1008與至少一個導電結構1006電接觸。被動裝置1008由第一鈍化層1002分隔開。鈍化層1002安置於第三表面902之至少一部分上，且可覆蓋至少一個導電結構1006之至少一部分，且可覆蓋至少一個被動裝置1008之至少一部分。複數個孔1004形成於第一鈍化層1002中。孔1004經安置使得至少一個導電結構1006或一個被動裝置1008之至少一部分曝露於每一孔1004之底部。舉例而言，被動裝置1008可為一或多個高密度溝槽電容器、MIM電容器、電阻器、高Q電感器、PIN二極體或曾納二極體。在所描繪之實施例中，MIM電容器1008形成於玻璃基板602上方，且MIM電容器1008經由對應之導電結構1006電連接至互連結構706。 在操作512中，複數個導電通孔1102分別形成於孔1004中，如圖11中所描繪。接著，複數個重佈層(RDL) 1104分別形成於導電通孔1102上。複數個導電墊1106形成於重佈層1104之至少一些上。另外，第二鈍化層1108安置於第一鈍化層1002之至少一部分上。導電通孔1102及重佈層1104之材料可包括鋁(Al)。因此，IPD結構在操作510及512中形成。 在操作514中，將半導體晶片1202附接至第二鈍化層1108，如圖12中所描繪，且執行晶圓級晶片至晶圓線接合製程。在該線接合製程期間，複數個接合線1204經配置以將半導體晶片1202與導電墊1106電連接。 在操作516中，執行晶圓級模製製程，如圖13中所描繪。在該模製製程期間，絕緣模製化合物1302安置於第二鈍化層1108上且覆蓋半導體晶片1202及接合線1204。接著，載體804被釋離且黏接層802被移除。當黏接層802被移除時，曝露導電凸塊708。根據一些實施例，導電凸塊708可經受回焊製程以用於連接至另一電路板。在其他實施例中，導電凸塊708不經受回焊製程。由於導電凸塊708藉由移除黏接層802而曝露，因此不必執行焊料球成形製程。因此，半導體裝置封裝之成本得以減小，且半導體裝置封裝之良品率及UPH (每小時單元)得以改良。 根據一些實施例，在操作504中，導電材料可藉由注入裝置泵送至孔604中以形成互連結構706。圖14為根據一些實施例之說明用於形成互連結構之系統的圖。根據一些實施例，注入裝置1400安置於玻璃基板1402及光阻層1406上方。玻璃基板1402及光阻層1406界定複數個孔1404。藉由光刻製程，光阻層1406可被圖案化以界定分別對應於孔1404之複數個開口1408。注入裝置1400包括槽1410、填充頭或機構1412、泵送頭或機構1414及真空頭或機構1416。槽1410填充有導電材料1418，諸如焊料。填充頭1412鄰近槽1410安置之底部且鄰近選定孔1404安置之開口1408中的至少一者。泵送頭1414鄰近於槽1410安置之頂部。諸如氮氣之氣體經由泵送頭1414被泵送至槽1410中且將導電材料1418推入選定孔1404中。注入裝置1400可遵循預定方向1420以一個接一個將導電材料1418泵送至孔1404中。真空頭1416經定位在方向1420上比槽1410遠。因此，真空頭1416經配置以首先將空氣抽取出選定孔1404，使選定孔1404變為真空或近真空。接著，後繼填充頭1412可在近真空環境中將導電材料1418注入選定孔1404中。根據一些實施例，導電材料1418經泵送以溢出光阻層1406之孔1404及開口1408以形成複數個導電凸塊1422。由於互連結構1424係藉由在近真空環境中將導電材料1418泵送至孔1404中而形成，因此導電材料1418比在非真空環境下更可完全填充孔1404。此可幫助防止空隙形成於孔1404中。 圖15為根據一些實施例之說明用於形成互連結構之系統的圖。根據一些實施例，注入裝置1500安置於玻璃基板1502及光阻層1506上方。玻璃基板1502及光阻層1506可界定複數個孔1504。藉由光刻製程，光阻層1506可被圖案化以界定分別對應於孔1504之複數個開口1508。注入裝置1500包括槽1510、填充頭或機構1512及泵送頭或機構1514。槽1510填充有導電材料1516，諸如焊料。填充頭1512安置於槽1510之底部處，鄰近於選定孔1404之開口1408中的至少一者。泵送頭1514安置於槽1510之頂部處。諸如氮氣之氣體經由泵送頭1514被泵送至槽1510中且將導電材料1516推入選定孔1504中。注入裝置1500可遵循預定方向1518以一個接一個將導電材料1516泵送至孔1504中。根據一些實施例，注入裝置1500及玻璃基板1502係安置於具有近真空環境的腔室中。因此，注入裝置1500可在近真空環境中將導電材料1516泵送至孔1504中。根據一些實施例，導電材料1516經泵送以溢出光阻層1506之孔1504及開口1508以形成複數個導電凸塊1520。由於互連結構1522係藉由在近真空環境中將導電材料1516泵送至孔1504中而形成，因此導電材料1516比在非真空環境下更可完全填充孔1504。此可幫助防止空隙形成於孔1504中。 根據本發明之一些系統、裝置及方法，半導體裝置封裝之玻璃基板上的互連結構(例如，TGV)及導電凸塊係藉由在近真空環境中將導電材料直接泵送至玻璃基板中的孔中而形成。因此，導電材料更完全填入孔中，且可避免空隙形成。另外，由於互連結構及導電凸塊可藉由單個泵送製程形成，因此不必執行焊料球成形製程，且可減小半導體裝置封裝之生產成本。 如本文中所使用，除非上下文另外清晰地規定，否則單數術語「一」及「該」可包括複數指示物。 如本文中所使用，術語「大致」、「實質上」、「相當大的」及「約」係用以描述及考慮小的變化。當與事件或情形結合使用時，該等術語可指其中事件或情形精確地發生之例子以及其中事件或情形極近似發生之例子。舉例而言，當結合數值使用時，該等術語可指小於或等於該數值之±10%的變化範圍，諸如，小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%或者小於或等於±0.05%之變化範圍。舉例而言，若兩個數值之間的差異小於或等於該等值之平均值的±10% (諸如，小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%)、小於或等於±0.1%或小於或等於±0.05%，則可認為該兩個數值「實質上」相同或相等的。 另外，有時在本文中按範圍格式呈現量、比率及其他數值。應理解，此類範圍格式出於便利及簡潔起見而使用，且應靈活地理解為不僅包括明確地指定為範圍限值之數值，且亦包括涵蓋於該範圍內之所有個別數值或子範圍，如同明確地指定每一數值及子範圍一般。 雖然已描述某些實施例，但此等實施例僅作為實例呈現，且並不意欲限制本發明之範疇。實際上，可以多種其他形式來實施本文中所描述之實施例；此外，可在不脫離本發明之精神的情況下對本文中所描述之實施例的形式進行各種省略、替代及改變。隨附申請專利範圍及其等效物意欲涵蓋應屬於本發明之範疇及精神內的此類形式或修改。另外，上述實施例中之一些或全部可在實施時予以組合。
100‧‧‧半導體裝置封裝102‧‧‧玻璃基板104‧‧‧整合被動裝置結構(IPD)106‧‧‧半導體晶片108‧‧‧第一表面110‧‧‧第二表面112‧‧‧孔114‧‧‧互連結構116‧‧‧導電凸塊118‧‧‧接合線120‧‧‧第一開口122‧‧‧第二開口124‧‧‧內表面126‧‧‧平坦表面202‧‧‧互連結構204‧‧‧導電凸塊206‧‧‧孔208‧‧‧第一表面210‧‧‧第二表面212‧‧‧玻璃基板302‧‧‧互連結構304‧‧‧導電凸塊306‧‧‧孔308‧‧‧第一表面310‧‧‧第二表面312‧‧‧玻璃基板314‧‧‧鈍化層402‧‧‧互連結構404‧‧‧導電凸塊406‧‧‧孔408‧‧‧第一表面410‧‧‧第二表面412‧‧‧玻璃基板414‧‧‧鈍化層416‧‧‧寬度418‧‧‧第二表面500‧‧‧方法502‧‧‧操作504‧‧‧操作506‧‧‧操作508‧‧‧操作510‧‧‧操作512‧‧‧操作514‧‧‧操作516‧‧‧操作602‧‧‧玻璃基板604‧‧‧孔606‧‧‧第一表面608‧‧‧第二表面610‧‧‧第一開口702‧‧‧光阻層704‧‧‧開口706‧‧‧互連結構708‧‧‧導電凸塊802‧‧‧黏接層804‧‧‧載體902‧‧‧第三表面904‧‧‧第二開口1002‧‧‧第一鈍化層1004‧‧‧孔1006‧‧‧導電結構1008‧‧‧被動裝置/金屬-絕緣體-金屬(MIM)電容器1102‧‧‧導電通孔1104‧‧‧重佈層1106‧‧‧導電墊1108‧‧‧第二鈍化層1202‧‧‧半導體晶片1204‧‧‧接合線1302‧‧‧絕緣模製化合物1400‧‧‧注入裝置1402‧‧‧玻璃基板1404‧‧‧孔1406‧‧‧光阻層1408‧‧‧開口1410‧‧‧槽1412‧‧‧填充頭或機構1414‧‧‧泵送頭或機構1416‧‧‧真空頭或機構1418‧‧‧導電材料1420‧‧‧方向1422‧‧‧導電凸塊1424‧‧‧互連結構1500‧‧‧注入裝置1502‧‧‧玻璃基板1504‧‧‧孔1506‧‧‧光阻層1508‧‧‧開口1510‧‧‧槽1512‧‧‧填充頭或機構1514‧‧‧泵送頭或機構1516‧‧‧導電材料1518‧‧‧方向1520‧‧‧導電凸塊1522‧‧‧互連結構d1‧‧‧第一直徑d2‧‧‧深度d3‧‧‧第二直徑d4‧‧‧厚度D1‧‧‧第一直徑D2‧‧‧第二直徑D3‧‧‧深度D4‧‧‧直徑D5‧‧‧直徑D6‧‧‧直徑H1‧‧‧第一高度H2‧‧‧第二高度W‧‧‧寬度W1‧‧‧寬度W2‧‧‧寬度W3‧‧‧寬度
當結合隨附圖式閱讀時，自以下詳細描述最佳地理解本發明之一些實施例的態樣。應注意，圖式中所描繪之物件及組件的各種特徵可能未必按比例繪製。圖式中所描繪之各種物件及組件的一些尺寸可出於提供用於論述之適用實例的目的而任意增大或減小。 圖1為根據一些實施例之說明半導體裝置封裝的橫截面圖。 圖2為根據一些實施例之說明互連結構及導電凸塊的圖。 圖3為根據一些實施例之說明互連結構及導電凸塊的圖。 圖4為根據一些實施例之說明互連結構及導電凸塊的圖。 圖5為根據一些實施例之說明形成半導體裝置封裝之方法的流程圖。 圖6為根據一些實施例之說明具有複數個孔之玻璃基板的圖。 圖7為根據一些實施例之說明圖案化於玻璃基板上之光阻層的圖。 圖8為根據一些實施例之說明玻璃基板的黏接層及黏接至該黏接層之載體的圖。 圖9為根據一些實施例之說明薄化玻璃基板的圖。 圖10為根據一些實施例之說明形成於玻璃基板上之複數個被動裝置的圖。 圖11為根據一些實施例之說明形成於玻璃基板上之整合被動裝置結構的圖。 圖12為根據一些實施例之說明附接於整合被動裝置結構上之半導體晶片的圖。 圖13為根據一些實施例之說明安置於半導體晶片上之絕緣模製化合物的圖。 圖14為根據一些實施例之說明注入裝置的圖。 圖15為根據一些實施例之說明注入裝置的圖。
100‧‧‧半導體裝置封裝
102‧‧‧玻璃基板
104‧‧‧整合被動裝置結構(IPD)
106‧‧‧半導體晶片
108‧‧‧第一表面
110‧‧‧第二表面
112‧‧‧孔
114‧‧‧互連結構
116‧‧‧導電凸塊
118‧‧‧接合線
120‧‧‧第一開口
122‧‧‧第二開口
124‧‧‧內表面
126‧‧‧平坦表面
D1‧‧‧第一直徑
D2‧‧‧第二直徑
D3‧‧‧深度
W‧‧‧寬度

Claims (1)

  1. 一種用於形成一互連結構的系統，其包含：基板，其界定形成於該基板之一表面中之複數個孔；一注入裝置，其安置於該基板上方，該注入裝置包含：一槽，其經組態以裝載有一導電材料；一泵送頭，其鄰近該槽之一頂部安置；一填充頭，其鄰近該槽之一底部安置且經組態以填充該複數個孔之一選定孔以形成一互連結構；及一真空頭，其經組態以將空氣抽取出該選定孔以使該選定孔變為真空或近真空；其中該泵送頭經組態以將一氣體泵送至該槽中且藉此將該導電材料在一真空或近真空環境中推入該選定孔中。
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Publication number Priority date Publication date Assignee Title
US11272618B2 (en) 2016-04-26 2022-03-08 Analog Devices International Unlimited Company Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits
US10325842B2 (en) * 2017-09-08 2019-06-18 Advanced Semiconductor Engineering, Inc. Substrate for packaging a semiconductor device package and a method of manufacturing the same
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
US11201205B2 (en) * 2019-07-31 2021-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect layout for semiconductor device
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080001241A1 (en) * 2006-03-01 2008-01-03 Tessera, Inc. Structure and method of making lidded chips
US20100314758A1 (en) * 2009-06-12 2010-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via structure and a process for forming the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8405201B2 (en) * 2009-11-09 2013-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via structure
US8431977B2 (en) * 2010-06-10 2013-04-30 Megica Corporation Wafer level processing method and structure to manufacture semiconductor chip
US20130113103A1 (en) * 2011-11-03 2013-05-09 Texas Instruments Incorporated DEVICE HAVING TSVs WITH GETTERING LAYER LATERAL TO TSV TIPS
US8916422B2 (en) * 2013-03-15 2014-12-23 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
TWI544593B (zh) * 2013-09-09 2016-08-01 矽品精密工業股份有限公司 半導體裝置及其製法
CN105489580B (zh) * 2014-09-17 2018-10-26 日月光半导体制造股份有限公司 半导体衬底及半导体封装结构
KR20180001699A (ko) * 2016-06-27 2018-01-05 에스케이하이닉스 주식회사 웨이퍼 레벨 패키지 및 제조 방법
US10163771B2 (en) * 2016-08-08 2018-12-25 Qualcomm Incorporated Interposer device including at least one transistor and at least one through-substrate via
US10290590B2 (en) * 2016-11-29 2019-05-14 Taiwan Semiconductor Manufacturing Company Ltd. Stacked semiconductor device and method of manufacturing the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080001241A1 (en) * 2006-03-01 2008-01-03 Tessera, Inc. Structure and method of making lidded chips
US20100314758A1 (en) * 2009-06-12 2010-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via structure and a process for forming the same

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