CN105702633A - 半导体封装体 - Google Patents

半导体封装体 Download PDF

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Publication number
CN105702633A
CN105702633A CN201510934776.5A CN201510934776A CN105702633A CN 105702633 A CN105702633 A CN 105702633A CN 201510934776 A CN201510934776 A CN 201510934776A CN 105702633 A CN105702633 A CN 105702633A
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package body
semiconductor package
chip
binding face
support portion
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许文松
林世钦
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MediaTek Inc
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MediaTek Inc
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Abstract

本发明实施例公开了一种半导体封装体。该半导体封装体包括：基板结构、半导体祼芯片以及中介层，其中该基板结构具有凹口，其中该凹口的底表面作为该基板结构的祼芯片贴合面；该半导体祼芯片设于该凹口中，且设于该祼芯片贴合面上，其中该凹口的侧壁与该半导体祼芯片隔开；该中介层，设于该基板结构上，且覆盖该凹口。本发明的半导体封装体，采用具有凹口结构的基板结构，可提供较小的垂直高度。

Description

半导体封装体
技术领域
本发明涉及半导体封装体，尤其涉及一种层叠封装(PackageonPackage，PoP)的半导体封装体。
背景技术
层叠封装的封装体是用以垂直结合分离的片上为统(system-on-chip，SOC)及存储器封装结构的集成电路封装方法。两个或更多个的封装安装在彼此顶上，亦即堆叠，且在两个或多个封装之间具有路由信号的标准界面。这使得在诸如移动电话、个人数字助理(PDA)和数字照相机等装置中可实现更高的元件密度。
由于在底部的SOC封装体的输入/输出连接的数量增加，很难减少上部的存储器封装体与底部的SOC封装体之间的高度。
因此，业界仍须一种新颖的半导体封装体。
发明内容
有鉴于此，本发明实施例提供了一种半导体封装体，可以提供较小的垂直高度。
本发明提供了一种半导体封装体，包括：
基板结构，具有凹口，其中该凹口的底表面作为该基板结构的祼芯片贴合面；
半导体祼芯片，设于该凹口中，且设于该祼芯片贴合面上，其中该凹口的侧壁与该半导体祼芯片隔开；以及
中介层，设于该基板结构上，且覆盖该凹口。
其中，该基板结构包括：
底板部，具有顶表面和底表面，其中，该祼芯片贴合面为该底板部的顶表面的一部分；以及
支撑部，设于该底板部的顶表面上，且围绕该半导体祼芯片，其中该支撑部的内壁为该凹口的侧壁。
其中，更包括：底部填充材料，填入该半导体祼芯片与该基板结构之间的间隙。
其中，更包括：模塑料，填入该凹口，且与该半导体祼芯片直接接触。
其中，该半导体祼芯片中相对于该祼芯片贴合面的表面自该模塑料暴露出来。
其中，该模塑料完全覆盖该半导体祼芯片。
其中，该模塑料填入该中介层与该基板结构之间的空间。
其中，该半导体祼芯片相对于该祼芯片贴合面的表面与该支撑部相对该祼芯片贴合面的表面齐平，或低于该支撑部相对该祼芯片贴合面的表面。
其中，该底板部及该中介层包括：核心基板或无核心基板。
其中，该底板部包括：额外的电路结构，该额外的电路结构包括：介电层以及设于该介电层中的导电线路。
其中，该支撑部包括：介电层以及穿过该介电层的导电结构。
其中，该底板部的介电层及该支撑部的介电层以包括预浸渍材料、聚亚酰胺、味之素组成薄膜、聚对苯撑苯并双恶唑、聚丙烯或模塑料的材料形成。
其中，该导电结构包括：导孔、导电柱、或焊接球。
其中，该中介层接合于该支撑部上。
其中，该支撑部的外壁与该底板部的侧壁及该中介层的侧壁对齐。
本发明提供了一种半导体封装体，包括：
基板结构，具有祼芯片贴合面、中介层贴合面以及凸块贴合面，其中该祼芯片贴合面及该中介层贴合面分别与该凸块贴合面为相反面；
中介层，设于该基板结构的该中介层贴合面上，其中该基板结构与该中介层共同形成容纳空间；以及
半导体祼芯片，设于该容纳空间中，且设于该祼芯片贴合面上。
其中，该祼芯片贴合面与该中介层贴合面并不共平面。
其中，该中介层贴合面与该半导体祼芯片横向隔开。
其中，该基板结构包括：
底板部，具有顶表面以及底表面，其中，该祼芯片贴合面为该底板部的顶表面的一部分；以及
支撑部，具有分别连接该中介层及该底板部的底表面的顶表面及底表面，其中该支撑部的顶表面为该中介层贴合面。
其中，更包括：底部填充材料，填入该半导体祼芯片与该基板结构之间的间隙。
其中，更包括：模塑料，填入该容纳空间，且与该半导体祼芯片直接接触。
其中，该半导体祼芯片相对于该祼芯片贴合面的表面自该模塑料暴露出来。
其中，该模塑料完全覆盖该半导体祼芯片。
其中，该模塑料填入该中介层与该基板结构之间的空间。
其中，该底板部与该支撑部各自分别包括一介电层。
其中，该底板部的介电层和该支撑部的介电层均以包括预浸渍材料、聚亚酰胺、味之素组成薄膜、聚对苯撑苯并双恶唑、聚丙烯或模塑料的材料形成。
其中，该支撑部包括：穿过该支撑部的介电层的导电结构，其中该导电结构包括：导孔、导电柱或焊接球。
其中，该支撑部的内壁与该半导体祼芯片的侧壁隔开。
其中，该支撑部的外壁与该底板部的侧壁及该中介层的侧壁对齐。
本发明实施例的有益效果是：
本发明实施例，由于半导体祼芯片设置在封装基板的凹口中或者设置在封装基板和中介层共同形成的容纳空间中，因此能够提供较小的垂直高度。
附图说明
图1为本发明公开的一些实施例的半导体封装体的横截面示意图。
图2为本发明公开的另一些实施例的半导体封装体的横截面示意图。
图3为本发明公开的另一些实施例的半导体封装体的横截面示意图。
图4A显示了根据本发明公开的一些实施例的半导体封装体的制造方法中的其中一步骤的半导体封装体的横截面示意图。
图4B显示了根据本发明公开的一些实施例的半导体封装体的制造方法中的其中一步骤的半导体封装体的横截面示意图。
图4C显示了根据本发明公开的一些实施例的半导体封装体的制造方法中的其中一步骤的半导体封装体的横截面示意图。
具体实施方式
为了使本发明所解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
在本申请说明书及权利要求当中使用了某些词汇来指称特定的组件。本领域技术人员应可理解，硬件制造商可能会用不同的名词来称呼同一个组件。本说明书及权利要求并不以名称的差异作为区分组件的方式，而是以组件在功能上的差异作为区分的准则。在通篇说明书及权利要求当中所提及的“包括”、“包含”为一开放式的用语，故应解释成“包括(含)但不限定于”。另外，“耦接”一词在此为包括任何直接及间接的电气连接手段。因此，若文中描述第一装置耦接于第二装置，则代表该第一装置可直接电气连接至该第二装置，或透过其它装置或连接手段间接地电气连接至该第二装置。
本发明公开的一些实施例提供了具有层叠封装结构(Package-on-Packagestructure)的半导体封装体。此半导体封装体包括：凹口基板以及设于其上的中介层。此凹口基板为用以将SOC祼芯片(die)设于其凹口中。而上述中介层为用以将存储器祼芯片接合于其上。使用此凹口基板的半导体封装体可达到低成本、高带宽(highbandwidth)、低功率及快速转换的需求。
图1为本发明公开的一些实施例的半导体封装体500a的横截面示意图。在本发明公开的一些实施例中，此半导体封装体500a包括SOC封装结构350a及堆叠(stack)于其上的存储器封装结构410。在本发明公开的一些实施例中，此半导体封装体500a为层叠封装半导体封装体。此半导体封装体500a包括至少两个垂直堆叠且设于基材200上的晶圆级(wafer-level)半导体封装体。
如图1所示，例如为印刷电路板的基材200可包括聚丙烯(polypropylene)。应注意的是，基材200可为单层结构或多层结构。多个导电垫(未绘示)及/或导电线路(conductivetrace)(未绘示)设于基材200的封装表面202上。在本发明公开的一些实施例中，导电线路可包括电源线路部分、信号线路部分、或接地线路部分，此导电线路用作SOC封装结构350a及存储器封装结构410的输入/输出连接。此外，SOC封装结构350a可直接设于导电线路上。在本发明公开的其它一些实施例中，导电垫为设于封装表面202上，并连接至导电线路不同的末端。SOC封装结构350a可直接设于此导电垫上。
如图1所示，SOC封装结构350a藉由接合步骤设于基材200的封装表面202上。此SOC封装结构350a藉由导电结构322设于基材200上。此SOC封装结构350a包括基板结构306与接合于基板结构306上的半导体祼芯片300。在本发明公开的一些实施例中，此半导体祼芯片300为SOC祼芯片。
如图1所示，基板结构306具有中介层贴合面(interposer-attachsurface)334及与此中介层贴合面334互为相反面的凸块贴合面(bump-attachsurface)304。基板结构306具有凹口(cavity)360，此凹口360自中介层贴合面334向下延伸至部分基板结构306中。此凹口360大致位于此基板结构306的中间部分。此凹口360的底表面361亦作为基板结构306的祼祼芯片贴合面。
如图1所示，基板结构306包括底板部(plateportion)320及支撑部308。此底板部320具有平坦的顶表面302及平坦的底表面。此底板部320的底表面亦为基板结构306的凸块贴合面304。凹口360的底表面361为底板部320的顶表面302的一部分。在本发明公开的一些实施例中，底板部320可包括核心基板(coresubstrate)或无核心基板(corelesssubstrate)。在本发明公开的一些实施例中，如图1所示，底板部320为无核心基板。此底板部320包括额外的电路结构，此额外的电路结构包括一个或多个介电层310、导电线路312(conductivetrace)、导孔314以及导电垫316、318。在本发明公开的一些实施例中，介电层310以包括预浸渍材料(“预浸渍”复合纤维)(prepreg("pre-impregnated"compositefibers)、聚亚酰胺、味之素组成薄膜(Ajinomotobuild-upfilm，ABF)、聚对苯撑苯并双恶唑(poly-p-phenylenebenzobisthiazole，PBO)、聚丙烯(polypropylene，PP)或模塑料的材料形成。上述导电线路312及导孔314藉由激光冲孔步骤(laserdrillingprocess)、镀膜步骤及光刻(photolithography)步骤设于介电层310中。导电垫316及318藉由镀膜步骤及光刻步骤分别设于邻近顶表面302与底表面304的部分。此导电垫316及318电性连接至上述导电线路312及导孔314。此外，邻近底表面304的导电垫318电性连接至导电结构322。在本发明公开的一些实施例中，导电线路312、导孔314及导电垫316、318为由包括铜的金属形成。
如图1所示，支撑部308设于底板部320的顶表面302上。支撑部308具有顶表面，此顶表面亦为基板结构306的中介层贴合面334。支撑部308亦具有底表面332，此底表面332接触底板部320的顶表面302。因此，凹口360的底表面361(顶表面302的一部分)与基板结构306的中介层贴合面334并不共平面。此支撑部308环绕底板部320的周边区以形成穿过此支撑部308的凹口360。底表面332接触此底板部320的顶表面302的周边区。换言之，支撑部308并未覆盖底板部320的顶表面302对应底表面361的部分。此外，支撑部308的外壁331与底板部320的侧壁311对齐。此外，支撑部308的内壁364作为凹口360的侧壁364。
如图1所示，支撑部308包括介电层330以及至少一个穿过介电层330的导电结构324。在本发明公开的一些实施例中，介电层330为单层结构。此外，介电层330为以包括预浸渍材料(“预浸渍”复合纤维)、聚亚酰胺、味之素组成薄膜(ABF)、聚对苯撑苯并双恶唑(PBO)、聚丙烯(PP)或模塑料的材料形成。在本发明公开的一些实施例中，底板部320的介电层310及支撑部308的介电层330可由相同材料形成。导电结构324电性连接至底板部320的导电垫316。在本发明公开的一些实施例中，导电结构324包括导孔、导电柱、或焊接球。在本发明公开的一些实施例中，导电结构324为由包括铜或焊材的金属形成。在本发明公开的一些实施例中，如图1所示，当导电结构324为铜导孔时，支撑部308更包括导电垫326及设于此导电垫326上的导电凸块328。此导电垫326及导电凸块328设于支撑部308的顶表面上(亦即基板结构306的中介层贴合面334)，且此导电垫326及导电凸块328电性连接至导电结构324。在本发明公开的一些实施例中，导电凸块328包括预焊材料(pre-solder)、导电柱、或焊接球。
如图1所示，半导体祼芯片300设于凹口360中，且设于基板结构306的底表面361上。于图1所示的横截面示意图中，此半导体祼芯片300的宽度可设计为小于凹口360的宽度。在本发明公开的一些实施例中，凹口360的侧壁364与半导体祼芯片300隔开。此外，于图1所示的横截面示意图中，基板结构306的中介层贴合面334与半导体祼芯片300横向隔开(laterallyseparate)。在本发明公开的一些实施例中，半导体祼芯片300为包括逻辑祼芯片的半导体祼芯片300。此逻辑祼芯片包括中央处理单元(CPU)、图形处理单元(GPU)、动态随机存取存储器(DRAM)控制器、或上述的组合。应注意的是，半导体祼芯片300的数量并不限于所述的实施例。在本发明公开的一些实施例中，此半导体祼芯片300可由硅穿孔技术或倒装芯片技术制得。在此实施例中，半导体祼芯片300由倒装芯片技术制得。因此，半导体祼芯片300具有远离底表面361的背表面351。在本发明公开的一些实施例中，半导体祼芯片300的背表面351与基板结构306的中介层贴合面334齐平，或低于基板结构306的中介层贴合面334。此半导体祼芯片300藉由导电凸块352电性连接至基板结构306的导电垫316。导电凸块352设于半导体祼芯片300与导电垫316之间。在本发明公开的一些实施例中，导电凸块352可包括铜凸块或焊材凸块。
如图1所示，SOC封装结构350a更包括填入半导体祼芯片300与基板结构306之间的间隙的底部填充材料354。此底部填充材料354覆盖基板结构306的底表面361的一部分。在本发明公开的一些实施例中，底部填充材料354可包括毛细底部填充材料(CapillaryUnderfill，CUF)、模塑底部填充材料(MoldedUnderfill，MUF)、或上述的组合。
如图1所示，半导体封装体500a更包括堆叠于SOC封装结构350a上的存储器封装结构410。在本发明公开的一些实施例中，存储器封装结构410包括引线接合封装(wirebondingpackage)、贯孔导孔(硅穿孔)封装(throughholevia(TSV)package)或倒装芯片封装。在此实施例中，存储器封装结构410为引线接合封装。或者，存储器封装结构410可包括由多个存储器祼芯片垂直堆叠形成的三维半导体封装结构。此存储器封装结构410包括中介层340以及至少一个接合于此中介层340上的存储器祼芯片400。此中介层340接合于基板结构306的支撑部308。此外，中介层340完全覆盖凹口360与基板结构306的中介层贴合面334。此中介层340具有祼芯片贴合面342及凸块贴合面344，此祼芯片贴合面342及凸块贴合面344互为相反面。此祼芯片贴合面342用以贴合存储器祼芯片400。此凸块贴合面344用以将导电结构(例如：导电凸块328)接合至基板结构306的中介层贴合面334。
在本发明公开的一些实施例中，中介层340可包括核心基板或无核心基板。中介层340的侧壁341大抵与支撑部308的外壁331及底板部320的侧壁311对齐。在本发明公开的一实施例中，如图1所示，中介层340为无核心基板。中介层340包括额外的电路结构，此额外的电路结构包括一个或多个介电层348以及设于此介电层348中的导电电路346。在本发明公开的一些实施例中，导电电路346可包括导电线路(conductivetrace)、导孔及导电垫。在本发明公开的一些实施例中，中介层340的组成(composition)与底板部320的组成相似。例如，中介层340的介电层348可与底板部320的介电层310相似。此中介层340的导电电路346可包括导电线路、导孔及导电垫，其与底板部320的导电线路312、导孔314及导电垫316及318相似。在本发明公开的一些实施例中，如图1所示，中介层340的导电电路346电性连接至其对应的导电凸块328，此导电凸块328设于支撑部308上且具有一高度。因此，可于中介层340与基板结构306之间形成一空间362。此外，此空间362可形成于多个导电凸块328之间。
在本发明公开的一些实施例中，如图1所示，基板结构306与中介层340共同形成容纳空间(accommodationspace)，此容纳空间包括上述位于基板结构306的中央部的凹口360。半导体祼芯片300设于包括凹口360的容纳空间中，且设于基板结构306的底表面361上。换言之，基板结构306与接合于其上的中介层340共同形成复合结构380。于图1所示的横截面示意图中，此复合结构380大抵具有圆环型(ringshape)。在本发明公开的一些实施例中，如图1所示，复合结构380可具有中空空间(hollowspace)，此中空空间包括上述位于基板结构306的中央部的凹口360。半导体祼芯片300设于包括凹口360的中空空间中，且设于基板结构306的底表面361上。
在本发明公开的一些实施例中，存储器祼芯片400可包括遵守特定引脚分配规则(例如JEDECLPDDRI/O存储器标准(JEDECLow-PowerDoubleDataRateI/OMemoryspecification))的LPDDRDRAM祼芯片，或者遵守另一特定引脚分配规则(例如JEDEC宽输入输出存储器标准(JEDECWideI/OMemoryspecification))的宽输入输出DRAM祼芯片。此存储器祼芯片400藉由黏胶(未绘示)贴合至祼芯片贴合面342上。此存储器祼芯片400藉由接线404耦接至中介层340。接线404的末端电性连接至存储器祼芯片400的导电垫402以及对应的中介层340的导电电路346。此存储器祼芯片400更包括模塑料(moldingmaterial)406，此模塑料406覆盖中介层340的祼芯片贴合面342，且封装存储器祼芯片400及接线404。
图2为本发明公开的另一些实施例的半导体封装体500b的横截面示意图。应注意的是，后文中与前文相同或相似的组件或膜层将以相同或相似于图1的标号表示，其材料、制造方法与功能皆与前文所述相同或相似，故此部分在后文中将不再赘述。如图1和2所示，半导体封装体500a与半导体封装体500b的差异在于半导体封装体500b包括模塑料370(moldingcompound)，此模塑料370填入凹口360且填入半导体祼芯片300与基板结构306之间的间隙。模塑料370与半导体祼芯片300、凹口360的侧壁364及基板结构306的底表面361直接接触。此模塑料370与中介层340的凸块贴合面344隔开。在此实施例中，半导体祼芯片300中远离底表面361的背表面351自模塑料370暴露出来。半导体祼芯片300的背表面351可对齐模塑料370远离底表面361的顶表面371。此外，模塑料370的顶表面371可对齐基板结构306的中介层贴合面334。
图3为本发明公开的另一些实施例的半导体封装体500c的横截面示意图。应注意的是，后文中与前文相同或相似的组件或膜层将以相同或相似于图1～2的标号表示，其材料、制造方法与功能皆与前文所述相同或相似，故此部分在后文中将不再赘述。如图1和3所示，半导体封装体500a与半导体封装体500c的差异在于半导体封装体500c包括模塑料370，此模塑料370填入凹口360且填入半导体祼芯片300与基板结构306之间的间隙。模塑料370与半导体祼芯片300、凹口360的侧壁364、基板结构306的底表面361及中介层340的凸块贴合面344直接接触。在此实施例中，模塑料370完全覆盖半导体祼芯片300。因此，半导体祼芯片300远离底表面361的背表面351被模塑料370完全覆盖。此外，模塑料370填入中介层340与基板结构306之间的空间362。在此实施例中，模塑料370亦围绕导电垫326上的导电凸块328。
半导体封装体500a-500c使用具有凹口的基板结构，并将半导体祼芯片设于此凹口中。此具有凹口的基板结构可提供较小的垂直高度。基板结构的支撑部可提供SOC封装结构与存储器封装结构之间的额外的内连线。此外，基板结构的底板部可由无核心基板形成，以更进一步减少垂直高度以及工艺成本。使用此凹口基板的半导体封装体可达到低成本、高带宽(highbandwidth)、低功率及快速转换的需求。
图4A-4C为本发明公开的实施例的半导体封装体500a-500c在其制造方法中各阶段的横截面示意图。应注意的是，后文中与前文相同或相似的组件或膜层将以相同或相似的标号表示，其材料、制造方法与功能皆与前文所述相同或相似，故此部分在后文中将不再赘述。
如图4A所示，提供一载板(未绘示)，并使基板结构306形成于其上。接着，进行层叠步骤以将底板部320的一层或多层介电层310形成于载板上。接着，进行冲孔步骤以形成贯穿介电层310的开口(未绘示)，以定义后续的导孔314形成的位置。在本发明公开的一些实施例中，冲孔步骤可包括激光冲孔步骤、蚀刻冲孔步骤或机械冲孔步骤。接着，进行镀膜步骤、光刻步骤及非等向性蚀刻步骤以将导电材料填入开口中以形成底板部320的导电线路312、导孔314及导电垫316、318。在本发明公开的一些实施例中，镀膜步骤可包括电镀步骤。
接着，如图4A所示，将支撑部308形成于底板部320的顶表面302上。形成支撑部308的步骤可与形成底板部320的步骤相似。在本发明公开的一些实施例中，支撑部308与底板部320可各自独立地形成，接着再将支撑部308设于底板部320上，以藉由此层叠步骤形成基板结构306。
然而，在其它一些实施例中，如图4A所示，包括介电层330、导电结构324及/或导电垫326的一块基板藉由层叠步骤设于底板部320上。接着，进行光刻步骤以及非等向性蚀刻步骤以移除此块基板的中间部分，并形成设于底板部320上的支撑部308。于前述步骤之后，便形成具有凹口360的基板结构306。
接着，如图4B所示，翻转半导体祼芯片300并将其设于凹口360中。此半导体祼芯片300藉由接合步骤设于基板结构306的底表面361上。半导体祼芯片300为透过导电凸块352电性连接至基板结构306的导电垫316。
接着，如图4C所示，将中介层340接合至基板结构306的支撑部308上。形成中介层340的步骤可与形成底板部320与支撑部308的步骤相似。在本发明公开的一些实施例中，于接合中介层340之前，导电凸块328可形成于对应的基板结构306的导电垫326上。中介层340的导电电路346可电性连接至对应的导电凸块328。
接着，进行后续的步骤以形成图1～3所示的半导体封装体500a-500c。在本发明公开的一些实施例中，如图1所示，于接合中介层340后，底部填充材料354可填入半导体祼芯片300与基板结构306之间的间隙。或者，可进行涂布步骤(coatingprocess)以将模塑料370填入凹口360且填入半导体祼芯片300与基板结构306之间的间隙，如图2～3所示。于进行前述步骤之后，便形成SOC封装结构350a。
在形成图1所示的底部填充材料354或图2～3所示的模塑料370之后，可藉由焊接球制造步骤或铜柱制造步骤形成导电结构322于基板结构306的凸块贴合面304上，如图1～3所示。在本发明公开的一些实施例中，如图1～3所示，导电结构322电性连接至对应的导电垫318。
在形成导电结构322于基板结构306的凸块贴合面304上后，如图1～3所示，存储器祼芯片400藉由粘胶(未绘示)贴附于祼芯片贴合面342上。接着，进行接合步骤，存储器祼芯片400藉由接线404耦接至中介层340，如图1～3所示。接着，进行模塑步骤以形成模塑料406，此模塑料406覆盖中介层340的祼芯片贴合面342，且封装存储器祼芯片400及接线404，如图1～3所示。在本发明公开的一些实施例中，模塑步骤可包括转印成模步骤(transfermoldingprocess)、片状成模步骤(sheetmoldingprocess)、或模压成模步骤(compressionmoldingprocess)。在进行模塑步骤后，便形成存储器封装结构410。
本发明公开的的一些实施例提供具有层叠封装结构(package-on-packagestructure)的半导体封装体及其制造方法。此半导体封装体包括凹口基板以及设于其上的中介层。此凹口基板用以将SOC祼芯片设于其凹口中，故可减小此半导体封装体的垂直高度。基板结构的支撑部可提供SOC封装结构与存储器封装结构之间的额外的内连线。而中介层接合于基板结构的中介层贴合面上，且此中介层用以将存储器祼芯片接合于其上。基板结构与接合于其上的中介层共同形成复合结构，此复合结构的横截面示意图大抵具有圆环型，如图1～3所示。换言之，复合结构可具有中空空间(hollowspace)，此中空空间包括上述位于基板结构的中央部的凹口。半导体祼芯片为设于包括凹口的中空空间中。因此，祼芯片贴合面与基板结构的中介层贴合面并不共平面。使用此凹口基板的半导体封装体可达到低成本、高带宽(highbandwidth)、低功率及快速转换的需求。
虽然本发明公开的的实施例及其优点已揭露如上，但应该了解的是，任何本领域技术人员，在不脱离本发明公开的的精神和范围内，当可作更动、替代与润饰。此外，本发明公开的的保护范围并未局限于说明书内所述特定实施例中的工艺、机器、制造、物质组成、装置、方法及步骤，任何本领域技术人员可从本发明公开的揭示内容中理解现行或未来所发展出的工艺、机器、制造、物质组成、装置、方法及步骤，只要可以在此处所述实施例中实施大抵相同功能或获得大抵相同结果皆可为根据本发明公开的使用。因此，本发明公开的保护范围包括上述工艺、机器、制造、物质组成、装置、方法及步骤。另外，每一权利要求构成个别的实施例，且本发明公开的的保护范围也包括各个权利要求及实施例的组合。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (29)

1.一种半导体封装体，其特征在于，包括：
基板结构，具有凹口，其中该凹口的底表面作为该基板结构的祼芯片贴合面；
半导体祼芯片，设于该凹口中，且设于该祼芯片贴合面上，其中该凹口的侧壁与该半导体祼芯片隔开；以及
中介层，设于该基板结构上，且覆盖该凹口。
2.如权利要求1所述的半导体封装体，其特征在于，该基板结构包括：
底板部，具有顶表面和底表面，其中，该祼芯片贴合面为该底板部的顶表面的一部分；以及
支撑部，设于该底板部的顶表面上，且围绕该半导体祼芯片，其中该支撑部的内壁为该凹口的侧壁。
3.如权利要求2所述的半导体封装体，其特征在于，更包括：底部填充材料，填入该半导体祼芯片与该基板结构之间的间隙。
4.如权利要求2所述的半导体封装体，其特征在于，更包括：模塑料，填入该凹口，且与该半导体祼芯片直接接触。
5.如权利要求4所述的半导体封装体，其特征在于，该半导体祼芯片中相对于该祼芯片贴合面的表面自该模塑料暴露出来。
6.如权利要求4所述的半导体封装体，其特征在于，该模塑料完全覆盖该半导体祼芯片。
7.如权利要求6所述的半导体封装体，其特征在于，该模塑料填入该中介层与该基板结构之间的空间。
8.如权利要求2所述的半导体封装体，其特征在于，该半导体祼芯片相对于该祼芯片贴合面的表面与该支撑部相对该祼芯片贴合面的表面齐平，或低于该支撑部相对该祼芯片贴合面的表面。
9.如权利要求2所述的半导体封装体，其特征在于，该底板部及该中介层包括：核心基板或无核心基板。
10.如权利要求2所述的半导体封装体，其特征在于，该底板部包括：额外的电路结构，该额外的电路结构包括：介电层以及设于该介电层中的导电线路。
11.如权利要求10所述的半导体封装体，其特征在于，该支撑部包括：介电层以及穿过该介电层的导电结构。
12.如权利要求11所述的半导体封装体，其特征在于，该底板部的介电层及该支撑部的介电层以包括预浸渍材料、聚亚酰胺、味之素组成薄膜、聚对苯撑苯并双恶唑、聚丙烯或模塑料的材料形成。
13.如权利要求11所述的半导体封装体，其特征在于，该导电结构包括：导孔、导电柱、或焊接球。
14.如权利要求2所述的半导体封装体，其特征在于，该中介层接合于该支撑部上。
15.如权利要求2所述的半导体封装体，其特征在于，该支撑部的外壁与该底板部的侧壁及该中介层的侧壁对齐。
16.一种半导体封装体，其特征在于，包括：
基板结构，具有祼芯片贴合面、中介层贴合面以及凸块贴合面，其中该祼芯片贴合面及该中介层贴合面分别与该凸块贴合面为相反面；
中介层，设于该基板结构的该中介层贴合面上，其中该基板结构与该中介层共同形成容纳空间；以及
半导体祼芯片，设于该容纳空间中，且设于该祼芯片贴合面上。
17.如权利要求16所述的半导体封装体，其特征在于，该祼芯片贴合面与该中介层贴合面并不共平面。
18.如权利要求16所述的半导体封装体，其特征在于，该中介层贴合面与该半导体祼芯片横向隔开。
19.如权利要求16所述的半导体封装体，其特征在于，该基板结构包括：
底板部，具有顶表面以及底表面，其中，该祼芯片贴合面为该底板部的顶表面的一部分；以及
支撑部，具有分别连接该中介层及该底板部的底表面的顶表面及底表面，其中该支撑部的顶表面为该中介层贴合面。
20.如权利要求19所述的半导体封装体，其特征在于，更包括：底部填充材料，填入该半导体祼芯片与该基板结构之间的间隙。
21.如权利要求19所述的半导体封装体，其特征在于，更包括：模塑料，填入该容纳空间，且与该半导体祼芯片直接接触。
22.如权利要求21所述的半导体封装体，其特征在于，该半导体祼芯片相对于该祼芯片贴合面的表面自该模塑料暴露出来。
23.如权利要求21所述的半导体封装体，其特征在于，该模塑料完全覆盖该半导体祼芯片。
24.如权利要求23所述的半导体封装体，其特征在于，该模塑料填入该中介层与该基板结构之间的空间。
25.如权利要求19所述的半导体封装体，其特征在于，该底板部与该支撑部各自分别包括一介电层。
26.如权利要求25所述的半导体封装体，其特征在于，该底板部的介电层和该支撑部的介电层均以包括预浸渍材料、聚亚酰胺、味之素组成薄膜、聚对苯撑苯并双恶唑、聚丙烯或模塑料的材料形成。
27.如权利要求25所述的半导体封装体，其特征在于，该支撑部包括：穿过该支撑部的介电层的导电结构，其中该导电结构包括：导孔、导电柱或焊接球。
28.如权利要求19所述的半导体封装体，其特征在于，该支撑部的内壁与该半导体祼芯片的侧壁隔开。
29.如权利要求19所述的半导体封装体，其特征在于，该支撑部的外壁与该底板部的侧壁及该中介层的侧壁对齐。
CN201510934776.5A 2014-12-16 2015-12-15 半导体封装体 Pending CN105702633A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107546215A (zh) * 2016-06-27 2018-01-05 南亚科技股份有限公司 中介物、其半导体封装及其半导体封装的制备方法

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9741649B2 (en) 2014-06-04 2017-08-22 Invensas Corporation Integrated interposer solutions for 2D and 3D IC packaging
US10340155B2 (en) * 2016-04-14 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of forming
US10229859B2 (en) * 2016-08-17 2019-03-12 Advanced Semiconductor Engineering, Inc. Semiconductor device package and a method of manufacturing the same
TW202404049A (zh) * 2016-12-14 2024-01-16 成真股份有限公司 標準大宗商品化現場可編程邏輯閘陣列(fpga)積體電路晶片組成之邏輯驅動器
US10410940B2 (en) * 2017-06-30 2019-09-10 Intel Corporation Semiconductor package with cavity
JP2019016683A (ja) * 2017-07-06 2019-01-31 新光電気工業株式会社 配線基板及びその製造方法、半導体パッケージ
KR102509052B1 (ko) * 2018-08-31 2023-03-10 에스케이하이닉스 주식회사 브리지 다이를 포함하는 스택 패키지
TWI711095B (zh) 2019-08-21 2020-11-21 欣興電子股份有限公司 封裝結構及其製備方法
US11688693B2 (en) * 2019-10-29 2023-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packages and method of manufacture
DE102020119181A1 (de) 2019-10-29 2021-04-29 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiterpackages und verfahren zu deren herstellung
KR20220065550A (ko) * 2020-11-13 2022-05-20 삼성전기주식회사 연결구조체 내장기판
KR20220085624A (ko) 2020-12-15 2022-06-22 삼성전자주식회사 인터포저 및 이를 포함하는 반도체 패키지
TWI778560B (zh) * 2021-03-30 2022-09-21 力成科技股份有限公司 封裝結構及其製造方法
TWI788099B (zh) * 2021-11-15 2022-12-21 大陸商芯愛科技（南京）有限公司 電子封裝件及其封裝基板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5081563A (en) * 1990-04-27 1992-01-14 International Business Machines Corporation Multi-layer package incorporating a recessed cavity for a semiconductor chip
US20080308950A1 (en) * 2007-06-12 2008-12-18 Samsung Electro-Mechanics Co., Ltd. Semiconductor package and method for manufacturing thereof
US20140264811A1 (en) * 2013-03-12 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package-On-Package with Cavity in Interposer

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6906415B2 (en) * 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
CN101138089B (zh) * 2005-01-31 2011-02-09 斯班逊有限公司 层叠型半导体装置及层叠型半导体装置的制造方法
US20120119342A1 (en) * 2010-11-11 2012-05-17 Mediatek Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
US20120159118A1 (en) * 2010-12-16 2012-06-21 Wong Shaw Fong Lower IC Package Structure for Coupling with an Upper IC Package to Form a Package-On-Package (PoP) Assembly and PoP Assembly Including Such a Lower IC Package Structure
US8866285B2 (en) * 2012-09-05 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package comprising bulk metal
US10269619B2 (en) * 2013-03-15 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale packaging intermediate structure apparatus and method
US9337135B2 (en) * 2014-10-08 2016-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Pop joint through interposer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5081563A (en) * 1990-04-27 1992-01-14 International Business Machines Corporation Multi-layer package incorporating a recessed cavity for a semiconductor chip
US20080308950A1 (en) * 2007-06-12 2008-12-18 Samsung Electro-Mechanics Co., Ltd. Semiconductor package and method for manufacturing thereof
US20140264811A1 (en) * 2013-03-12 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package-On-Package with Cavity in Interposer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107546215A (zh) * 2016-06-27 2018-01-05 南亚科技股份有限公司 中介物、其半导体封装及其半导体封装的制备方法

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