CN113035858A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN113035858A
CN113035858A CN202110598491.4A CN202110598491A CN113035858A CN 113035858 A CN113035858 A CN 113035858A CN 202110598491 A CN202110598491 A CN 202110598491A CN 113035858 A CN113035858 A CN 113035858A
Authority
CN
China
Prior art keywords
eic
chip
pic
substrate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110598491.4A
Other languages
English (en)
Other versions
CN113035858B (zh
Inventor
彭博
孟怀宇
沈亦晨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hangzhou Guangzhiyuan Technology Co ltd
Original Assignee
Hangzhou Guangzhiyuan Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hangzhou Guangzhiyuan Technology Co ltd filed Critical Hangzhou Guangzhiyuan Technology Co ltd
Priority to CN202110598491.4A priority Critical patent/CN113035858B/zh
Publication of CN113035858A publication Critical patent/CN113035858A/zh
Application granted granted Critical
Publication of CN113035858B publication Critical patent/CN113035858B/zh
Priority to TW111119878A priority patent/TW202247409A/zh
Priority to US17/826,791 priority patent/US20220384409A1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06E—OPTICAL COMPUTING DEVICES; COMPUTING DEVICES USING OTHER RADIATIONS WITH SIMILAR PROPERTIES
    • G06E3/00—Devices not provided for in group G06E1/00, e.g. for processing analogue or hybrid data
    • G06E3/001—Analogue devices in which mathematical operations are carried out with the aid of optical or electro-optical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/14136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16148—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73209—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/182—Disposition

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明涉及光子集成电路领域，其提供了一种半导体装置及其制造方法，所述半导体装置包括设置在基板上的EIC芯片和PIC芯片，并且，所述EIC芯片位于所述PIC芯片与所述基板之间；其中，至少一个EIC芯片设置在单个PIC芯片的朝向所述基板的表面上，并且所述EIC芯片通过连接结构安装在所述基板上。本发明的半导体装置优化了PIC芯片的布线并能够抑制因布线过长导致的电压压降，优化了封装结构。

Description

半导体装置及其制造方法
技术领域
本发明涉及光子集成电路领域，更为具体而言，涉及一种半导体装置及其制造方法。
背景技术
近年来，人工智能技术快速发展，其中涉及的某些神经网络算法需要进行大量矩阵运算。目前，已有提出用光子计算进行上述运算，光子计算以光作为信息的载体，通过光学器件/芯片实现光的传输、处理、计算等。
现有的一种实现光子计算系统的方案中，需要对电子集成电路（EIC）芯片、光子集成电路（PIC）芯片进行电连接，由于芯片较大，其中起到连接作用的线路较长。由于电阻的存在，电流流经长连接线路后产生电压压降不可忽略并导致额外功耗，压降过多还可能导致系统无法正常工作。此外，在诸如光子计算芯片等应用场景中，为了实现大量数据、信号的传输及电连接，EIC芯片、PIC芯片均具有多个连接点，大量连接点对应了大量的布线线路，这也进一步导致不必要的电压压降。另外，PIC芯片有时需要与外界具有光耦合，这对半导体装置整体的集成具有很大限制。
发明内容
本发明提供了一种半导体装置及其制造方法，其能够有效抑制电压压降，优化PIC芯片、EIC芯片之间的电连接，优化封装尺寸。
一方面，本发明的实施方式提供了一种半导体装置，其包括基板；光子集成电路（PIC）芯片；电子集成电路（EIC）芯片；所述EIC芯片位于所述PIC芯片与所述基板之间；其中，所述PIC芯片与所述EIC芯片进行电连接。
在本发明的一些实施方式中，所述PIC芯片包括PIC布线结构，所述EIC芯片包括EIC布线结构；在所述PIC芯片到所述基板的电连接路径中，包括先后经过所述PIC布线结构、所述EIC布线结构、所述基板的电连接路径。
在本发明的一些实施方式中，所述EIC芯片的周围的至少一部分设置有封装材料，所述封装材料中设置有过孔导电结构，在所述PIC芯片到所述基板的电连接路径中，包括经过所述过孔导电结构的电连接路径。
在本发明的一些实施方式中，所述半导体装置包括PIC再布线结构、第一键合结构、EIC再布线结构一、EIC再布线结构二、过孔导电结构、第二键合结构中的至少一个结构；并且，上述至少一个结构满足：
所述PIC布线结构到所述EIC布线结构的电连接路径中，先后经过PIC再布线结构、第一键合结构、EIC再布线结构一中的至少一个，和/或
所述EIC布线结构到所述基板布线结构的电连接路径中，先后经过EIC再布线结构二、过孔导电结构、第二键合结构中的至少一个。
在本发明的一些实施方式中，所述半导体装置包括至少两个EIC芯片，所述至少两个EIC芯片中，包括第一EIC芯片、第二EIC芯片，所述第一EIC芯片、第二EIC芯片之间具有封装材料，所述封装材料中设置至少一个过孔导电结构。在一些实施方式中，所述第一EIC芯片周围的具有两个以上的过孔导电结构，选取与其布线距离非最远的至少一个过孔导电结构进行连接。
在本发明的一些实施方式中，所述EIC芯片通过第一键合结构与所述PIC芯片连接。所述EIC芯片通过连接结构与所述基板连接，所述连接结构包括：与所述第一键合结构电连接的第一段连接结构、与所述第一段连接结构电连接的第二段连接结构、以及与所述第二段连接结构电连接的第二键合结构。其中，所述EIC芯片通过所述第二键合结构与所述基板连接。
在本发明的一些实施方式中，所述第一段连接结构自所述EIC芯片上的所述第一键合结构的连接点横向延伸并超出所述EIC芯片。所述第二段连接结构自所述第一段连接结构朝着所述基板纵向延伸，并止于所述第二键合结构。
在本发明的一些实施方式中，在所述EIC芯片的周围的至少一部分设置有封装材料，所述封装材料包围所述第二段连接结构。
在本发明的一些实施方式中，所述第二段连接结构包括在所述封装材料中形成的过孔导电结构。
在本发明的一些实施方式中，所述第一段连接结构包括形成在所述EIC芯片及其封装材料上的再分布金属层。
在本发明的一些实施方式中，所述PIC芯片朝向所述基板的投影面积大于至少一个EIC芯片朝向所述基板的投影面积之和。
在本发明的一些实施方式中，多个EIC芯片按照矩阵的形式布置。相邻的EIC芯片之间可设置有封装材料，所述封装材料包围所述第二段连接结构。
在本发明的一些实施方式中，对于多个EIC芯片中的至少一个EIC芯片，从该EIC芯片周围的第二段连接结构中选取与其布线距离非最远的第二段连接结构进行连接。在本发明的可选实施方式中，对于多个EIC芯片中的至少一个EIC芯片，从该EIC芯片周围的第二段连接结构中选取与其布线距离最短的第二段连接结构进行连接。
另一方面，本发明的实施方式提供了一种半导体装置的制造方法，其包括：
提供基板、EIC芯片和PIC芯片；
将所述EIC芯片与所述基板进行电连接；
将所述EIC芯片与所述PIC芯片进行电连接；
所述EIC芯片位于所述PIC芯片与所述基板之间。
在本发明的一些实施方式中，在所述EIC芯片的周围的至少一部分设置封装材料；在所述封装材料中设置过孔导电结构，所述PIC芯片到所述基板的电连接路径中，包括经过所述过孔导电结构的电连接路径。
在本发明的一些实施方式中，所述制造方法设置至少两个EIC芯片，所述至少两个EIC芯片中，包括第一EIC芯片、第二EIC芯片，所述第一EIC芯片、第二EIC芯片之间具有封装材料，所述封装材料中设置至少一个过孔导电结构。
根据本发明的实施方式，通过将EIC芯片设置在PIC芯片与基板之间，并且所述PIC芯片与所述EIC芯片进行电连接， PIC芯片可以通过EIC芯片和连接结构与基板电连接。相比于现有的打线方式的布线，PIC芯片的布线缩短了到基板的线路距离，从而减少了电压压降。另外，可使用多个小的EIC芯片替代原本一个较大的EIC芯片，至少一个EIC芯片可以通过位于其附近的连接结构连接至基板，进一步缩短电连接距离，使所述电压压降得到进一步抑制。由此，改善了半导体装置的性能。
本发明实施方式的各个方面、特征、优点等将在下文结合附图进行具体描述。根据以下结合附图的具体描述，本发明的上述方面、特征、优点等将会变得更加清楚。
附图说明
图1是示例性示出根据本发明的一种实施方式的半导体装置的结构的截面图；
图2是示例性示出根据本发明的一种实施方式的半导体装置的部分结构的截面图；
图3是示例性示出根据本发明的一种实施方式的半导体装置的部分结构的平面布局的示意图；
图4是示例性示出根据本发明的另一种实施方式的半导体装置的结构的截面图；
图5是示例性示出根据本发明的一种实施方式的半导体装置的制造方法的流程图。
具体实施方式
为了便于理解本发明技术方案的各个方面、特征以及优点，下面结合附图对本发明进行具体描述。应当理解，下述的各种实施方式只用于举例说明，而非用于限制本发明的保护范围。
图1示例性示出根据本发明的一种实施方式的半导体装置的结构。图2示例性示出根据本发明的一种实施方式的半导体装置的部分结构，其省略了PIC芯片。图3示例性示出根据本发明的一种实施方式的半导体装置的部分结构的平面布局，其省略了PIC芯片、表面覆盖层和再分布金属层（Redistribution Metal Layer，RDL）。下面结合图1-3对本发明的一种实施方式进行说明。
在本发明的一种实施方式中，所述半导体装置包括设置在基板100上的EIC芯片200和PIC芯片300，并且，所述EIC芯片200位于所述PIC芯片300与所述基板100之间，其中所述EIC芯片与所述PIC芯片可以正对设置，也可以不完全正对。在本实施方式中，一个EIC芯片200设置在单个PIC芯片300的第一表面上，所述PIC芯片300的第一表面朝向所述基板100，所述EIC芯片200的第一表面朝向所述PIC芯片，所述EIC芯片200的第二表面朝向所述基板100；所述EIC芯片200通过连接结构400安装在所述基板100上。
在本实施方式中，所述EIC芯片200通过第一键合结构与所述PIC芯片300连接。所述第一键合结构可以包括由焊料形成的微凸块（Microbump）201，其中，在所述EIC芯片200的多个连接点202上形成多个微凸块201，所述多个微凸块201与所述PIC芯片300上的连接点连接，从而将所述EIC芯片与PIC芯片键合。在本发明的可选实施方式中，所述第一键合结构还可以包括诸如焊料球之类的其他键合结构。
在本实施方式中，所述PIC芯片300朝向所述基板100的投影面积大于所述EIC芯片200朝向所述基板100的投影面积，在所述EIC芯片的周围设置有封装材料500，例如，模塑材料（molding compound）。在可选的实施方式中，所述PIC芯片300的投影面积可以等于或小于所述EIC芯片200的投影面积，同样可以在所述EIC芯片的周围设置有封装材料500。在本发明的可选实施方式中，可以在所述EIC芯片的周围的部分设置所述封装材料，例如，可以在所述EIC芯片至基板的布线距离相对较短或最短的侧面设置所述封装材料。
在本发明的实施方式中，所述连接结构400包括与所述第一键合结构电连接的第一段连接结构、与所述第一段连接结构电连接的第二段连接结构、以及与所述第二段连接结构电连接的第二键合结构。在本实施方式中，所述第一段连接结构包括形成在所述EIC芯片200及其封装材料500上的RDL层401，所述第二段连接结构包括在所述封装材料500中形成的过孔导电结构402，所述第二键合结构包括用于将所述EIC芯片200与基板100连接的焊料球403。EIC芯片的电信号可经由附近的过孔导电结构402传输至基板上，减少了整体的导电连接距离。与某一EIC芯片连接的周边过孔导电结构可以为一个或多个（2个以上），示例性的，某个EIC芯片的四边分别布置有8个、6个、8个、6个过孔导电结构402。在某些情况下，EIC芯片的某一边/某些边可以不布置与之连接的过孔导电结构。
在本实施方式中，所述RDL层401自与微凸块201连接的连接点横向延伸并超出所述EIC芯片200；所述过孔导电结构402自所述RDL层401朝着所述基板100纵向延伸，并止于所述焊料球403；所述焊料球403与设置在所述基板100上或所述基板100中的布线结构101电连接，或者进一步连接至外界布线和/或端口。由此，本实施方式的PIC芯片300的布线线路为自PIC 芯片300的连接点经过微凸块201、RDL层401、以及过孔导电结构402和焊料球403连接于基板100，相比于现有的打线方式布线，本实施方式的布线简单，线路较短，减少了电压压降。在本实施方式中，在所述封装材料500中形成开口，在所述开口中形成导电材料，从而形成所述过孔导电结构402，所述过孔导电结构402通过焊料球403连接至基板100。在所述封装材料500和EIC芯片200的表面形成RDL层401，所述RDL层401将所述过孔导电结构402与所述EIC芯片200和PIC芯片300电连接。在本实施方式中，在所述RDL层401的表面形成有保护所述RDL层401的表面覆盖层600。如图3所示，图中省略了PIC芯片300、RDL层401和表面覆盖层600，类似于焊接垫片（Wirebond pads），过孔导电结构402可以尽可能靠近EIC芯片200设置，以缩短布线线路。
在某些实施方式中，PIC芯片300可包括PIC布线结构（图未示），EIC芯片200可包括EIC布线结构（图未示）。沿着PIC芯片300到基板的导电路径，包括依次经过PIC布线结构（PIC芯片）、EIC布线结构（EIC芯片）、基板100的导电路径，经过基板，可以是经过/最终到达基板（基板上的布线）或基板上的其它器件。在某些实施方式中，所述到达路径包括依次经过PIC布线结构、EIC布线结构、过孔导电结构402、基板100的导电路径。可选的，PIC芯片300到基板100的导电路径中，可包括依次经过PIC布线结构（PIC芯片）、PIC再布线结构、第一键合结构、EIC再布线结构一、EIC布线结构（EIC芯片）、EIC再布线结构二、过孔导电结构、第二键合结构、基板，其中，第一键合结构、PIC再布线结构、EIC再布线结构一、EIC再布线结构二是第二键合结构中的至少一个是可选的（可省略的）。另外，在上述的布线结构、再布线结构、PIC芯片、EIC等进行连接时，可设置额外的键合结构。例如，PIC芯片与EIC芯片连接时，采用了第一键合结构，即微凸块201；在EIC芯片200与基板100进行连接时，采用了第二键合结构为焊料球403。前述各种再布线结构可以包括RDL层。通过导电路径的合理设置，提供了一种适用于PIC芯片、EIC芯片的电连接方式，优化了PIC芯片、EIC芯片封装时的电连接。在某些实施例中，EIC与基板之间的连接结构400的第一段连接结构包括EIC再布线结构二（例如RDL层401），连接结构400的第二段连接结构包括过孔导电结构。
可选的，EIC芯片200与PIC芯片300在电连接时，第一键合结构并非必需的，二者可以通过扩散法键合，例如，在加压加热条件下，EIC布线结构中的Cu与PIC布线结构中的Cu扩散，进行键合。
在本发明的一些实施方式中，所述RDL层401可具有5层铜层，每一层的厚度为约7.5um，由此，相比于现有的在PIC芯片上的金属打线，RDL层401的阻抗要小24倍多。在本发明的可选实施方式中，RDL层401可以是其他结构，例如，4层或5层等其他层数的其他材料的导体层，并且每一层的厚度可以为其他值，并且各层的厚度可以不同。
在本发明的可选实施方式中，所述第二键合结构也可以是本领域中除了焊料球之外的键合结构，例如为焊料凸块。
以上结合附图对一个EIC芯片倒装在PIC芯片上的示例进行了说明。本发明不限于此，可以将至少2个EIC芯片倒装在PIC芯片上。
图4示例性示出根据本发明的另一种实施方式的半导体装置的结构。在本实施方式中，所述半导体装置包括设置在基板100上的多个EIC芯片200和PIC芯片300，并且，所述多个EIC芯片200位于所述PIC芯片300与所述基板100之间。在本实施方式中，多个EIC芯片200倒装在单个PIC芯片300的朝向所述基板100的表面上，所述多个EIC芯片200分别通过连接结构400安装在所述基板100上。其中，连接结构400与上述实施方式的连接结构相同，请参见上面的描述，在此不再重复。
本实施方式与图1所示的实施方式的不同在于所述EIC芯片200的数量和布局。在本实施方式中，所述EIC芯片200的数量可以2个、或3个以上。所述PIC芯片300朝向所述基板100的投影面积大于多个EIC芯片200朝向所述基板的投影面积之和。EIC芯片的电信号可经由附近的过孔导电结构传输至基板，减少了整体的导电连接距离；另外，对于多个EIC芯片（2个以上），包括第一EIC芯片、第二EIC芯片，其中第一EIC芯片、第二EIC芯片的各自周围均可布置过孔导电结构，使得第一和/或第二EIC芯片能就近连接至过孔导电结构，优化了电连接；在某些实施例中，第一、第二EIC芯片之间共有16个过孔导电结构，其中6个与第一EIC连接，10个与第二EIC芯片连接。在本发明的一些实施方式中，多个EIC芯片按照矩阵的形式布置（未示出），相邻的EIC芯片之间可设置有封装材料，所述封装材料包围所述第二段连接结构（例如过孔导电结构）。并且，对于多个EIC芯片200中的至少一个EIC芯片，从该EIC芯片周围的第二段连接结构中选取与其布线距离非最远的第二段连接结构进行连接。换句话说，选取包含与EIC芯片的布线距离相对较近的第二连接结构的连接结构进行连接。在本发明的一种实施方式中，对于多个EIC芯片中的至少一个EIC芯片，从该EIC芯片周围的第二段连接结构中选取与其布线距离最短的第二段连接结构进行连接。例如，在一种示例性应用中，EIC芯片共有9个，呈3乘3阵列布置，相邻的EIC芯片之间均具有封装材料，封装材料中可设置一个和/或多个开口，用于容纳连接导体，对于某一个EIC芯片，可选取与其布线距离最近或相对较近的一个/多个开口进行连接布线。在本发明的可选实施方式中，所有EIC芯片均可选取与其布线距离最短或相对较近的第二段连接结构进行连接。
在本发明的可选实施方式中，对于数量较少的EIC芯片，可以按照线性布置，例如，2个、3个或4个EIC芯片排成一行。
在本实施方式中，使用多个EIC芯片（多个指两个以上）替代所述半导体装置原本需要的一个EIC芯片，所述多个EIC芯片中的部分或全部通过位于其附近的连接结构连接至基板，从而缩短了电连接距离，减少了电压压降。
图5示例性示出根据本发明的一种实施方式的半导体装置的制造方法的流程。所述半导体装置的制造方法包括：
S101，提供基板、电子集成电路（EIC）芯片和光子集成电路（PIC）芯片；
S102，将至少一个EIC芯片倒装在单个PIC芯片上；
S103，将倒装在单个PIC芯片上的EIC芯片通过连接结构安装在所述基板上，使得所述EIC芯片位于所述PIC芯片与所述基板之间。
在本发明的一些实施方式中，所述EIC芯片通过第一键合结构（例如，焊料球、微凸块等）与所述PIC芯片连接。所述连接结构包括：与所述第一键合结构电连接的第一段连接结构（例如，RDL层等）、与所述第一段连接结构电连接的第二段连接结构（例如，过孔导电结构等）、以及与所述第二段连接结构电连接的第二键合结构（例如，焊料球等）。其中，所述EIC芯片通过所述第二键合结构与所述基板连接。
在本发明的一些实施方式中，所述制造方法还包括：在所述EIC芯片的周围的至少一部分设置封装材料；在所述EIC芯片及其封装材料上形成再分布金属层，所述第一段连接结构包括所述RDL层；在所述封装材料中形成的过孔导电结构，所述第二段连接结构包括所述过孔导电结构。
在本发明的一些实施方式中，所述PIC芯片朝向所述基板的投影面积大于至少一个EIC芯片朝向所述基板的投影面积之和。在本发明的可选实施方式中，对于单个EIC芯片，所述PIC芯片朝向所述基板的投影面积可等于或小于所述EIC芯片朝向所述基板的投影面积。
在本发明的一些实施方式中，多个EIC芯片按照矩阵的形式布置。对于多个EIC芯片中的至少一个EIC芯片，从该EIC芯片周围的第二段连接结构中可选取与其布线距离非最远（即，相对较近）的第二段连接结构的连接结构进行连接。在本发明的可选实施方式中，对于多个EIC芯片中的至少一个EIC芯片，从该EIC芯片周围的第二段连接结构中选取与其布线距离最短的第二段连接结构的连接结构进行连接。可见，通过上述连接结构的连接，优化了PIC芯片的布线，具体而言，采用简单的布线结构，缩短了布线线路，减少了电压压降。
在本发明的可选实施方式中，多个EIC芯片可以线性排列布置。例如，两个EIC芯片排成一行或一列。
在本发明的可选实施方式中，一种半导体装置的制造方法包括：提供基板、EIC芯片和PIC芯片；将所述EIC芯片与所述基板进行电连接；将所述EIC芯片与所述PIC芯片进行电连接；所述EIC芯片位于所述PIC芯片与所述基板之间。可选的，在所述EIC芯片的周围的至少一部分设置封装材料；在所述封装材料中设置过孔导电结构，所述PIC芯片到所述基板的电连接路径中，包括经过所述过孔导电结构的电连接路径。可选的，可以设置至少两个EIC芯片，所述至少两个EIC芯片中，包括第一EIC芯片、第二EIC芯片，所述第一EIC芯片、第二EIC芯片之间具有封装材料，所述封装材料中设置至少一个过孔导电结构。
本领技术人员应当理解，以上所公开的仅为本发明的实施方式而已，当然不能以此来限定本发明之权利范围，依本发明实施方式所作的等同变化，仍属本发明权利要求所涵盖的范围。例如，在本发明的可选实施方式中，所述连接结构400除了采用RDL层和过孔导电结构外，还可以采用本领域已知的其他合适的电连接结构。

Claims (13)

1.一种半导体装置，其特征在于，包括
基板；
光子集成电路PIC芯片；
电子集成电路EIC芯片，所述EIC芯片位于所述PIC芯片与所述基板之间；
其中，所述PIC芯片与所述EIC芯片进行电连接。
2.如权利要求1所述的半导体装置，其特征在于，所述PIC芯片包括PIC布线结构，所述EIC芯片包括EIC布线结构；在所述PIC芯片到所述基板的电连接路径中，包括先后经过所述PIC布线结构、所述EIC布线结构、所述基板的电连接路径。
3.如权利要求1所述的半导体装置，其特征在于，所述EIC芯片的周围的至少一部分设置有封装材料，所述封装材料中设置有过孔导电结构，在所述PIC芯片到所述基板的电连接路径中，包括经过所述过孔导电结构的电连接路径。
4.如权利要求2所述的半导体装置，其特征在于，包括PIC再布线结构、第一键合结构、EIC再布线结构一、EIC再布线结构二、过孔导电结构、第二键合结构中的至少一个结构；并且，上述至少一个结构满足：
所述PIC布线结构到所述EIC布线结构的电连接路径中，先后经过PIC再布线结构、第一键合结构、EIC再布线结构一中的至少一个，和/或
所述EIC布线结构到所述基板布线结构的电连接路径中，先后经过EIC再布线结构二、过孔导电结构、第二键合结构中的至少一个。
5.如权利要求1所述的半导体装置，其特征在于，所述EIC芯片通过第一键合结构与所述PIC芯片连接；
所述EIC芯片通过连接结构与所述基板连接，所述连接结构包括：与所述第一键合结构电连接的第一段连接结构、与所述第一段连接结构电连接的第二段连接结构、以及与所述第二段连接结构电连接的第二键合结构；
其中，所述EIC芯片通过所述第二键合结构与所述基板连接。
6.如权利要求5所述的半导体装置，其特征在于，所述第一段连接结构自所述EIC芯片上的所述第一键合结构的连接点横向延伸并超出所述EIC芯片；
所述第二段连接结构自所述第一段连接结构朝着所述基板纵向延伸，并止于所述第二键合结构。
7.如权利要求5或6所述的半导体装置，其特征在于，在所述EIC芯片的周围的至少一部分设置有封装材料，所述封装材料包围所述第二段连接结构。
8.如权利要求1至6任意一项所述的半导体装置，其特征在于，所述PIC芯片朝向所述基板的投影面积大于至少一个EIC芯片朝向所述基板的投影面积之和。
9.如权利要求1所述的半导体装置，包括至少两个EIC芯片，所述至少两个EIC芯片中，包括第一EIC芯片、第二EIC芯片，所述第一EIC芯片、第二EIC芯片之间具有封装材料，所述封装材料中设置至少一个过孔导电结构。
10.如权利要求9所述的半导体装置，其特征在于，所述第一EIC芯片周围的具有两个以上的过孔导电结构，选取与其布线距离非最远的至少一个过孔导电结构进行连接。
11.一种半导体装置的制造方法，其特征在于，所述制造方法包括：
提供基板、电子集成电路EIC芯片和光子集成电路PIC芯片；
将所述EIC芯片与所述基板进行电连接；
将所述EIC芯片与所述PIC芯片进行电连接；
所述EIC芯片位于所述PIC芯片与所述基板之间。
12.如权利要求11所述的制造方法，其特征在于：
在所述EIC芯片的周围的至少一部分设置封装材料；
在所述封装材料中设置过孔导电结构，所述PIC芯片到所述基板的电连接路径中，包括经过所述过孔导电结构的电连接路径。
13.如权利要求11所述的制造方法，其特征在于，设置至少两个EIC芯片，所述至少两个EIC芯片中，包括第一EIC芯片、第二EIC芯片，所述第一EIC芯片、第二EIC芯片之间具有封装材料，所述封装材料中设置至少一个过孔导电结构。
CN202110598491.4A 2021-05-31 2021-05-31 半导体装置及其制造方法 Active CN113035858B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202110598491.4A CN113035858B (zh) 2021-05-31 2021-05-31 半导体装置及其制造方法
TW111119878A TW202247409A (zh) 2021-05-31 2022-05-27 半導體裝置及其製造方法
US17/826,791 US20220384409A1 (en) 2021-05-31 2022-05-27 Semiconductor devices and methods for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110598491.4A CN113035858B (zh) 2021-05-31 2021-05-31 半导体装置及其制造方法

Publications (2)

Publication Number Publication Date
CN113035858A true CN113035858A (zh) 2021-06-25
CN113035858B CN113035858B (zh) 2021-09-14

Family

ID=76455883

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110598491.4A Active CN113035858B (zh) 2021-05-31 2021-05-31 半导体装置及其制造方法

Country Status (3)

Country Link
US (1) US20220384409A1 (zh)
CN (1) CN113035858B (zh)
TW (1) TW202247409A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113514923A (zh) * 2021-07-01 2021-10-19 上海曦智科技有限公司 封装结构及其封装方法
CN114063229A (zh) * 2021-09-30 2022-02-18 上海曦智科技有限公司 半导体装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11726383B2 (en) * 2020-10-14 2023-08-15 California Institute Of Technology Modular hybrid optical phased arrays

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107111086A (zh) * 2015-01-26 2017-08-29 甲骨文国际公司 封装的光电模块
US20170287831A1 (en) * 2012-09-28 2017-10-05 Intel Corporation Localized high density substrate routing
CN107731778A (zh) * 2016-08-10 2018-02-23 意法半导体股份有限公司 一种制造半导体器件的方法、相应的器件及电路
CN107785358A (zh) * 2016-08-25 2018-03-09 Imec 非营利协会 半导体管芯封装及生产这种封装的方法
CN109309061A (zh) * 2017-07-27 2019-02-05 台湾积体电路制造股份有限公司 半导体封装
CN112005370A (zh) * 2018-04-24 2020-11-27 思科技术公司 用于光子芯片和电气芯片集成的集成电路桥

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170287831A1 (en) * 2012-09-28 2017-10-05 Intel Corporation Localized high density substrate routing
CN107111086A (zh) * 2015-01-26 2017-08-29 甲骨文国际公司 封装的光电模块
CN107731778A (zh) * 2016-08-10 2018-02-23 意法半导体股份有限公司 一种制造半导体器件的方法、相应的器件及电路
CN107785358A (zh) * 2016-08-25 2018-03-09 Imec 非营利协会 半导体管芯封装及生产这种封装的方法
CN109309061A (zh) * 2017-07-27 2019-02-05 台湾积体电路制造股份有限公司 半导体封装
CN112005370A (zh) * 2018-04-24 2020-11-27 思科技术公司 用于光子芯片和电气芯片集成的集成电路桥

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113514923A (zh) * 2021-07-01 2021-10-19 上海曦智科技有限公司 封装结构及其封装方法
WO2023273862A1 (zh) * 2021-07-01 2023-01-05 上海曦智科技有限公司 封装结构及其封装方法
CN113514923B (zh) * 2021-07-01 2023-04-25 上海曦智科技有限公司 封装结构及其封装方法
CN116299902A (zh) * 2021-07-01 2023-06-23 上海曦智科技有限公司 封装结构及其封装方法
CN116299902B (zh) * 2021-07-01 2024-05-28 上海曦智科技有限公司 封装结构及其封装方法
CN114063229A (zh) * 2021-09-30 2022-02-18 上海曦智科技有限公司 半导体装置

Also Published As

Publication number Publication date
TW202247409A (zh) 2022-12-01
US20220384409A1 (en) 2022-12-01
CN113035858B (zh) 2021-09-14

Similar Documents

Publication Publication Date Title
CN113035858B (zh) 半导体装置及其制造方法
US20220375864A1 (en) Multi-chip modules formed using wafer-level processing of a reconstituted wafer
KR102541861B1 (ko) 리소-에칭가능 층에 브리지를 포함하는 통합 디바이스 패키지
TWI708297B (zh) 形成半導體裝置的方法
US8120186B2 (en) Integrated circuit and method
KR101501739B1 (ko) 반도체 패키지 제조 방법
CN116169110A (zh) 一种芯片及封装方法
US7074696B1 (en) Semiconductor circuit module and method for fabricating semiconductor circuit modules
KR101652386B1 (ko) 집적회로 칩 및 이의 제조방법과 집적회로 칩을 구비하는 플립 칩 패키지 및 이의 제조방법
US9917073B2 (en) Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package
EP3547364B1 (en) Semiconductor chip and semiconductor package including the same
CN106449579A (zh) 半导体器件及制造方法
CN113192937A (zh) 半导体装置及其制造方法
CN114068446A (zh) 半导体封装件
US9721928B1 (en) Integrated circuit package having two substrates
CN113451281A (zh) 半导体封装件
CN220627791U (zh) 电子器件
US20230402359A1 (en) Semiconductor device and method of forming redistribution structures of conductive elements
US20220208712A1 (en) Multi-level bridge interconnects
US20230033087A1 (en) Semiconductor package
US20240006396A1 (en) Optical device
US20240071980A1 (en) Wire bonding directly on exposed conductive vias and interconnects and related systems and methods
US20220230981A1 (en) Arrangement of power-grounds in package structures
TW202414748A (zh) 半導體裝置
CN116682802A (zh) 电子封装件及其制法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant