TWI527187B - 嵌入式結構及其製造方法 - Google Patents

嵌入式結構及其製造方法 Download PDF

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Publication number
TWI527187B
TWI527187B TW100125576A TW100125576A TWI527187B TW I527187 B TWI527187 B TW I527187B TW 100125576 A TW100125576 A TW 100125576A TW 100125576 A TW100125576 A TW 100125576A TW I527187 B TWI527187 B TW I527187B
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Taiwan
Prior art keywords
wafer
substrate
coupled
stack
electrical signal
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TW100125576A
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English (en)
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TW201214658A (en
Inventor
秀文 周
亞伯 吳
吳嘉洛
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馬維爾國際貿易有限公司
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Publication of TW201214658A publication Critical patent/TW201214658A/zh
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Description

嵌入式結構及其製造方法 【相關申請的交叉引用】
本公開要求2010年7月20日提交的美國臨時專利申請第61/366,136號、2010年7月28日提交的美國臨時專利申請第61/368,555號的優先權，除了其中存在的任何與本說明書不一致的部分以外，通過以所有目的引用其整體而將其整體說明結合於此。本申請涉及2011年3月16日提交的美國專利申請第13/049,550號，除了其中存在的任何與本說明書不一致的部分以外，通過以所有目的引用其整體而將其整體說明結合於此。
本公開的實例涉及積體電路領域，更具體地涉及嵌入襯底內的結構的技術、構造和配置，以及與這種嵌入襯底中的結構相結合的封裝裝置。
此文所提供的背景技術說明以對本公開的內容作一般性說明為目的。發明人的某些工作(即已在此背景技術部分中作出描述的工作)以及說明書中關於某些尚未成為申請日之前的現有技術的內容，無論是以明確或隱含的方式均不被視為相對於本公開的現有技術。
通常，對於許多多晶片封裝裝置而言，封裝裝置被佈置在疊成封裝(POP(package-on-package))裝置和多晶片模組(MCM)裝置的一個中。這兩種封裝裝置一般具有高達2.6毫米的相當厚的高度。另外，對於MCM裝置，在該裝置內的晶片中之一通常是配置了一個或多個片上系統(SoC)的積體電路，而其他晶片通常是某種類型的記憶體件。來自SoC內的處理器的熱通常對記憶體件的性能有負面影響。
在各種實例中，本公開提供了一種方法，包括提供第一晶片，該第一晶片具有包括焊盤以傳遞第一晶片的電信號並將第一晶片附接到襯底層的表面。該方法還包括形成襯底的一個或多個附加層以將第一晶片嵌入襯底中並將第二晶片耦接到一個或多個附加層，該第二晶片具有包括焊盤以傳遞第二晶片的電信號的表面。第二晶片耦接到一個或多個附加層以使得在第一晶片與第二晶片之間傳遞電信號。
本公開還提供了一種設備，包括襯底，所述襯底具有(i)第一疊層，(ii)第二疊層，和(iii)佈置在第一疊層與第二疊層之間的芯材料。所述設備還包括耦接到第一疊層的第一晶片，該第一晶片包括具有焊盤以傳遞第一晶片的電信號的表面，其中第一晶片嵌入在襯底的芯材料中。所述設備還包括耦接到第二疊層的第二晶片，第二晶片具有包括焊盤以傳遞第二晶片的電信號的表面。第二晶片耦接到第二疊層以使得在第一晶片與第二晶片之間傳遞電信號。
通過以下結合附圖的詳細描述，將會理解本公開的實例。為有助於該描述，相似參考數位表示相似結構元件。本文的實例以示例的方式來說明而非以附圖所示的示圖進行限制。
圖1A示出包括晶片裝置102的封裝裝置100，在晶片裝置102中，第一晶片104嵌入於襯底106內。根據各種實例，第一晶片104是記憶體元件，並且根據一個實例，第一晶片104是動態隨機存取記憶體(DRAM)。然而，可以使用其他類型的記憶體元件。為清楚起見，沒有描述晶片裝置102內的許多部件。本文將關於圖4-圖11來詳細描述晶片裝置102。
第二晶片108耦接到晶片裝置102。第二晶片108包括焊盤110。第二晶片108經由焊球112耦接到晶片裝置102，使得第二晶片108的焊球110經由佈線結構128、130和132可通信地與第一晶片104的焊盤114耦接。因此，電信號能夠在第一晶片104與第二晶片108之間傳遞。第二晶片108還經由焊球112耦接到晶片裝置102，使得焊盤110經由佈線結構128、130和132可通信地與佈線結構126和134耦接，以將電信號傳遞到封裝裝置100外部的器件。根據各種實例，第二晶片108配置來包括一個或多個片上系統(SoC)。
根據各種實例，在第二晶片108與晶片裝置102之間提供了底部填充材料116。底部填充材料116對由焊球112形成的連接提供保護。參考圖1B，根據各種實例，不包括底部填充材料116。一般地，焊球112的尺寸越大，越不需要底部填充材料116。
參考圖1A和圖1B，根據各種實例，包括了散熱器118。散熱器118可以經由適當的粘合劑(例如環氧樹脂)耦接到晶片裝置102。另外，採用熱傳導化合物120來將散熱器118耦接到第二晶片108。熱傳導化合物120通常為摻金屬的合成樹脂膠，而散熱器118通常包括例如鋁或銅。根據各種實例，散熱器118經由熱傳導化合物120僅耦接到第二晶片108，而不耦接到晶片裝置102。
圖1C示出封裝裝置100的一個實例，其中封裝裝置100不包括散熱器118並因而不包括熱傳導化合物120。在圖1C所示的實例中，在第二晶片108與晶片裝置102之間包括底部填充材料116。圖1D示出不包括散熱器118並因而不包括熱傳導化合物120的封裝裝置100的一個實例，並且在第二晶片108與晶片裝置102之間也不包括底部填充材料116。
圖2A示出與封裝裝置100類似的封裝裝置200。封裝裝置200包括嵌入於與晶片裝置102類似的晶片裝置202內的兩個第一晶片204a、204b。從圖2A可看出，兩個第一晶片204a、204b以並排放置關係嵌入在晶片裝置202中。根據許多實例，第一晶片204a、204b是記憶體件，並且，根據一個實例，第一晶片204a、204b是動態隨機存取記憶體(DRAM)。然而，可以使用其他類型的記憶體件。
第二晶片208耦接到晶片裝置202。第二晶片208包括焊盤210。第二晶片208經由焊球212耦接到晶片裝置202，使得第二晶片208的焊盤210經由佈線結構228、230和232可通信地與第一晶片204a的焊盤214a和第一晶片204b的焊盤214b耦接。因此，電信號能夠在第一晶片204a、204b與第二晶片208之間傳遞。第二晶片208還經由焊球212耦接到晶片裝置202，使得焊盤210經由佈線結構228、230和232可通信地與佈線結構226和234耦接，以將電信號傳遞到封裝裝置200外部的器件。根據各種實例，第二晶片208配置來包括一個或多個片上系統(SoC)。
根據各種實例，在第二晶片208與晶片裝置202之間提供了底部填充材料216。底部填充材料216對由焊球212形成的連接提供保護。參考圖2B，根據各種實例，不包括底部填充材料216。
參考圖2A和圖2B，根據各種實例，包括散熱器218。散熱器218可以經由適當的粘合劑(例如環氧樹脂)耦接到晶片裝置202。另外，使用熱傳導化合物220將散熱器218耦接到第二晶片208。熱傳導化合物220一般是金屬填充樹脂膠，而散熱器218一般包括例如鋁或銅。根據各種實例，散熱器218經由熱傳導化合物220僅耦接到第二晶片208而不耦接到晶片裝置202。
圖2C示出封裝裝置200的一個實例，其中封裝裝置200不包括散熱器218，並因而不包括熱傳導化合物220。在圖2C所示的實例中，在第二晶片208與晶片裝置202之間包括底部填充材料216。圖2D示出不包括散熱器218因而不包括熱傳導化合物220的封裝裝置200的實例，並且在第二晶片208與晶片裝置202之間也不包括底部填充材料216。
圖3A示出與封裝裝置100和200類似的封裝裝置300。封裝裝置300包括嵌入於與晶片裝置102和202類似的晶片裝置302內的兩個第一晶片304a、304b。從圖3A可看出，兩個第一晶片304a、304b以與並排佈置相反的堆疊佈置的方式嵌入於晶片裝置302中。根據各種實例，第一晶片304a、304b是記憶體件，並且，根據一個實例，第一晶片304a、304b是動態隨機存取記憶體(DRAM)。然而，可以使用其他類型的記憶體件。
兩個第一晶片304a、304b一般地利用襯底通孔(TSV)裝置結合到單個器件中，並隨後嵌入於襯底306內。兩個第一晶片304a、304b每一個分別包括焊盤314a、314b。為第一晶片304a提供通孔322。
第二晶片308耦接到晶片裝置302。第二晶片308包括焊盤310。第二晶片308經由焊球312耦接到晶片裝置302，使得第二晶片308的焊盤310經由佈線結構328、330和332可通信地與第一晶片304b的焊盤314b耦接。第二晶片308還經由焊球312耦接到晶片裝置302，使得焊盤310經由佈線結構328、330和332與通孔322耦接，並因此可通信地與第一晶片304a的焊盤314a耦接。因此，電信號能夠在第一晶片304a、304b與第二晶片308之間傳遞。第二晶片308還經由焊球312耦接到晶片裝置302，使得焊盤310經由佈線結構328、330和332與佈線結構326和334可通信地耦接，以將電信號傳遞到封裝裝置300外部的器件。根據各種實例，第二晶片308配置來包括一個或多個片上系統(SoC)。
圖3A示出在第二晶片308與晶片裝置302之間包括底部填充材料316的裝置。然而，對於本文所述之其他實例，如果希望的話可以去掉底部填充材料316。類似地，儘管圖3A示出封裝裝置300包括散熱器318和熱傳導化合物320，然而如果希望的話可以如本文前面關於其他實例所述之那樣去掉散熱器318和熱傳導化合物320。
圖3B示出包括晶片裝置302且包括四個第一晶片304a-304d的封裝裝置300。兩個第一晶片304a、304b以堆疊關係佈置，同時其他兩個第一晶片304c、304d也以堆疊關係佈置。根據各種實例，第一晶片304a-304d是記憶體件，並且根據一個實例，第一晶片304a-304d是動態隨機存取記憶體(DRAM)。然而，可以使用其他類型的記憶體件。
兩個第一晶片304a、304b一般地利用TSV裝置結合到單個器件中，並隨後嵌入於襯底306內。兩個第一晶片304a、304b每一個分別包括焊盤314a、314b。為第一晶片304a提供通孔322a。其他兩個第一晶片304c、304d一般地利用TSV結合到單個器件中，並隨後嵌入襯底306內。兩個第一晶片304c、304d每一個分別包括焊盤314c、314d。為第一晶片304c提供通孔322c。
第二晶片308耦接到晶片裝置302。第二晶片308包括焊盤310。第二晶片308經由焊球312耦接到晶片裝置302，使得第二晶片308的焊盤310經由佈線結構328、330和332可通信地與第一晶片304b的焊盤314b和第一晶片304d的焊盤314d耦接。第二晶片308還經由焊球312耦接到晶片裝置302，使得焊盤310經由佈線結構328、330和332與通孔320a耦接，並因此可通信地與第一晶片304a的焊盤314a耦接。第二晶片308還經由焊球312耦接到晶片裝置302，使得焊盤310經由佈線結構328、330和332與通孔320b耦接，並因此可通信地與第一晶片304c的焊盤314c耦接。因此，電信號可以在第一晶片304a-304d與第二晶片308之間傳遞。第二晶片還經由焊球312耦接到晶片裝置302，使得焊盤310經由佈線結構328、330和332可通信地與佈線結構326和334耦接，以將電信號傳遞到封裝裝置300外部的器件。根據各種實例，第二晶片308配置來包括一個或多個片上系統(SoC)。
圖3B示出在第二晶片308與晶片裝置302之間包括底部填充材料316的裝置。然而，對於本文所述之其他實例，如果希望的話可以去掉底部填充材料316。類似地，儘管圖3B示出封裝裝置300包括散熱器318和熱傳導化合物320，然而如果希望的話可以如本文前面關於其他實例所述之那樣去掉散熱器318和熱傳導化合物320。
圖4示意性示出包括嵌入於襯底460內的晶片402的示例晶片裝置400。晶片裝置400可以用來實施本文前面關於圖1A-圖1D、圖2A-圖2D以及圖3A-圖3B所述之晶片裝置102、202和302。
襯底460包括第一疊層416、第二疊層420、和佈置在第一疊層416與第二疊層420之間的芯材料418。第一疊層416和/或第二疊層420可以包括層疊材料，比如基於環氧樹脂/樹脂的材料。在一些實例中，層疊材料包括阻燃劑4(FR4)或者雙馬來醯亞胺三嗪樹脂(BT)。芯材料418可以包括例如樹脂。在一些實例中，芯材料418包括B/C階熱固樹脂。材料不限於這些示例，並且在其他實例中可以使用其他適合於第一疊層416、第二疊層420、和/或芯材料418的材料。
襯底460還包括如圖所示的耦接到第一疊層416的第一焊接掩膜層424和耦接到第二疊層420的第二焊接掩膜層422。第一焊接掩膜層424和第二焊接掩膜層422一般地包括阻焊材料，比如環氧樹脂。在其他實例中可以使用其他適合的材料來製造第一焊接掩膜層424和第二焊接掩膜層422。
襯底460還包括分別佈置在第一疊層416、芯材料418、第二疊層420、第二焊接掩膜層422和第一焊接掩膜層424中的佈線結構426、428、430、432和434。佈線結構426、428、430、432和434一般地包括導電材料(例如銅)來傳遞晶片402的電信號。晶片402的電信號可以包括例如用於形成在晶片402中的積體電路(IC)器件(未示出)的輸入/輸出(I/O)信號和/或電源/地。
如圖所示，佈線結構426、428、430、432和434可以包括線型結構來在襯底460的一層內傳遞電信號，和/或包括通孔型結構來穿過襯底460的層傳遞電信號。佈線結構426、428、430、432和434在其他實例中可以包括所述類型以外的其他配置。儘管針對襯底460已經描述和示出了特定配置，然而使用三維(3D)封裝方法來嵌入一個或多個晶片的其他襯底也可以從本文所述之原理中獲利。
儘管在圖1A-圖1D、圖2A-圖2D和圖3A-圖3B的實例中沒有示出，然而晶片裝置400(從而晶片裝置102、202和302)可以包括一個或多個仲介層408。如圖4所示，晶片402和仲介層408嵌入於襯底460中。根據各種實例，晶片402和仲介層408嵌入在第一疊層416與第二疊層420之間的芯材料418中。根據各種實例，與嵌入在襯底460內相反，仲介層408可以由重分佈線(RDL)圖案形成。還可以通過RDL圖案生成襯底460內的其他層和/或結構。
晶片402包括半導體材料(比如矽)，並一般地包括在晶片402的有源側S1上形成的諸如用於邏輯的電晶體和/或記憶體或其他之類的電路IC器件(未示出)。與晶片402的有源側S1相對地佈置晶片402的無源側S2。一般地用有源側S1和無源側S2來稱呼晶片402的相對的表面以便於本文所述之各種配置的描述，而並不意在將其限制於晶片402的特定結構。
在一些實例中，使用粘合劑414(例如樹脂)將晶片402的無源側S2上的表面附接到第一疊層416。在其他實例中可以使用其他技術來將晶片402耦接到第一疊層416，比如使用載波群(carrier group)。
晶片402的有源側S1具有包括電介質材料404的表面。在一些實例中，電介質材料404包括電介質常數小於二氧化矽電介質常數的低k電介質材料。低k電介質材料(比如用來製造包括了尺寸約為40納米或更小的部件的晶片的那些電介質材料)通常比非低k電介質材料具有對工藝相關應力的結構缺陷更敏感的材料屬性。根據各種實例，電介質材料404包括摻雜了比如碳或氟之類材料的二氧化矽。電介質材料404在其他實例中可以包括其他低k電介質材料。
在晶片402的有源側S1上的表面還包括一個或多個焊盤406或類似結構以傳遞晶片402的電信號。一個或多個焊盤406一般地包括導電材料，比如鋁或銅。在其他實例中可以使用其他適合的材料。
如圖所示，仲介層408耦接到具有電介質材料404和一個或多個焊盤406的晶片402的表面(例如有源側S1上的表面)。仲介層408通常包括形成於半導體材料(比如矽)中的一個或多個通孔410。在一些實例中，一個或多個通孔410包括矽通孔(TSV)，該通孔完全穿過仲介層408，如圖所示。一個或多個通孔410電耦接到一個或多個焊盤406並一般地被導電材料(例如銅)填充，以進一步傳遞晶片402的電信號。
可以使用例如熱壓工藝或者回流焊工藝來將仲介層408粘結到晶片402。在一些實例中，將耦接到一個或多個通孔410的金屬或焊錫材料粘結到佈置在晶片402的有源側S1上的金屬或焊錫材料。例如，可以使用熱壓來在仲介層408與晶片402之間形成例如銅與銅、金與銅、或金與金的金屬-金屬粘結。可以使用回流焊來形成例如焊錫與焊錫或焊錫與金屬的焊錫粘結。可以使用各種結構來形成粘結，比如凸點、柱凸、和包括重佈線層(RDL)焊盤配置在內的焊盤(例如一個或多個焊盤406)。在其他實例中可以使用其他適合的材料、結構和/或粘結技術。
在一些實例中，晶片402和仲介層408兩者均包括具有相同或相似熱膨脹系統(CTE)的材料(例如矽)。晶片402和仲介層408使用具有相同或相似CTS的材料減小了與材料的加熱和/或冷卻不匹配有關的應力。
根據各種實例，仲介層408配置來保護晶片402的電介質材料404不斷裂或者不產生與將晶片402嵌入襯底460中有關的其他缺陷。例如，形成一個或多個層(例如沉積芯材料418)以將晶片402嵌入於襯底460中，可以產生導致晶片的電介質材料404中的結構缺陷的應力。尤其在形成一個或多個層以將晶片402嵌入襯底460中的期間，仲介層408向晶片402(例如電介質材料404)提供了物理緩衝、支援和增強劑。即，如本文所述耦接到仲介層408的晶片402提供了受到保護的積體電路結構450，其在結構上比單獨的晶片402本身對與製造襯底460有關的應力更具有恢復能力，導致晶片402的合格率和可靠性提高。儘管已經結合圖4所示的襯底460一般地描述了實例，然而在本公開的範圍中還包括從這些原理中獲益的其他襯底配置。
佈線結構426、428、430、432和434電耦接到一個或多個通孔410，以進一步遍及襯底460地傳遞晶片402的電信號。例如，可以使用扇入(fan-out)、扇出(fan-in)或直接(straight-up)連接來將一個或多個通孔410電耦接到佈置在芯材料418的區域中的佈線結構428。在一些實例中，在仲介層408上形成包括導電材料(例如銅)的重分佈層412，以在一個或多個通孔410與佈線結構428之間傳遞電信號。如圖所示，佈線結構426、428、430、432和434可以用來在襯底460的相對的表面上為晶片402的電信號提供電連接。
可以形成附加結構來進一步傳遞晶片402的電信號。例如，可以在襯底460的一個表面上形成一個或多個焊盤436。在所示實例中，將一個或多個焊盤436佈置在第一焊接掩膜層424中並電耦接到一個或多個通孔410。儘管未示出，但在其他實例中可以在第二焊接掩膜層422中形成一個或多個焊盤。一個或多個焊盤436一般地包括比如銅或鋁之類的導電材料。在其他實例中，可以使用其他導電材料來形成一個或多個焊盤436。
在一些實例中，在一個或多個焊盤436上形成一個或多個焊球438或類似的封裝互連結構，以便於晶片裝置400與其他電部件(例如母板之類的印刷電路板)的電耦接。根據各種實例，晶片裝置400是球柵陣列(BGA)封裝。在其他實例中，晶片裝置400可以包括其他類型的封裝。
圖5示意性示出在耦接到一起之前的晶片402和仲介層408。晶片402和仲介層408可以與已經結合圖4描述了的實例相一致。
可以使用公知的半導體製造技術來製造晶片402。例如，可以在具有多個其他晶片的晶圓上形成晶片402，其中在晶片402的有源側S1上形成了諸如電晶體之類的一個或多個IC器件(未示出)。一般地在晶片402的有源側S1上的表面上形成電介質材料404以及一個或多個焊盤406。可以將晶圓分割以提供分立形式的晶片402。
同樣地可以使用公知半導體製造技術來製造仲介層408。與晶片402相似，可以在具有多個其他仲介層的晶圓上形成仲介層408。可以穿過仲介層408來形成一個或多個通孔410，比如TSV，和/或可以在仲介層408的表面上形成重分佈層412。可以將晶圓分割以提供分立形式的仲介層408。
可以以分立或晶圓形式或兩者結合的方式按照各種技術來將晶片402和仲介層408粘結到一起。例如，可以將仲介層408分割並粘結到晶圓形式的晶片402，反之亦然。
根據各種實例，使用如本文所述之熱壓工藝或回流焊工藝來將仲介層408粘結到晶片402。即，在仲介層408和晶片402上形成一個或多個導電結構(例如柱凸、凸點、焊盤、重分佈層)，以在仲介層408與晶片402之間形成粘結。可以使用任何適合的熱壓工藝或回流焊工藝來將晶片402的一個或多個焊盤406電耦接到仲介層408的一個或多個通孔410，以在一個或多個導電結構之間形成粘結。仲介層408被粘結到其上佈置了電介質材料404和一個或多個焊盤406的晶片402的表面(例如在有源側S1上)，如箭頭所示。
圖6示意性示出將晶片402和仲介層408附接到襯底的層(例如圖4的襯底460)之後的晶片裝置600。在一些實例中，襯底的層是第一疊層416。第一疊層416可以與已經結合圖4描述了的實例相一致。
可以使用粘合劑414將晶片402附接到第一疊層416，以將晶片402的無源側S2耦接到第一疊層416。粘合劑414可以與已經結合圖4描述了的實例相一致。在其他實例中，可以使用其他技術(例如載波群)將晶片402附接到襯底的層。
圖7-圖11示意性示出在形成襯底的一個或多個附加層以將晶片嵌入襯底中之後的晶片裝置。圖7的晶片裝置700表示在形成了襯底(例如圖4的襯底460)的芯材料418之後的圖6的晶片裝置600。芯材料418可以與已經結合圖4描述了的實例相一致。
可以沉積芯材料418以如圖所示包起晶片402和仲介層408。例如，可以通過將熱固樹脂沉積到模具中來形成芯材料418。
根據一些實例，佈置仲介層408來保護晶片402的電介質材料404不遭受與芯材料418的沉積有關的應力。晶片402上的仲介層408形成了如結合圖4描述的受到保護的IC結構450。
在一些實例中，在沉積芯材料418之前在第一疊層416上形成佈線結構428。可以在將晶片402附接到第一疊層416之前在第一疊層416上形成佈線結構428。佈線結構428可以與已經結合圖4描述了的實例相一致。
圖8的晶片裝置800表示在形成芯材料418圖案並形成了如圖所示的佈線結構428和佈線結構430之後的圖7的晶片裝置700。佈線結構430可以與已經結合圖4描述了的實例相一致。
可以使用任何適合的工藝(例如平面印刷/石刻或鐳射鑽蝕)去除芯材料418的一些部分來形成芯材料418圖案。將芯材料418的一些部分去除，以允許沉積導電材料來形成佈線結構428、430。例如，可以形成芯材料418圖案來便於形成與穿過芯材料418的仲介層408的一個或多個通孔410的電連接。例如可以通過沉積導電材料來形成如圖所示通過重分佈層412而電耦接到一個或多個通孔410的佈線結構428、430，來形成電連接。
圖9的晶片裝置900表示在芯材料418上形成第二疊層420之後的晶片裝置800。第二疊層420可以與已經結合圖4描述了的實例相一致。
可以通過在芯材料418上沉積層疊材料並將層疊材料形成圖案以便於穿過層疊材料與仲介層408的一個或多個通孔410形成電連接，來形成第二疊層420。例如，可以將導電材料沉積到第二疊層420的已經去除層疊材料的形成圖案區中以形成附加佈線結構430，如圖所示。佈線結構430提供了穿過第二疊層420與一個或多個通孔410的電連接。
圖10的晶片裝置1000表示在第二疊層420上形成焊接掩膜層(例如圖4的第二焊接掩膜層422)之後的晶片裝置900。第二焊接掩膜層422可以與已經結合圖4描述了的實例相一致。
可以通過在第二疊層420上沉積和/或形成導電材料圖案來形成佈線結構432。佈線結構432可以與已經結合圖4描述了的實例相一致。可以沉積和/或形成阻焊材料來形成第二焊接掩膜層422。可以將阻焊材料形成來使得暴露一些佈線結構432以用於進一步電連接。
圖11的晶片裝置1100表示在第一疊層416中形成佈線結構426之後並在第一疊層416上形成焊接掩膜層(例如圖4的第一焊接掩膜層424)之後的晶片裝置1000。第一焊接掩膜層424、一個或多個焊盤436、一個或多個焊球438、以及佈線結構426和434可以與已經結合圖4描述了的實例相一致。
在一些實例中，將第一疊層416形成圖案以便於穿過第一疊層416形成與仲介層408的一個或多個通孔410的電連接。可以將導電材料沉積到第一疊層的形成圖案的部分中以形成提供了與一個或多個通孔410的電連接的佈線結構426。
佈線結構434形成在第一疊層416上並被電耦接到佈線結構426以傳遞晶片402的電信號。在佈線結構426上形成一個或多個焊盤436。將阻焊材料沉積和/形成圖案來形成焊接掩膜層424。可以在阻焊材料中形成開口，以允許在一個或多個焊盤434上形成/放置焊球438。
本文所述之封裝裝置100、200和300一般地可以具有大約1.2毫米的厚度。另外，將第二晶片108、208和308(配置有一個或多個SoC)與第一晶片104、204a、204b和304a-304d(當具有記憶體形式時)分開，導致來自第二晶片的影響第一晶片的性能的熱更少。散熱器118、218和318以及熱傳導化合物120、220和320也有助於防止第二晶片的熱影響第一晶片的性能。
圖12示出根據本公開的一個實例的示例方法1200。在1204，提供第一晶片，使得第一晶片具有包括焊盤以傳遞第一晶片的電信號的表面。在1208，將第一晶片附接到襯底的層。在1212，形成襯底的一個或多個附加層以將第一晶片嵌入在襯底中。在1216，將第二晶片耦接到一個或多個附加層，其中第二晶片具有包括焊盤以傳遞第二晶片的電信號的表面。在一個實例中，將第二晶片耦接到一個或多個附加層，使得電信號在第一晶片與第二晶片之間傳遞。
本說明可能使用了基於透視的描述，比如向上/向下、上方/下方、和/或頂部/底部。這種描述僅用於方便討論，並不意在將本文所屬的實例的應用限制於任何具體方向。
出於本公開的目的，短語“A/B”表示A或者B。出於本公開的目的，短語“A和/或B”表示“(A)、(B)或者(A和B)”。出於本公開的目的，短語“A、B和C的至少一個”表示“(A)、(B)、(C)、(A和B)、(A和C)、(B和C)、或者(A、B和C)”。出於本公開的目的，短語“(A)B”表示“(B)或(AB)，即A是可選的元素。
以最有助於理解所公開主題的方式依次地將各個操作描述為多個獨立的操作。然而，描述的次序並不意在暗示這些操作必須基於這種次序。具體地，這些操作不一定以所呈現的次序來執行。可以按照與所述實例不同的次序來執行操作。可以執行各種附加的操作和/或在附加的實例中可以省略所描述的操作。
說明書使用了短語“在一個實例中”、“在實例中”或類似語言，其每一個都可以指代一個或多個相同的或者不同的實例。另外，關於本公開的實例所使用的術語“包括”、“包含”、“具有”等是同義的。
術語晶片。積體電路、單片器件、半導體器件、晶片和微電子器件在微電子領域中通常是可互換使用的。由於在本領域中通常都能理解，因此本發明可應用於上面的所有情況。
儘管本文已經示出和說明了特定實例，然而可以在不脫離本公開範圍的情況下以寬泛的各種替代方案和/或等價實例或者計算來實現相同目的的實施方案來代替所示和所說明的實例。該公開意在覆蓋本文討論的實例的任何修改或變型。因此，很顯然，本文所述之實例僅由請求項及其等同物限制。
100．．．封裝裝置
102．．．晶片裝置
104．．．第一晶片
106．．．襯底
108．．．第二晶片
110．．．焊盤
112．．．焊球
116．．．底部填充材料
118．．．散熱器
120．．．熱傳導化合物
128．．．佈線結構
130．．．佈線結構
132．．．佈線結構
200．．．封裝裝置
202．．．晶片裝置
204a．．．第一晶片
204b．．．第一晶片
208．．．第二晶片
210．．．焊盤
212．．．焊球
214a．．．焊盤
214b．．．焊盤
216．．．底部填充材料
218．．．散熱器
220．．．熱傳導化合物
226．．．佈線結構
228．．．佈線結構
230．．．佈線結構
232．．．佈線結構
234．．．佈線結構
300．．．封裝裝置
302．．．晶片裝置
304a．．．第一晶片
304b．．．第一晶片
304c．．．第一晶片
304d．．．第一晶片
306．．．襯底
308．．．第二晶片
310．．．焊盤
312．．．焊球
314a．．．焊盤
314b．．．焊盤
314c．．．焊盤
314d．．．焊盤
316．．．底部填充材料
318．．．散熱器
320．．．熱傳導化合物
320a．．．通孔
320b．．．通孔
322．．．通孔
322a．．．通孔
322c．．．通孔
326．．．佈線結構
328．．．佈線結構
330．．．佈線結構
332．．．佈線結構
334．．．佈線結構
316．．．底部填充材料
318．．．散熱器
320．．．熱傳導化合物
400．．．晶片裝置
402．．．晶片
404．．．電介質材料
406．．．焊盤
408．．．仲介層
410．．．通孔
412．．．重分佈層
414．．．粘合劑
416．．．第一疊層
418．．．芯材料
420．．．第二疊層
422．．．第二焊接掩膜層
424．．．第一焊接掩膜層
426．．．佈線結構
428．．．佈線結構
430．．．佈線結構
432．．．佈線結構
434．．．佈線結構
436．．．焊盤
438．．．焊球
450．．．IC結構
460．．．襯底
600．．．晶片裝置
700．．．晶片裝置
800．．．晶片裝置
900．．．晶片裝置
1000．．．晶片裝置
1100．．．晶片裝置
S1．．．有源側
S2．．．無源側
圖1A-圖1D示意性地示出包括示例晶片裝置的一個示例封裝裝置，該示例晶片裝置包括嵌入於襯底中的一個晶片。
圖2A-圖2D示意性地示出包括另一示例晶片裝置的另一示例封裝裝置，該另一示例晶片裝置包括嵌入於襯底中的兩個晶片。
圖3A示意性地示出包括另一示例晶片裝置的另一示例封裝裝置，該另一示例晶片裝置包括嵌入於襯底中的兩個晶片。
圖3B示意性地示出包括另一示例晶片裝置的另一示例封裝裝置，該另一示例晶片裝置包括嵌入於襯底中的四個晶片。
圖4示意性地示出包括嵌入於襯底中的一個晶片的示例晶片裝置。
圖5示意性地示出在耦接到一起之前的晶片和仲介層。
圖6示意性地示出在將晶片和仲介層附接到襯底的層之後的晶片裝置。
圖7-11示意性地示出在形成襯底的一個或多個附加層以將晶片嵌入該襯底中之後的晶片裝置。
圖12是製造本文所述封裝裝置的方法的工藝流程圖。

Claims (18)

  1. 一種附接多晶片到一襯底的方法，包括：提供第一晶片，所述第一晶片具有包括焊盤以傳遞所述第一晶片的電信號的表面；將所述第一晶片附接到襯底的層；形成所述襯底的一個或多個附加層以將所述第一晶片嵌入所述襯底中；和將第二晶片耦接到所述一個或多個附加層，所述第二晶片具有包括焊盤以傳遞所述第二晶片的電信號的表面，其中將所述第二晶片耦接到所述一個或多個附加層，以使得在所述第一晶片與所述第二晶片之間傳遞電信號；以及將散熱器耦接到所述第二晶片，其中在所述第二晶片的第一表面將所述第二晶片耦接到所述一個或多個附加層，和其中在與所述第二晶片的第一表面相對的所述第二晶片的第二表面將所述散熱器耦接到所述第二晶片。
  2. 如請求項1所述之方法，其中將所述第二晶片耦接到所述一個或多個附加層包括：使用焊球將所述第二晶片耦接到所述一個或多個附加層。
  3. 如請求項2所述之方法，還包括：在所述第二晶片與所述一個或多個附加層之間提供底部填充材料。
  4. 一種附接多晶片到一襯底的方法，包括：提供第一晶片，所述第一晶片具有包括焊盤以傳遞所述第一晶片的電信號的表面；將所述第一晶片附接到襯底的層；形成所述襯底的一個或多個附加層以將所述第一晶片嵌入所述襯底中；和將第二晶片耦接到所述一個或多個附加層，所述第二晶片具有包括焊盤以傳遞所述第二晶片的電信號的表面，其中將所述第二晶片耦接到所述一個或多個附加層，以使得在所述第一晶片與所述第二晶片之間傳遞電信號；提供第三晶片，所述第三晶片具有包括焊盤以傳遞所述第三晶片的電信號的表面；和將所述第三晶片附接到所述襯底的層，其中形成所述襯底的一個或多個附加層以將所述第一晶片嵌入所述襯底中包括形成所述襯底的一個或多個附加層以將所述第三晶片嵌入所述襯底中，和其中將所述第二晶片耦接到所述一個或多個附 加層，以使得在所述第三晶片與所述第二晶片之間傳遞電信號。
  5. 如請求項4所述之方法，其中提供所述第三晶片包括：在所述第一晶片旁邊以基本上並排放置的方式來提供所述第三晶片。
  6. 如請求項4所述之方法，其中提供所述第三晶片包括：在所述第一晶片上方提供所述第三晶片，以使得所述第三晶片與所述第一晶片處於基本上堆疊放置的方式。
  7. 如請求項6所述之方法，還包括：提供第四晶片，所述第四晶片具有包括焊盤以傳遞所述第四晶片的電信號的表面；和提供第五晶片，所述第五晶片具有包括焊盤以傳遞所述第五晶片的電信號的表面，其中在所述第一晶片上方提供所述第三晶片，以使得所述第三晶片與所述第一晶片處於基本上堆疊放置的方式，其中在所述第四晶片上方提供所述第五晶片，以使得所述第五晶片與所述第四晶片處於基本上堆疊放置的方式，其中以基本上並排放置的方式來佈置所述第一 和第三晶片與所述第四和第五晶片，其中形成所述襯底的一個或多個附加層以將所述第一晶片嵌入所述襯底中包括形成所述襯底的一個或多個附加層以將所述第四和第五晶片嵌入所述襯底中，其中將所述第二晶片耦接到所述一個或多個附加層，以使得在所述第四晶片與所述第二晶片之間傳遞電信號，和其中將所述第二晶片耦接到所述一個或多個附加層，以使得在所述第五晶片與所述第二晶片之間傳遞電信號。
  8. 一種耦接多晶片的設備，包括：襯底，具有(i)第一疊層、(ii)第二疊層、和(iii)佈置在所述第一疊層與所述第二疊層之間的芯材料，第一晶片耦接到所述第一疊層，所述第一晶片具有包括焊盤以傳遞所述第一晶片的電信號的表面，其中所述第一晶片嵌入於所述襯底的所述芯材料中；和耦接到所述第二疊層的第二晶片，所述第二晶片具有包括焊盤以傳遞所述第二晶片的電信號的表面，其中將所述第二晶片耦接到所述第二疊層，以使 得在所述第一晶片與所述第二晶片之間傳遞電信號；以及耦接到所述第二晶片的散熱器；其中以所述第二晶片的第一表面將所述第二晶片耦接到所述第二疊層；和其中以與所述第二晶片的第一表面相對的所述第二晶片的第二表面將所述散熱器耦接到所述第二晶片。
  9. 如請求項8所述之設備，其中通過焊球將所述第二晶片耦接到所述第二疊層。
  10. 如請求項9所述之設備，還包括：在所述第二晶片與所述第二疊層之間的底部填充材料。
  11. 一種耦接多晶片的設備，包括：襯底，具有(i)第一疊層、(ii)第二疊層、和(iii)佈置在所述第一疊層與所述第二疊層之間的芯材料，第一晶片耦接到所述第一疊層，所述第一晶片具有包括焊盤以傳遞所述第一晶片的電信號的表面，其中所述第一晶片嵌入於所述襯底的所述芯材料中；和耦接到所述第二疊層的第二晶片，所述第二晶片具有包括焊盤以傳遞所述第二晶片的電信號的表 面，其中將所述第二晶片耦接到所述第二疊層，以使得在所述第一晶片與所述第二晶片之間傳遞電信號；以及耦接到所述第一疊層的第三晶片，所述第三晶片具有包括焊盤以傳遞所述第三晶片的電信號的表面；其中所述第三晶片嵌入於所述襯底的芯材料中，並且其中所述第二晶片耦接到所述第二疊層，以使得在所述第三晶片與所述第二晶片之間傳遞電信號。
  12. 如請求項11所述之設備，其中所述第三晶片以下列中的一種方式佈置：(i)相對於所述第一晶片基本上並排地放置；或(ii)相對於所述第一晶片基本上堆疊地放置。
  13. 如請求項11所述之設備，還包括：耦接到所述第一疊層的第四晶片，所述第四晶片具有包括焊盤以傳遞所述第四晶片的電信號的表面，其中所述第四晶片嵌入於所述襯底的所述芯材料中；和耦接到所述第一疊層的第五晶片，所述第五晶片具有包括焊盤以傳遞所述第五晶片的電信號的表面，其中所述第五晶片嵌入於所述襯底的所述芯材料中， 其中在所述第一晶片上方提供所述第三晶片，以使得所述第三晶片與所述第一晶片處於基本上堆疊放置的方式，其中在所述第四晶片上方提供所述第五晶片，以使得所述第五晶片與所述第四晶片處於基本上堆疊放置的方式，其中以基本上並排放置的方式來佈置所述第一和第三晶片與所述第四和第五晶片，其中所述第二晶片耦接到所述第二疊層，以使得在所述第四晶片與所述第二晶片之間傳遞電信號，和其中所述第二晶片耦接到所述第二疊層，以使得在所述第五晶片與所述第二晶片之間傳遞電信號。
  14. 如請求項8所述之設備，其中所述第一晶片是記憶體件，所述第二晶片是配置來包括一個或多個片上系統(SoC)的積體電路。
  15. 一種封裝裝置，包括：襯底，具有(i)第一疊層、(ii)第二疊層、和(iii)佈置在所述第一疊層與所述第二疊層之間的芯材料，具有耦接到所述第一疊層的第一表面的第一晶片，所述第一晶片具有與所述第一晶片的所述第一表面相對的第二表面，其中所述第一晶片的所述第 二表面具有焊盤以傳遞所述第一晶片的電信號，且其中所述第一晶片嵌入於所述襯底的所述芯材料中以使得所述芯材料由所述第二疊層分開至少一部份的所述第一晶片的所述第二表面；以及耦接到所述第二疊層的第二晶片，所述第二晶片具有包括焊盤以傳遞所述第二晶片的電信號的表面，其中將所述第二晶片耦接到所述第二疊層，以使得在所述第一晶片與所述第二晶片之間傳遞電信號。
  16. 如請求項15所述之封裝裝置，其中所述第二疊層由所述第二晶片分開所述第一晶片。
  17. 一種附接多晶片到一襯底的方法，包括：提供第一晶片，所述第一晶片具有(i)第一表面、(ii)與所述第一表面相對的第二表面、(iii)與所述第一表面垂直的第三表面、和(iv)與所述第一表面垂直的第四表面，其中所述第一晶片的所述第二表面包括第一焊盤，其中所述第一晶片的所述第一焊盤被設置以傳遞所述第一晶片的電信號；將所述第一晶片的所述第一表面附接到襯底的層；將所述第一晶片的第二表面附接到插入物的第一表面，其中所述插入物包括第一通孔，且其中所 述插入物具有(i)所述第一表面、(ii)第二表面相對於所述第一表面、(iii)第三表面垂直於所述第一表面、及(iv)第四表面垂直於所述第一表面；形成所述襯底的一個或多個附加層以將所述第一晶片及所述插入物嵌入所述襯底中，使所述襯底的所述所述一個或多個附加層被附接到(i)所述第一晶片的所述第三表面和所述第四表面以及(ii)所述插入物的所述第三表面和所述第四表面；以及將第二晶片耦接到所述襯底的所述一個或多個附加層，其中所述第二晶片具有包括第二焊盤的表面，且其中所述第二晶片的所述第二焊盤被設置以傳遞所述第二晶片的電信號；其中將所述第二晶片耦接到所述襯底的所述一個或多個附加層，以使得在所述第一晶片與所述第二晶片之間傳遞電信號經由(i)所述第一晶片的所述第一焊盤、(ii)所述插入物的所述第一通孔、(iii)部分設置在所述襯底的所述一個或多個附加層中的傳遞結構、以及(iv)所述第二晶片的所述第二焊盤。
  18. 如請求項17所述之方法，進一步包括：將散熱器耦接到所述第二晶片，其中在所述第二晶片的第一表面將所述第二晶 片耦接到所述襯底的所述一個或多個附加層，和其中在與所述第二晶片的第一表面相對的所述第二晶片的第二表面將所述散熱器耦接到所述第二晶片。
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CN103168358A (zh) 2013-06-19
US8618654B2 (en) 2013-12-31
US9087835B2 (en) 2015-07-21
US20120049364A1 (en) 2012-03-01
WO2012012338A1 (en) 2012-01-26
EP2596531B1 (en) 2018-10-03
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US20140106508A1 (en) 2014-04-17
CN103168358B (zh) 2016-05-25

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