CN101211874A - 超薄芯片尺寸封装结构及其方法 - Google Patents

超薄芯片尺寸封装结构及其方法 Download PDF

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CN101211874A
CN101211874A CNA2007103075245A CN200710307524A CN101211874A CN 101211874 A CN101211874 A CN 101211874A CN A2007103075245 A CNA2007103075245 A CN A2007103075245A CN 200710307524 A CN200710307524 A CN 200710307524A CN 101211874 A CN101211874 A CN 101211874A
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plural
dielectric layer
chip scale
super thin
thin chip
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杨文焜
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Yupei Science & Technology Co Ltd
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Yupei Science & Technology Co Ltd
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Abstract

本发明揭露超薄芯片尺寸封装结构及其方法。超薄芯片尺寸封装结构包含基板；晶圆，其附有具复数接合垫的复数个晶粒；第一介电层；穿透导电层；第二介电层；重分布层导线；以及导电凸块，其依序形成于晶圆上。本发明因将封装结构的尺寸最小化，故可提供超薄芯片尺寸封装结构。特别是用于制造超薄芯片尺寸封装的方法包含切割晶圆，背面研磨晶圆的背侧，以及蚀刻基板的背侧，以提供超薄芯片尺寸封装结构。因此，本发明可最小化封装结构尺寸以及有效改善制造工艺。

Description

超薄芯片尺寸封装结构及其方法
技术领域
本发明有关于芯片尺寸封装，特定而言是有关于可最小化封装尺寸及有效改善制造工艺的超薄芯片尺寸封装结构及其方法。
背景技术
近年来，高科技电子制造业发展出更具特色包装且更为人性化的电子产品。此类展示于商品橱窗的新产品于设计上较为轻薄短小。于此类电子产品的制造当中，关键组件必定为每一电子产品中的集成电路(IC)芯片。
半导体科技的快速发展已引导半导体封装尺寸缩小、多接脚采用、细间距采用、电子组件最小化等的快速进展。晶圆级封装的目的及优点包含降低生产成本、通过利用较短的导电线路径而降低寄生电容(parasitic capacitance)及寄生电感(parasitic inductance)所造成的影响、获得较佳讯杂比(SNR)。此外，晶圆级封装产品的尺寸接近于芯片的尺寸，故芯片尺寸决定封装的体积。
传统上形成芯片尺寸封装(CSP)的方法为切割半导体晶圆成半导体晶粒，接着架置半导体晶粒至作为封装基底的基板上的预定位置且结合至其上，整体以树脂密封，之后，密封树脂及基板是一同切割成半导体晶粒间部分的块体。于另一传统方法中，半导体晶圆(未切割成半导体晶粒)架置于基板上且结合至其上，随后同步切割半导体晶圆及基板，经切割并分离的半导体晶粒及封装基座遂以树脂密封。
此外，集成电路芯片的操作性、表现及寿命受其电路设计、晶圆制造及芯片封装所大为影响。本发明将着重于芯片封装技术。由于集成电路芯片的特性及速度快速提升，故必须加强电路的传导性以降低晶粒至外部电路的信号延迟及衰减。提供良好散热及保护集成电路芯片并具有微小的整体封装尺寸的芯片封装对于较高效能芯片而言为必须。此类为芯片封装中所欲达的目标。
现存的芯片封装技术有许多种类，例如锡球阵列(BGA)、打线接合(wirebonding)、覆晶(flip chip)，以用于透过晶粒与基板上的接合点架置晶粒于基板上。内部导线有助于扩散基板底部的接合点。焊锡球分别植入于接合点上，以作用为晶粒电性连接至外部电路的接口。同样地，针脚阵列(PGA)相当类似于锡球阵列(BGA)，其以针脚替代锡球于基板上，且针脚阵列(PGA)亦作用为晶粒电性连接至外部电路的接口。
锡球阵列(BGA)及针脚阵列(PGA)封装均需要打线或覆晶以用于架置晶粒于基板上。基板内的内部导线扩散基板上的接合点，且至外部电路的电性连接通过接合点上的焊锡球或针脚予以实行。因此，此类传统方法无法缩短信号传输路径的距离，而事实上增加信号路径距离。如此会增加信号的延迟及衰减并降低芯片效能。
然而，于制造方法中，晶圆级芯片尺寸封装(WLCSP)通过利用晶粒的周围区域作为接合点，而具有能于晶粒上直接印刷重分布电路的优点。其通过于晶粒的表面上重分布面阵列(area array)而达成，如此可完全利用晶粒的整体面积。接合点通过形成覆晶凸块而设置于重分布电路上，故晶粒的底侧直接连接至具微分隔接合点的印刷电路板(PCB)。
虽然晶圆级芯片尺寸封装(WLCSP)可大为缩短信号路径距离，然而当晶粒及内部组件的整合更为高阶时于晶粒表面上容纳所有接合点仍非常困难。当整合更为高阶时晶粒上的针脚数量增加，故面阵列中的针脚重分布变为难以达成。即使针脚重分布成功，针脚间的距离将会过小而无法符合印刷电路板(PCB)的间距。换言之，由于以上所述此样先前技术的程序及结构将受困于产率及可靠度问题。先前方法的另一缺点较高成本及制造工艺费时。
发明内容
鉴于上述，本发明提供用于超薄芯片尺寸封装的新结构及方法，其将晶圆级封装的封装结构厚度最小化以克服上述缺点。
本发明将叙述一些较佳实施例。然而，此领域的技术者应得以领会，除此处详细叙述的外本发明可广泛实行于其它实施例。本发明的范围除权利要求书所明定的外不特别受限。
本发明的一目的为提供能够将芯片尺寸封装的尺寸最小化的芯片尺寸封装结构。
本发明的另一目的为提供可有效改善芯片尺寸封装的制造工艺的用于芯片尺寸封装的方法。
本发明提供超薄芯片尺寸封装结构，其包含基板，复数晶粒，其具有形成于其上的复数接合垫，第一介电层，其形成于复数晶粒的上以暴露接合垫的部分表面，连通导电层，其填充于第一介电层中的空隙内，重分布层导线，其形成于连通导电层及第一介电层上，第二介电层，其形成于第一介电层及重分布导线上以暴露重分布层导线的部分表面，复数导电凸块(例如焊锡)，其形成于第二介电层中的空隙内，以及覆盖保护层，其形成于基板的下方，其中复数导电凸块可透过连通导电层及重分布层导线而电性连接至接合垫。
本发明提供用于制造超薄芯片尺寸封装的方法，包含预备附有复数晶粒的晶圆，复数晶粒具有复数接合垫形成于其上，切割附着于切割胶带上的晶圆以形成复数狭长孔直到达第一预定深度，附着晶圆于研磨胶带架下方且背面研磨晶圆直到达第二预定深度，接合晶圆至具晶粒黏着膜的基板，移除研磨胶带架，真空填充核心黏胶至复数晶粒及晶粒黏着膜间的空隙内，形成第一介电层于晶圆上且暴露复数晶粒的部分表面，溅镀连通导电层(种子金属层)以填充复数第一介电层中的空隙，涂布重分布层导线于连通导电层及第一介电层上以暴露复数第一介电层的部分表面，涂布复数第二介电层以填充连通导电层间的空隙且暴露连通导电层的部分表面，蚀刻基板的背侧以去除部分区域的基板，形成覆盖保护层于基板的背侧上，以及焊接复数导电凸块于复数第二介电层间的空隙上。
附图说明
本发明可通过说明书中若干较佳实施例及详细叙述以及后附图式得以了解。然而，此领域的技术者应得以领会所有本发明的较佳实施例用以说明而非用以限制本发明的权利要求，其中：
图1是根据本发明说明超薄芯片尺寸封装的独立分离结构的概要示意图。
图2a至图2g是根据本发明说明将晶圆形成为板型的横切面示意图。
图3a是根据本发明说明于蚀刻后基板的背侧的横切面示意图。
图3b是根据本发明说明于基板背侧上形成覆盖保护层的横切面示意图。
图4a至图4d是根据本发明说明于图3b的板型上形成第一介电层、连通导电层、重分布层导线、第二介电层及导电凸块的横切面示意图。
图5是根据本发明说明切割超薄芯片尺寸封装的横切面示意图。
图6是根据本发明说明制造超薄芯片尺寸封装的方法的流程图。
附图标号：
100超薄芯片尺寸封装        101覆盖保护层
102基板                    103晶粒黏着膜
104晶粒                    105接合垫
106第一介电层              107连通导电层
108重分布层导线            109第二介电层
110凸块底层金属            111导电凸块
112核心黏胶                200晶圆
201狭长孔                  202切割胶带
203第一研磨胶带架          204背面研磨区域
205基板                    206晶粒黏着膜
207核心黏胶                208第二研磨胶带架
209覆盖保护层              210第一介电层
211连通导电层            212重分布层导线
213第二介电层            214导电凸块
215箭头                  216第二切割胶带
220接合垫
300、302、304、306、308、310、312、314、316、318、320、322、324步骤
具体实施方式
本发明将以较佳实施例及所附图式加以详细叙述。然而，此领域的技术者将得以领会，本发明的较佳实施例为说明而叙述，而非用以限制本发明的权利要求。除此处明确叙述的较佳实施例之外，本发明可广泛实行于其它实施例，且本发明的范围除权利要求书所明定之外不特别受限。
参照图1，其是根据本发明的超薄芯片尺寸封装100的独立分离结构的概要示意图。超薄芯片尺寸封装100结构为切割后的芯片尺寸封装的独立分离结构。超薄芯片尺寸封装100包含覆盖保护层101、基板102、晶粒黏着膜103、晶粒104、复数接合垫105、第一介电层106、连通导电层107、重分布层导线108、第二介电层109、凸块底层金属110、复数导电凸块111以及核心黏胶112。
具复数接合垫105的晶粒104形成于基板102上，而接合垫105形成于晶粒104内且于其顶侧，因此接合垫105的表面可暴露出。晶粒黏着膜103形成于晶粒104与基板102之间，且设置于每一晶粒104的下方。核心黏胶112填充于环绕晶粒104及晶粒黏着膜103的空隙内。覆盖保护层101形成于基板102的下表面。
此外，第一介电层106形成于具复数接合垫105的晶粒104及核心黏胶112上，且晶粒104的部分表面通过随后的暴露/形成或光微影蚀刻程序而暴露出。接着，连通导电层107(通过溅镀种子金属钛/铜)形成于晶粒104的接合垫105的暴露表面上，以耦合至晶粒104及建构重分布层导线108。重分布层导线108部分形成于连通导电层107及第一介电层106上(通过利用光阻(PR)形成重分布层的图形及电镀铜/金或铜/镍/金而后剥除光阻及湿式金属蚀刻以形成重分布层导线108)，以覆盖连通导电层107。第二介电层109形成于第一介电层106及重分布层导线108上，且重分布层导线108的部分表面暴露出以电性连接至复数导电凸块111。
于一实施例中，本结构还包含凸块底层金属110，其形成于重分布层导线108及导电凸块111之间以避免重分布层导线108及导电凸块111间的交互扩散(inter-diffusion)。
于一实施例中，覆盖保护层101的厚度b约为30至50微米。基板102的厚度c约为50至60微米。晶粒黏着膜103的厚度d约为10微米，以及晶粒104的厚度e约为50微米。第一介电层106的厚度f约为5微米，以及第二介电层109的厚度g约为20微米。导电凸块111的厚度h约为80至200微米。核心黏胶112的宽度i约为20微米，且宽度i指从晶粒104的边缘至独立分离结构的切割边缘的距离。因此，芯片尺寸封装100的总厚度a不含导电凸块111的厚度约为小于200微米。是故，本发明可提供超薄芯片尺寸封装结构。
本发明更提供用于制造超薄芯片尺寸封装100结构的方法。图2a至图5显示用于形成超薄芯片尺寸封装100的过程的横切面示意图。
图2a至图2g是根据本发明说明将晶圆形成为板型的横切面示意图。晶圆200具有复数晶粒，其附有形成于其上的复数接合垫220。参照图2a，晶圆200以厚度约2至3微米的介电层涂布。晶圆200置于切割胶带202上，且切割步骤通过具特定厚度的切割刀片于晶圆200上实行直到达第一预定深度，藉此于晶粒间形成复数狭长孔201，如图2b所示。于切割后晶圆200具有复数狭长孔201形成于晶粒之间，且狭长孔201的宽度大体上等于该切割刀片的特定厚度。其后，切割胶带202从晶圆200的背侧予以移除。
于切割晶圆200到达第一预定深度后，第一研磨胶带架203装附于具有晶圆200上的晶粒的表面上。晶圆200从其背侧予以背面研磨直到达第二预定深度，且背面研磨区域204予以去除，如图2c的虚线区域所示。上述程序称作为研磨前切割(Dicing Before Lapping；DBL)。
于一实施例中，第一预定深度约为75微米，以及第二预定深度约为50微米。此领域的技术者应注意，第二预定深度大体上为小于或等于第一预定深度，以确保晶圆200分割成复数独立晶粒，此外应注意以上深度均从晶圆(晶粒)的主动表面开始计算。第一及第二预定深度亦可根据不同传导需求而予以修改。
于一实施例中，基板205的材料包含刚性材料，可为金属、合金、柯弗合金(Kover)、有机物、玻璃、陶瓷或硅。此外，合金最好为镍铁合金(Alloy42)，其由镍及铁所组成的合金，其膨胀系数使其适于结合至微型电路中的硅芯片且其由42％镍及58％铁所组成。合金亦可为柯弗合金(Kover)，其由29％镍、17％钴及54％铁所组成。
于一实施例中，核心黏胶112的材料包含硅胶、含硅树脂或环氧树脂，而覆盖保护层209的材料包含环氧树脂及橡胶。于一实施例中，第一介电层210及第二介电层213的材料包含苯环丁烯(BCB)、硅氧烷聚合物(SINR)或聚亚酰胺(PI)。此领域的技术者应注意，本发明所提及的材料只用以说明而非用以限制本发明。
参照图2d，图2c的结构的背侧接合至具有复数晶粒黏着膜206的基板2050以形成图2e所示的组合结构。参照图2f，预先固化晶粒200与基板205间的晶粒黏着膜206，接着从晶圆200剥除第一研磨胶带架203。此处的剥除处理亦称为贴布去除(detapping)。于贴布去除第一研磨胶带架203后，印刷核心黏胶112以填入晶圆200的晶粒间的空隙及晶粒黏着膜206间的空隙，如图2g所示。
其后，于真空环境下处理附着于基板205上的晶圆200，且软烘烤(soft-baked)核心黏胶112。附着于基板205上的晶圆200可选择性加以旋转以确定结构的一致性。核心黏胶112由于其感光特性故通过光屏蔽而去除其部分区域以开启晶粒区域。通过电浆蚀刻法(plasma etching method)蚀刻晶圆200，接着通过快速倾卸冲洗(quick dump rinse)法清洗晶圆200以去除残留物。
参照图3a，图2g的结构的晶圆200贴附至第二研磨胶带架208的下方，且基板205的部分背侧区域，即蚀刻区域205a，通过蚀刻予以去除，如图3a的虚线区域所示。之后，通过快速倾卸冲洗(quick dump rinse)法清洗晶圆200的背侧，且从晶圆200贴布去除(detapping)第二研磨胶带架208。于图3b，覆盖保护层209印刷于晶圆200的背侧，而后固化覆盖保护层209。
于一实施例中，去除蚀刻区域205a的步骤通过湿式蚀刻法实行。
参照图4a至图4d，其根据本发明说明于图3b的板型上形成第一介电层210、连通导电层211、重分布层导线212、第二介电层213及导电凸块214的概要示意图。于图4a，制作第一介电层210的图样于晶圆200上，而附着于晶圆200上的复数接合垫220暴露出。其后，溅镀种子金属层(连通导电层211)于附着于晶圆200上的第一介电层210及复数接合垫220上，而种子金属层的材料包含钛/铜。接续，于种子金属层上涂布光阻层(未图示)、软烘烤光阻层及光遮蔽光阻层。光阻层予以显影以开启重分布层(RDL)的图形，并通过电浆清洗。重分布层导线212电镀于第一介电层210间的空隙，而重分布层导线212的材料包含铜/金或铜/镍/金。于剥除光阻层后，种子金属层通过湿式蚀刻予以去除，以于连通导电层211及第一介电层210上形成重分布层导线212，而第一介电层210的部分表面暴露出，如图4b所示。
参照图4c，第二介电层213涂布于第一介电层210及重分布层(RDL)导线212上，而后光遮蔽第二介电层213以开启导电凸块金属垫。第二介电层213的开启区域通过电浆进行清洗，之后固化第二介电层213。
接续，种子金属层(未图示)溅镀于第二介电层213上，且重分布层(RDL)导线212的暴露表面(用于导电凸块金属垫)予以开启以用于凸块底层金属(UBM)。第二光阻层涂布于种子金属层上，以及第二光阻层经过软烘烤(soft-baked)及光遮蔽以用于凸块底层金属(UBM)。第二光阻层予以显影以开启导电凸块金属垫，而后通过电浆法进行清洗。铜/镍/金膜通过电镀而制成。其后，剥除第二光阻层，湿式蚀刻种子金属层以形成凸块底层金属(UBM)，以及通过快速倾卸冲洗(QDR)法清洗。焊锡糊剂(solder pastes)选择性通过红外线回焊(IR-reflow)法印刷于凸块底层金属(UBM)垫上以形成凸块。复数导电凸块214结合于凸块底层金属(UBM)上以填入第二介电层213间的空隙，如图4d所示。
参照图5，其根据本发明说明切割超薄芯片尺寸封装以实施最终测试及切单程序的横切面示意图。接着，板型晶圆级最终测试予以实行，以及产生具测试结果的晶圆对应图(wafer map)。图4d的结构置于第二切割胶带216上，接着从切割位置例如箭头215所指的位置切割图4d的结构以分离并形成独立的芯片尺寸封装。芯片尺寸封装(CSP)经取放于托盘上以FGS运输。
根据本发明的观点，本发明还提供用于制造超薄芯片尺寸封装100的方法。图6是根据本发明说明制造超薄芯片尺寸封装100的方法的流程图。其步骤说明如下。
首先，于步骤300，预备附有复数晶粒的晶圆200，复数晶粒具有复数接合垫220形成于其上。于步骤302，切割附着于切割胶带202上的晶圆200以形成复数狭长孔201直到达第一预定深度。接着，于步骤304，将晶圆200附着于研磨胶带架203的下方，且背面研磨晶圆200的背侧直到达第二预定深度。于步骤306，将附着于研磨胶带架203下方的晶圆200结合至具有复数晶粒黏着膜206的基板205。于步骤308，移除研磨胶带架203以暴露晶圆200的表面。于步骤310，填充核心黏胶207于晶圆200的复数晶粒间的空隙及成型于基板205上的晶粒黏着膜206间的空隙内。其后，于步骤312，蚀刻基板205的背侧以去除部分区域的基板205。于步骤314，形成覆盖保护层209于基板205的背侧上。步骤312及314可加以修改于步骤322之后及步骤324之前。
之后，于步骤316，制作第一介电层210的图样于晶圆200上，且晶圆200的部分表面暴露出。于步骤318，溅镀连通导电层211以填充于复数第一介电层210间的空隙内。接着，于步骤320，涂布重分布层导线212于连通导电层211及第一介电层210上以暴露复数第一介电层210的部分表面。于步骤322，涂布复数第二介电层213以填充于连通导电层211间的空隙，且暴露连通导电层211的部分表面。于步骤324，将复数导电凸块214焊接于复数第二介电层213间的空隙上。
此领域的技术者应注意，此处所提及的材料及材料的厚度只用以说明并非用以限制本发明。故此处提及的材料及其厚度可根据不同传导需求而加以修改。
根据本发明以上的叙述，本发明可缩小封装尺寸及减少制造时间。此外，本发明可将芯片尺寸封装结构的尺寸最小化，并有效改善制造工艺。因此，本发明所揭露的超薄芯片尺寸封装结构及其方法可提供先前技术所无法预期的效果并解决先前技术的问题。本发明的方法可应用于晶圆或面板业，且亦可应用及修改成其它相关的应用。
虽本发明的较佳实施例已叙述如上，然而，此领域的技术者将得以了解，上述本发明的较佳实施例只用以说明本发明，而非用以限制本发明，本发明不应受限于所述的较佳实施例。更确切言之，此领域的技术者可于权利要求书所定义的本发明的精神及范围内做若干改变或修改。

Claims (10)

1.一种超薄芯片尺寸封装结构，其特征在于，所述的超薄芯片尺寸封装结构包含：
一基板；
复数晶粒，其具有复数接合垫形成于其上；
一第一介电层，其形成于所述的复数晶粒上以暴露所述的接合垫的部分表面；
一连通导电层，其填充所述的第一介电层间的空隙内；
一重分布层导线，其形成于所述的连通导电层及所述的第一介电层上；
一第二介电层，其形成于所述的第一介电层及所述的重分布层导线上以暴露所述的重分布层导线的部分表面；
复数导电凸块，其形成于所述的第二介电层间的空隙上；以及
一覆盖保护层，其形成于所述的基板之下；
其中所述的复数导电凸块透过所述的连通导电层及所述的复数重分布层导线而电性连接至所述的接合垫。
2.根据权利要求1所述的超薄芯片尺寸封装结构，其特征在于，所述的超薄芯片尺寸封装结构还包含一晶粒黏着膜，其成型于所述的基板及所述的复数晶粒之间。
3.根据权利要求1所述的超薄芯片尺寸封装结构，其特征在于，所述的超薄芯片尺寸封装结构还包含核心黏胶，其填充于所述的复数晶粒间的空隙内。
4.根据权利要求3所述的超薄芯片尺寸封装结构，其特征在于，其中所述的核心黏胶的材料包含硅胶、含硅树脂或环氧树脂。
5.根据权利要求1所述的超薄芯片尺寸封装结构，其特征在于，其中所述的基板的材料包含金属、合金、有机物、玻璃、陶瓷或硅，其中所述的合金包含镍铁合金(Alloy42；42％Ni-58％Fe)、柯弗合金(Kover；29％Ni-17％Co-54％Fe)。
6.根据权利要求1所述的超薄芯片尺寸封装结构，其特征在于，其中所述的第一介电层及所述的第二介电层的材料包含苯环丁烯、硅氧烷聚合物或聚亚酰胺。
7.根据权利要求1所述的超薄芯片尺寸封装结构，其特征在于，其中所述的覆盖保护层的材料包含环氧树脂及橡胶。
8.一种用于制造超薄芯片尺寸封装的方法，其特征在于，所述的方法包含：
预备附有复数晶粒的晶圆，所述的复数晶粒具有复数接合垫形成于其上；
切割附着于切割胶带上的所述的晶圆以形成复数狭长孔直到达第一预定深度；
将所述的晶圆附着于研磨胶带架的下方且背面研磨所述的晶圆直到达第二预定深度；
将经切割的所述的晶圆结合至具有晶粒黏着膜的基板；
移除所述的研磨胶带架；
填充核心黏胶于所述的复数晶粒及所述的晶粒黏着膜间的空隙内；
蚀刻所述的基板的背侧以去除部分区域的所述的基板；
形成覆盖保护层于所述的基板的背侧上；
形成复数第一介电层于所述的晶圆上且暴露所述的复数晶粒的部分表面；
溅镀连通导电层以填充于所述的复数第一介电层间的空隙内；
形成重分布层导线于所述的连通导电层及所述的复数第一介电层上以暴露所述的复数第一介电层的部分表面；
涂布复数第二介电层以填充于所述的连通导电层间的空隙且暴露所述的连通导电层的部分表面；以及
将复数导电凸块焊接于所述的复数第二介电层间的空隙上。
9.根据权利要求8所述的用于制造超薄芯片尺寸封装的方法，其特征在于，所述的方法还包含：
于印刷焊锡糊剂或植入导电凸块于凸块底层金属上之前形成凸块底层金属结构；以及
将所述的超薄芯片尺寸封装置放于所述的切割胶带上以分离成独立芯片。
10.根据权利要求8所述的用于制造超薄芯片尺寸封装的方法，其特征在于，其中蚀刻所述的基板的背侧的步骤是通过湿式蚀刻法。
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