CN1516251A - 半导体组件的制造方法及半导体组件 - Google Patents

半导体组件的制造方法及半导体组件 Download PDF

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Publication number
CN1516251A
CN1516251A CNA031378625A CN03137862A CN1516251A CN 1516251 A CN1516251 A CN 1516251A CN A031378625 A CNA031378625 A CN A031378625A CN 03137862 A CN03137862 A CN 03137862A CN 1516251 A CN1516251 A CN 1516251A
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China
Prior art keywords
mentioned
semiconductor element
distribution
semiconductor
element mounting
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CNA031378625A
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English (en)
Inventor
ֱ
福富直树
坪松良明
井上文男
山崎聪夫
大畑洋人
萩原伸介
֮
田口矩之
野村宏
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Showa Denko Materials Co Ltd
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Hitachi Chemical Co Ltd
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Publication of CN1516251A publication Critical patent/CN1516251A/zh
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern

Abstract

本发明涉及半导体组件的制造方法及半导体组件，该半导体元件装载用基板具有绝缘性支撑体和在该支撑体的单面上形成的多条配线，其特征在于，具有：在上述绝缘性支撑体的表面上形成多组半导体元件装载区域和该半导体装载区域的外侧的树脂密封用半导体封装区域的工序；在上述半导体封装区域中形成金属线焊接端子、且在上述半导体元件装载区域中形成外部连接端子、且形成将该金属线焊接端子和该外部连接端子串接在一起的上述配线的配线形成工序，以及在形成上述外部连接端端子的地方的上述绝缘性支撑体上形成到达上述外部连接端子的开口部的开口部形成工序。

Description

半导体组件的制造方法及半导体组件
技术领域
本发明涉及一种半导体组件的制造方法及半导体组件。本申请是中国专利申请95192144.4的分案申请。
背景技术
随着半导体集成化的提高，输入输出端子数目正在增加。从而需要具有许多输入输出端子的半导体组件。通常，输入输出端子有两种形式：一种是组件周围一列配置，另一种是不仅在周围而且布至组件内部的多列配置。QFP(Qund Flat Package)是前者的代表，当要使其实现多端子化时，必须缩小端子间距。然而当间距小于0.5mm时，在与配线板的连接方面需要很复杂的技术。作为后者的阵列式有可能以比较大的间距配置端子，故适合于多针化。
以往，作为阵列式配置，通常是拥有连接针的PGA(Pin Grid Array)，但其与配线板的连接为插入型，不适合于表面安装。于是，人们正在开发一种可表面安装的、被称为BGA(Ball Grid Array)的半导体组件。作为BGA的类型有：(1)陶瓷型、(2)印刷电路板型及(3)使用TAB(tape automated bonding)的条型。这当中，若与过去的PGA相比，陶瓷型的母板与组件的距离变短，从而出现因母板与组件间的热应力差而造成的组件翅曲这一严重问题。另外，在印刷电路板型中也存在基片翅曲、耐湿性、可靠性以及基片过厚等问题。故而人们正提出可应用TAB技术的条型BGA。
作为与组件尺寸更加小型化相适应的一种技术，人们提出了一种与半导体芯片几乎同等大小的、所谓的芯片尺度组件(CSP：Chip Sizepackage)。这是一种不是在半导体芯片周围、而是在其安装区域内拥有可连接外部配线基片的连接部件的半导体组件。
作为具体的例子有以下两种：将凸出的聚酰亚胺膜与半导体芯片表面粘接，通过金属引线和芯片相接，然后浇注环氧树脂等进行密封(NIKKEIMATERIALS & TECHNOLOGY 94.4，NO.140，P18-19)；在临时基片上、相当于与半导体芯片及外部配线基片连接部位置，设置金属凸块，将半导体芯片倒焊后，用该临时基片自动传送模制而成(Smallest Flip-Chip-LivePackage CSP；The Second VLSI Package Workshop of Japan，P46-50，1994)。
另外，如前所述，在BGA和CSP领域，人们正在研究开发一种利用聚酰亚胺带作为基片的组件。这种情况下，作为聚酰亚胺带，通常是通过粘接料层使铜箔与聚酰亚胺带作成层压板，但从耐热和耐湿性的角度出发，人们更希望在铜箔上直接形成聚酰亚胺层，即所谓的双层片状基材。双层片状基材的制造方法大致可分为以下两种：①在铜箔上涂敷聚酰亚胺的前体聚酰胺酸后使其垫固；②利用真空成膜法和无电镀法，在固化了的聚酰亚胺膜上形成金属薄膜。若采用激光加工技术除去所需部分(相当于第2连接功能部)的聚酰亚胺除去，而形成抵达铜箔的凹部时，最好使聚酰亚胺膜尽量地薄。反之，若将双层片状基材加工处理成引线框架状时，如膜厚度过薄，则会出现缺乏操作性及框架的刚性。
如上所述，作为能适应小型化、高集成化发展的半导体组件，正提出种种方案，但人们期待着更进一步的改进，以满足性能、特性及生产等全方位的要求。
本发明提供一种半导体组件的制造方法及半导体组件，它可生产性能良好、安全稳定地制造能适应小型化、高集成化发展的半导体组件。
发明内容
本发明提供了一种半导体元件装载用基板的制造方法，该半导体元件装载用基板具有绝缘性支撑体和在该支撑体的单面上形成的多条配线，其特征在于，具有：
在上述绝缘性支撑体的表面上形成多组半导体元件装载区域和该半导体装载区域的外侧的树脂密封用半导体封装区域的工序；
在上述半导体封装区域中形成金属线焊接端子、且在上述半导体元件装载区域中形成外部连接端子、且形成将该金属线焊接端子和该外部连接端子串接在一起的上述配线的配线形成工序，以及
在形成上述外部连接端端子的地方的上述绝缘性支撑体上形成到达上述外部连接端子的开口部的开口部形成工序。
本发明还提供了一种半导体元件装载用基板，该半导体元件装载用基板具有绝缘性支撑体和在该支撑体的单面上形成的多条配线，其特征在于，具有：
多组半导体元件装载区域和该半导体装载区域的外侧的树脂密封用半导体封装区域；
上述配线含有将在上述半导体封装区域中形成的金属线焊接端子和在上述半导体元件装载区域中形成的外部连接端子串接在一起的配线，以及
本发明还提供了一种半导体元件装载用基板的制造方法，该半导体元件装载用基板具有绝缘性支撑体和多条配线，其特征在于，具有：
在上述绝缘性支撑体的表面上形成多组半导体元件装载区域和该半导体装载区域的外侧的树脂密封用半导体封装区域的工序；以及
具有形成含有金属线焊接端子、外部连接端子的确定的配线图形的配线形成工序，
上述金属线焊接端子设置在上述树脂密封用半导体封装区域中；
上述外部连接端子设置在上述半导体装载区域中。
本发明还提供了一种半导体元件装载用基板，该半导体元件装载用基板具有绝缘性支撑体和多条配线，其特征在于：
具有多组半导体元件装载区域和该半导体装载区域的外侧的树脂密封用半导体封装区域；
上述配线具有含有金属线焊接端子和外部连接端子的确定的配线图形，以及
上述金属线焊接端子设置在上述树脂密封用半导体封装区域中；
上述外部连接端子设置在上述半导体装载区域中，
对具有同一上述配线图形的半导体元件装载区域及上述半导体封装区域进行多个排列。
本发明还提供了一种半导体元件安装用基板，其特征在于：
具有：该半导体元件安装用基板具有用于装载各个半导体元件的多个半导体安装基板部件、用于在上述半导体元件安装基板部之间连结的连结部和对准位置的标记部，
该半导体元件安装用基板部件具有：
上述半导体元件装载区域，
上述半导体元件装载区域的外侧的树脂密封用半导体封装区域，以及
含有上述设置在上述树脂密封用半导体封装区域中的金属线焊接端子和设置在上述半导体元件装载区域的外部连接端子的配线，
上述连结部具有导电层。
本发明还提供了一种半导体元件安装用基板的制造方法，具有：用于安装半导体元件的具有各个配线的多个半导体元件安装基板部，将上述多个半导体元件基板部进行连接、有导电层的连结部，对准位置的标记部，上述半导体元件安装基板部具有上述半导体元件装载区域和上述半导体元件装载区域的外侧的树脂密封用半导体封装区域，其特征在于：
具有将含有设置在上述树脂密封用半导体封装区域中的金属线焊接端子和设置在上述半导体元件装载区域的外部连接端子的配线、上述连结部的上述导电层和树脂材料一起形成的配线形成工序。
附图说明
以下将对附图作简要说明：
图1为说明本发明中半导体组件制造方法的一实施例的剖面图。
图2为说明本发明中半导体组件制造方法的一实施例的剖面图。
图3为说明本发明中半导体组件制造方法的一实施例的剖面图。
图4为说明本发明中半导体组件制造方法的一实施例的剖面图。
图5为说明本发明中半导体组件制造方法的一实施例的剖面图。
图6为说明本发明中半导体组件制造方法的一实施例的剖面图。
图7为说明本发明中半导体组件制造方法的一实施例的剖面图。
图8为说明本发明中半导体组件制造方法的一实施例的剖面图。
图9为说明本发明中半导体组件制造方法的一实施例的剖面图。
图10为说明本发明中半导体组件制造方法的一实施例的剖面图。
图11为说明本发明中半导体组件制造方法的一实施例的剖面图。
图12为说明本发明中半导体组件制造方法的一实施例的剖面图。
图13为说明本发明中半导体组件制造方法的一实施例的剖面图。
图14为说明本发明中半导体组件制造方法的一实施例的剖面图。
图15为说明本发明中半导体组件制造方法的一实施例的剖面图。
图16为说明本发明中半导体组件制造方法的一实施例的剖面图。
图17为说明本发明中半导体组件制造方法的一实施例的剖面图。
图18为说明本发明中半导体组件制造方法的一实施例的剖面图。
图19为说明本发明中半导体组件制造方法的一实施例的剖面图。
图20为说明本发明中半导体组件制造方法的一实施例的剖面图。
图21为说明本发明中半导体组件制造方法的一实施例的剖面图。
图22为说明本发明中半导体组件制造方法的一实施例的剖面图。
图23为说明本发明中半导体组件制造方法的一实施例的剖面图。
图24为说明本发明中半导体组件制造方法的一实施例的剖面图。
图25为说明本发明中半导体组件制造方法的一实施例的剖面图。
具体实施方式
结合图1，对本发明的第1实施例进行说明。
在厚度为0.035mm的电解铜箔1的单面上电镀厚度为0.001mm的  镍层(图1中省略)。然后，对感光性干膜保护层(日立化成工业株式会社制造、商品名：″PHOTEC HN340″)进行层压，配线图形经曝光、显影，形成电镀保护层。接着，在硫酸铜液中进行电解镀铜。下一步进行厚度为0.003mm的镀镍、纯度在99.9％以上、厚度在0.0003mm以上的镀金。然后，剥离电镀保护层，形成配线2(图1a)。这样将LSI芯片3装配在已设有配线2的铜箔1上(图1b)。在粘接LSI芯片时，使用半导体专用的银焊料4。而后将LSI端子与配线2通过导线100相连接(图1c)。如此形成之后，将该件放入自动传送模中，采用专用于半导体密封的环氧树脂(日立化成工业株式会社制造、商品名：“CL-7700”)进行密封5(图1d)。此后，利用碱腐蚀方法只将铜箔1溶解除去，露出镍层。在对铜溶解性低的镍剥离液中除去镍层，露出配线部(图1e)。接着，涂敷焊料保护层6，并以能使连接用端子部呈露出状态地设置图形。在该配线露出处，设置焊料球7，并使之溶融(图1f)。通过该焊料球7与外部的配线相连接。
结合图2，对本发明的第2实施例进行说明。
用与图1同样的方法，制成拥有配线2的铜箔1(图2a)。装配LSI芯片3，在LSI芯片端子部设置金属凸块8，将所述金属凸块8与配线2的端子部经加热加压相连接(图2b)。然后在LSI芯片下部充填液态环氧树脂并使之固化9(图2c)。如此形成之后，将该件放入自动传送模中，采用半导体专用密封环氧树脂(日立化成工业株式会社制造、商品名：“CL-7700”)进行密封10(图2d)。此后，利用碱腐蚀方法只将铜箔1溶解除去，露出镍层。在对铜溶解性低的镍剥离液中除去镍层，露出配线部(图2e)。然后，涂敷焊料保护层6，并以能使连接用端子部呈露出状态地设置图形。在该配线露出处，设置焊料球7，并使之溶融(图2f)。通过该焊料球7与外部的配线相连接。
结合图3，对本发明第3实施例进行说明。
在厚度为0.035mm的电解铜箔1的单面电镀厚度为0.001mm的镍层(图3中省略)。然后对感光性干膜保护层(日立化成工业株式会社制造、商品名：“PHOTEC HN340″)进行层压，配线图形经曝光、显影，形成电镀保护层。接着，在硫酸铜液体中进行电解镀铜，设置第1配线13。而后使电镀保护层剥离，在第1配线13的表面进行氧化和还原处理。作为粘接树脂，使用聚酰亚胺类粘接膜(日立化成工业株式会社制造、商品名：“AS2210”)12，让配线13处于内侧，与新的铜箔层叠粘接。(用通常的光刻法在铜箔11上设置形成直径为0.1mm的孔穴。利用板镀法在孔穴内和铜箔整个表面进行镀铜)。利用铜箔及光刻法设置第2配线11。用准分子激光除去LSI装配部位的树脂(聚酰亚胺类粘接膜12)，使端子部露出。在该端子部，进行厚度为0.003mm的镀镍、纯度99.9％以上、厚度为0.0003mm以上的镀金(图3a)。这样，在设有双层配线的铜箔1上装配LSI芯片。粘接LSI芯片时，使用半导体专用的银焊料(图3b)。然后，用导线100将LSI端子部与配线13连接(图3c)。如此形成之后，将该件放入自动传送模中，用半导体专用密封环氧化树脂(日立化成工业株式会社制造、商品名“CL-7700”)进行密封5。此后，利用碱腐蚀方法只将铜箔1溶解除去，露出镍层。在对铜溶解性低的镍剥离液中除去镍层，露出配线(图3e)。然后，涂敷焊料保护层，以使连接用端子部呈露出状态地设置图形。在该配线的露出处，设置焊料球7、使之溶融(图3f)。通过该焊料球7与外部的配线相连接。
结合图4，对本发明的第4实施例进行说明。
在厚度为0.1mm的SUS(不锈钢)板14上，对感光性干膜保护层(日立化成工业株式会社制造、商品名“PHOTEC HN 340”)进行层压，配线图形经曝光、显影，形成电镀保护层。此后，在硫酸铜液中进行电解镀铜。下一步，进行厚度为0.003mm镀镍、纯度在99.9％以上、厚度为0.0003mm以上的镀金。然后，剥离电镀保护层，形成配线2(图4a)。这样，在设有配线2的SUS板14上装配半导体芯片103(图4b)。粘接半导体芯片时，采用半导体专用银焊料4。然后，通过导线100将半导体端子部与配线2连接(图4c)。如此形成之后，将该件放入自动传送模中，用半导体专用密封环氧树脂(日立化成工业株式会社制造、商品名：“CL-7700”)进行密封5(图4d)。此后，将SUS板14机械剥离除去，露出配线部(图4e)。然后，涂敷焊料保护层，以使连接用端子部呈露出状地设置图形。在该配线的露出处，设置焊料球7，并使之溶融(图4f)。通过该焊料球7与外部配线相连接。
结合图5，对本发明第5实施例进行说明。
在厚度为0.035mm的电解铜箔1上，对感光性干膜保护层(日立化成工业株式会社制造、商品名：″PHOTEC HN340″)进行层压，配线图形经曝光、显影，形成电镀保护层。接着，在进行镍的图纹电镀15之后，在硫酸铜液中进行电解镀铜。下一步，进行厚度为0.003mm的镍层、纯度99.9％以上、厚度在0.0003mm以上的镀金。然后剥离电镀保护层，形成配线2(图5a)。在如此设有配线2的铜箔1上装配半导体芯片103(图5b)。粘接半导体芯片时，利用半导体专用银焊料4。然后，通过导线100将半导体端子和配线2连接(图5c)。如此形成之后，将该件放入自动传送模中，采用半导体专用密封环氧树脂(日立化成工业株式会社制造、商品名：“CL-7700”)进行密封5(图5d)。此后，利用碱腐蚀方法将铜箔1除去，露出镍层的配线部(图5e)。然后，涂敷焊料保护层6，以使连接用端子部呈露出状地设置图形。在该配线露出处，设置并溶融焊球7(图5f)。通过该焊球7与外部配线相连接。
结合图6，对本发明第6实施例进行说明。
在厚度为0.035mm的电解铜箔1上，对感光性干膜保护层(日立化成工业株式会社制造、商品名：″PHOTEC HN340″)进行层压，配线图形经曝光、显影，形成电镀保护层。接着，进行纯度99.9％以上、厚度在0.0003mm以上的镀金，以及厚度大于0.003mm的镀镍。进而在硫酸铜液中进行电解镀铜，剥离电镀保护层，形成配线2(图6a)。这样，在已设置有配线2的铜箔1的配线面上粘接聚酰亚胺膜片16，利用激光使配线2的连接用端子部露出(图6b)，并利用腐蚀方法将铜箔1除去(图6c)。另外，不使用聚酰亚胺而用感光性薄膜16，不使用激光也可使连接用端子部露出。接着，在聚酰亚胺膜16的配线图形面上装配LSI芯片3。粘接LSI芯片时，利用半导体专用银焊料4。然后，通过导线100将半导体端子与配线2相连接(图6d)。如此形成之后，将该件放入自动传送模中，用半导体密封专用环氧树脂(日立化成工业株式会社制造、商品名：“CL-7700”)进行密封5(图6e)。此后，在连接用端子部设置并溶融焊料球7(图6f)。通过该焊料球7与外部配线相连接。
结合图7，对本发明第7实施例进行说明。
在厚度为0.035mm的电解铜箔1的平面上，电镀厚度为0.001mm的镍层(图7中省略)。然后对感光性干膜保护层(日立化成工业株式会社制造、商品名：“PHOTEC HN340”)进行层压，配线图形经曝光显影，形成电镀保护层。接着，在硫酸铜液中进行电解镀铜。进而进行厚度为0.003mm的镀镍，以及厚度大于0.0003mm、纯度在99.9％以上的镀金。此后，剥离电镀保护层，形成配线2(图7a)。这样，在设有配线2的铜箔上装配LSI芯片3。粘接LSI芯片时，采用半导体专用银焊料4。然后，通过导线100将半导体端子与配线2连接(图7b)。如此形成之后，将该件放入自动传送膜中，采用半导体密封专用环氧树脂(日立化成工业株式会社制造、商品名：“CL-7700”)进行密封5(图7c)。此后，用碱腐蚀方法只将铜箔1溶解除去，使镍层露出。在对铜溶解性低的镍剥离液中除去镍层，露出配线(图7d)。然后，粘接使连接用端子开口的聚酰亚胺薄膜16(图7e)，并在该配线露出处设置并溶融焊料球7(图7f)。通过该焊料球7与外部配线连接。
结合图8，对本发明第8实施例进行说明。
在厚度为0.035mm的电解铜箔1上，对感光性干膜保护层(日立化成工业株式会社制造、商品名：“PHOTEC HN340”)进行层压，配线图形经曝光、显影，形成电镀保护层。接着，进行纯度在99.9％以上、厚度为0.0003mm的镀金，以及厚度在0.003mm以上的镀镍。在硫酸铜液中电解镀铜，并剥离电镀保护层，形成配线2(图8a)。在如此设置有配线2的铜箔1的配线一面，采用丝网印刷方法涂敷液态密封树脂17，并使配线2的接线用端子部呈露出状地设置绝缘层(图8b)。待液态密封树脂固化后，利用腐蚀方法将铜箔1除去(图8c)。然后，在已固化的液态密封树脂16具有配线图形的一面装配LSI芯片3。粘接LSI芯片时，使用半导体专用银焊料4。此后，用导线100将半导体端子与配线2相连接(8d)。如此形成之后，将该件放入自动传送模中，采用半导体专用密封环氧树脂(日立化成工业株式会社制造、商品名：“CL-7700”)进行密封5(图8e)。此后，在配线2的连接端子处设置并溶融焊料球7(图8f)。通过该焊料球7与外部配线相连接。
结合图9，对本发明第9实施例进行说明。
在厚度为0.035mm的电解铜箔1的单面电镀厚度0.001mm的镍层(图9中省略)。此后，对感光性干膜保护层(日立化成工业株式会社制造、商品名：“PHOTEC HN340”)，进行层压，配线图形经曝光、显影，形成电镀保护层。接着，在硫酸铜液中电解镀铜。然后，进行厚度为0.003mm的镍电镀，以及纯度在99.9％以上、厚度在0.0003mm以上的镀金。此后，剥离电镀保护层，形成配线2(图9a)。这样，在设有配线2的铜箔1上装配LSI芯片3。粘接LSI芯片时，利用半导体专用的银焊料4。然后，通过导线100将半导体端子与配线2连接(图9b)。如此形成之后，将该件放入自动传送模中，用半导体密封专用环氧树脂(日立化成工业株式会社制造、商品名：“CL-7700”)进行密封5(图9c)。此后，利用碱腐蚀方法仅将铜箔1溶解除去，使镍层露出。在对铜溶解性低的镍剥离液中除去镍层，露出配线(图9d)。然后，采用丝网印刷方法涂敷液态密封树脂17，使配线2的连接用端子部呈露出状态而形成液态密封树脂17的绝缘层(图9e)。在使用液态密封树脂17固化后，在该配线2连接用端子部，设置并溶融焊料球7(图9f)。通过该焊料球7与外部配线相连接。
结合图10，对本发明第10实施例进行说明。
在厚度为0.035mm的电解铜箔1的单面，电镀厚度为0.001mm的镍层(图10中省略)。对感光性干膜保护层(日立化成工业株式会社制造、商品名：“PHOTEC HN340”)进行层压，经曝光、显影，形成配线图形及位置对合标识的电镀保护层。在硫酸铜液中进行电解镀铜。然后，继续进行厚度为0.003mm的镀镍，以及纯度在99.9％以上、厚度在0.0003mm以上的镀金。接着，剥离电镀保护层，形成配线2及位置对合标识18后(图10a)，仅在位置对合标识18处，用SUS板进行夹压，使铜箔1的背面形成突出的位置对合标识(图10b)。在如此已设置有配线2和位置对合标识18的铜箔1上，装配LSI芯片3(图10c)。粘接LSI芯片3时，采用半导体专用银焊料4。此后，通过导线100将半导体端子部与配线2连接(图10d)。如此形成之后，将该件放入自动传送模中，用半导体密封专用环氧树脂(日立化成工业株式会社制造、商品名：CL-7700)进行密封5(图10e)。
在铜箔背面再次对感光性干膜保护层进行压层，利用位置对合标识18形成腐蚀图形。此后，将铜箔1及镍层进行腐蚀处理，由铜箔1形成凸块7，并实现配线部的露出(图10f)。接着，涂敷焊料保护层8，并使凸块7呈露出状形成绝缘层(图10g)。通过该凸块7与外部配线连接。
结合图11，对本发明第11实施例进行说明。
在厚度为0.035mm的电解铜箔1上，对感光性干膜保护层(日立化成工业株式会社制造，商品名：“PHOTEC HN340”)进行层压，使多组配线图形经显影，形成电镀保护层。接着，进行纯度在99.9％以上、厚度0.0003mm的镀金，以及厚度在0.003mm以上的镀镍层。然后，在硫酸铜液中电解镀铜，剥离保护层，形成多组配线2(图11a)。这样，在已设有多组配线2的铜箔1的配线面上粘接聚酰亚胺膜19，并利用激光加工使配线2的连接端子部露出(图11b)，用腐蚀方法除去铜箔1(图11c)。这样，在一片聚酰亚胺膜片上形成多组配线2后，装配LSI芯片3。在粘接LSI芯片时，利用半导体专用芯片连接条4′。此后，通过导线100将半导体端子与配线2连接(图11d)。如此形成之后，将该件放入自动传送模中，用半导体密封用环氧树脂(日立化成工业株式会社制造、商品名：“CL-7700”)分别进行密封5(图11e)。然后，在配线2的连接端子部，设置、溶融焊料球7(图11f)。通过该焊料球7与外部配线相连接。最后，将用聚酰亚胺薄膜相连的组件冲压取出(图11g)。
结合图12，对本发明第12实施例进行说明。
在厚度为0.07mm、带有粘接剂的聚酰亚胺薄膜20上，用冲压的方法使其预成为连接端子的部分形成开口(图12a)。然后，在粘接厚度0.035mm的铜箔21后(图12b)，对感光性干膜保护层(日立化成株式会社制造、商品名：″PHDTEC HN340″)进行层压，多组配线图形经曝光、显影，形成腐蚀保护层。接着，将铜箔腐蚀，剥离保护层，形成多组配线2(图12c)。这样，在1片聚酰亚胺膜片上形成多组配线图形后，装配LSI芯片3。粘接LSI芯片3时，利用半导体专用芯片连接条4′。此后，通过导线100将半导体端子与配线2连接(图12d)。如此形成之后，将该件放入自动传送模中，用半导体专用密封环氧树脂(日立化成工业株式会社制造、商品名：“CL-7700”)分别进行密封5(图12e)。此后，在配线的连接端子部，设置并溶融焊料球7(图12f)。通过该焊料球7与外部配线相连接。最后，将用聚酰亚胺薄膜相连的组件冲压取出(图12g)。
结合图13、图14和图15，对本发明第13实施例进行说明。
在厚度为0.035mm的电解铜箔1的一面电镀厚度为0.001mm的镍层(图13中省略)。对感光性干膜保护层(日立化成工业株式会社制造、商品名：“PHOTEC HN340”)进行层压，经曝光、显影，形成多组配线图形的电镀保护层。然后在硫酸铜溶液中电解镀铜，接着进行厚度0.003mm的镀镍，纯度在99.9％以上、厚度在0.0003mm以上的镀金，剥离电镀保护层，形成配线2(图13a)。再接着，将形成有配线2的铜箔1分为单元个数后，利用聚酰亚胺粘接膜将其粘贴在另外准备好的、不锈钢制成的框架22(厚度0.135mm)上(图13b)。框架可以用磷青铜等铜合金、铜箔、镍箔及镍合金箔制成。而粘接方法还可以利用金属间共晶的方法，以及利用超音波的粘接方法等。另外，如图14所示，事先检查铜箔1上的配线，只要选择品质良好的配线23与框架22相粘接即可。在图14中，1为电解铜箔，22为框架，24为品质不良的配线，25是位置对合用孔穴。另外，在本实施例中，在分离后的铜箔上具有一个配线，但也可使分离后的铜箔上具有多组配线。作为将框架22与带有配线的铜箔进行粘合的位置关系，有如图15(a)和(b)所示的种种可能。图15为框架22的平面图，26是框架的开口部、27是带有配线的铜箔的安装位置、28是用来固定箔的粘接剂。然后，安装LSI芯片3，并通过导线100将半导体端子部与配线2相连接(图13c)。安装LSI芯片时，利用半导体专用芯片连接条4′。这里，也可以不用连接条4′，使用芯片连接用银焊料。另外，在安装半导体芯片时，选用了普通的导线连接，但也可以采用倒装片等其他方法。如此形成之后，将该件放入自动传送模中，采用半导体密封专用环氧树脂(日立化成工业株式会社、制造商品名“CL-7700”)进行密封5(图13d)。然后，利用碱腐蚀方法只将铜箔1溶解除去，使镍层露出。再在对铜溶解性低的镍剥离液中除去镍层，露出配线部分。此后，涂敷焊料保护层6，以使连接端子呈露出状设置图形。在该配线露出部，设置、溶融焊料球7(图13e)。此后，利用剪断机切断，并除掉框架22不要的切片101，分割成各个半导体组件(图13f)。通过所述焊料球7与外部配线相连接。本实施例是以板的形式操作，可高效率地制造半导体组件。
结合图16，对本发明第14实施例进行说明。
在厚度为0.07mm的、带有粘接剂的聚酰亚胺薄膜29上，用冲压的方法使其预成为连接端子的部分形成开口。然后，与厚度0.035mm的铜箔相粘接，对感光性干膜保护层(日立化成工业株式会社制造、商品名：“PHOTEC HN340”)进行层压，多组配线图形经曝光、显影，形成腐蚀保护层。接着，腐蚀铜箔，剥离保护层，形成多组配线2(图16a)。这里也可采用将聚酰亚胺直接涂到铜箔上的材料(日立化成工业株式会社制造、商品名：50001)，形成连接端子部及配线2。开口部的形成也可用钻孔加工、准分子激光等激光加工和印刷等方法，以及使用对聚酰亚胺具有感光性能的材料来通过曝光、显影而形成。不使用聚酰亚胺，也可以使用密封树脂的材料。
如上所述，在一片聚酰亚胺薄膜上形成多组配线图形后，将带有配线的薄膜分成数个单元，并通过粘合聚酰亚胺用粘接剂28，粘接在另已准备好的不锈钢制的框架22(厚0.135mm)上(图16b)。然后，装配LSI芯片3，通过导线100将半导体端子部与配线2连接(图16c)。在安装LSI芯片时，利用了芯片连接条4′。如此形成之后，将该件放入自动传送模中，采用半导体密封专用的环氧树脂(日立化成工业株式会社制造、商品名：“CL-7700”)进行密封5(图16d)。接着，在最初设置的、预成为连接端子的开口部配置、溶融焊料球7(图16e)。通过该焊料球7与外部配线相连接。最后，将以薄膜连的组件冲压取出，分割成各个组件(图16f)。
结合图17，对本发明第13实施例进行说明。
在金属箔31上直接设置绝缘材料32，在这种双层柔性基材(图17a)的金属箔上设置一定的保护层图案，用众所周知的腐蚀法形成所需的多组配线图形33，剥离保护层(图17b)。作为金属箔，除电解铜箔、压伸铜箔或铜合金箔等单一箔外，在经后续工艺可除去的载体箔上设有铜薄层的复合金属箔等也是适用的。具体地讲，在厚度18μm的电解铜箔的单面，形成厚度0.2μm左右的镍磷镀层后，继续电镀厚度为5μm左右的铜薄层，这种复合金属箔也是可应用的。这种情况下，当在铜薄层上形成聚酰亚胺层后，通过腐蚀除去铜箔及镍磷层，而露出铜薄层。即，在本申请的发明中，既可以在使铜薄层全部露出后再对铜薄层进行配线加工，也可以将载体箔(铜箔/镍薄层)作为引导框架结构体的一部分加以利用。
另外，作为绝缘基材，从工艺耐热性等观点来看，聚酰亚胺材料是很一般的。这种场合下，若聚酰亚胺和铜箔的热膨胀系数不相同，在焊料的软溶过程中，基材的翅曲就会显著。因此，作为聚酰亚胺，最好是使用含有70摩尔％以上的聚酰亚胺，该聚酰亚胺具有下列[化学式1]的循环单元。
[化学式1]
然后，后续处理中，在成为与外部基板连接部的位置上，设置达到铜箔的凹部34(图17c)。凹部的加工方法无特殊限定，除准分子激光、二氧化碳激光以及YAG激光等激光加工外，也可应用液体腐蚀方法。
然后，将框架基材37与配线图形面相粘接，所述基材37是对所设定部分(开孔部35)用冲孔加工等方法而成，并带有粘接材料36(图17d)。在这种情况下，对框架基材无特殊限定，象聚酰亚胺膜及铜箔等金属箔均可适用。这里假设双层柔性基材聚酰亚胺层厚度25μm，且粘接框架基材为聚酰亚胺膜，那么，为了确保框架整体的刚度，薄膜厚度必须在50-70μm左右。而且，对形成薄膜基材层的区域也无特殊限定，也可在装配半导体芯片的那部分设置框架基材层。具体地讲，在以导线连接方式装配芯片的情况下，只要最小限度地露出导线连接用端子部38，其他区域也可全部设置框架基材层。之后，装配半导体芯片39，用金线40将半导体芯片与配线图形间连通(图17e)。另外，作为半导体芯片的安装方式，在采用倒焊方式的情况下，也可在配线图形的一定位置(与半导体芯片外部连接所用电极的位置相对应)设置金属凸块，通过该金属凸块，使半导体芯片与波线图形相连通。然后，将该件放入自动传送模中，用树脂密封材料41进行密封(图17f)。这时树脂密封材料无特殊限定，比如可以采用含有直径在10-20μm的二氧化硅、含水量在5-80％范围的环氧类树脂等。然后形成与外部基板的连接部42。作为连接部42的形成方法，既可采取在图17c的工序后预先通过电解电镀法形成较聚酰亚胺膜要厚一些的凸块的方法，也可采取在树脂密封后由焊锡印刷法形成焊料凸块的方法。最后，由框架切断组件，得到所需的组件(图17g)。
以下对图17的第15实施例进行更具体的说明。
具体例1
在单面拥有厚度12μm电解铜箔的双层柔性基材(日立化成工业株式会社制造、商品名：“MCF5000I”)的铜箔面上，对干膜保护层(日立化成工业株式会社)制造、商品名：“PHOTEC HK815”)进行层压，经曝光、显影，得到所需的抗腐蚀图形。然后，用氯化铁溶液对铜箔腐蚀后，用氢氧化钾溶液剥离抗腐蚀图形，从而得到所需的配线图形。接着，采用准分子激光加工机(住友重型机械工业株式会社制造、“INDEX200”)在一定的位置，仅以一定的数量形成从绝缘基材一侧到达配线图形背面的凹部(直径300μm)。准分子激光加工条件为：能量密度250mJ/cm2，缩小率3.0，振荡频率200Hz，照射脉冲数为300。然后，制造粘接片，所述粘接片为：在厚度50μm的聚酰亚胺薄膜(宇部兴产制造、商品名：“UPILEXS”)的单面具有厚度10μm的聚酰亚胺类的粘接材料(日立化成工业株式会社制造、商品名：“AS2250”)。用冲孔加工方法除去所设定区域，该设定区域包括后续工序中设置导线连接端子的区域。这样，通过粘接材料，使聚酰亚胺薄膜与带有配线图形的双层柔性基材经加热而压接。压接条件为：压力20kgf/cm2，温度180℃，加热加压时间60分钟。然后，由无电解镍及镀金法，在导线连接端子处进行镀镍/金。镀层厚度分别为3μm、0.3μm。然后，利用装配半导体芯片的芯片连接材料(日立化成工业株式会社制造、商品名：“HM-1”)装配半导体芯片。装配条件为：冲压压力5kgf/cm2，粘接温度380℃，压接时间5秒钟。此后，通过导线连接接通半导体芯片的外部电极与配线图形。此后，冲压加工成引导框架状，放入自动传送膜中，采用半导体专用密封环氧树脂(日立化成工业株式会社制造、商品名：“CL-7700”)，在温度185℃、用90秒的时间进行密封。接着，在前述的凹部印刷涂敷一定量的焊料，利用红外线软溶炉使焊料溶融，形成与外部连接的凸块。最后，将组件冲压取出，得到所需的组件。
结合图18，对本发明第16实施例进行说明。
在金属箔31上直接配置绝缘材料32，在这种双层柔性基材(图18a)的金属箔上设置一定的保护层图形，用众所周知的腐蚀方法形成所需的多组配线图形33，并剥离保护层图形(图18b)。作为金属箔，除了电解铜箔、冲压铜箔或合金铜箔等单一箔外，在经后续工序可被除去的载体箔上设有铜薄层的复合金属箔等也是适用的。具体地讲，在厚度18μm的电解铜箔的单面上，设置厚度0.2μm左右的镍磷镀层后，接着再电镀厚度约为5μm的铜薄层，这种复合金属箔是可以使用的。这种情况下，在铜薄层上形成聚酰亚胺层后，通过腐蚀除去铜箔及镍磷层，露出铜薄层。即，在本申请发明中，既可以在使铜薄层全部露出后再对铜薄层进行配线加工，也可以将载体箔(铜箔/镍薄层)作为引导框架构造体的一部分加以利用。另外，从工艺耐热性等观点来看，聚酰亚胺作为绝缘材料是很一般的。这种情况下，若聚酰亚胺和铜箔的热膨胀系数不同，则在焊料的软溶过程中，基材的翅曲就会明显。因此，作为聚酰亚胺，最好是使用含70摩尔％以上的聚酰亚胺，该聚酰亚胺具有上述化学式1的循环单元。
然后，经后续工序，在将成为与外部基板连接部的位置，设置达到铜箔的凹部34(图18c)。凹部的加工方法无特殊限定，除准分子激光、二氧化碳激光及YAG激光加工方法外，也可采用液体腐蚀方法。
作为第2绝缘基材，将框架基材37与配线图形面相粘接，该框架基材37是对所设定的部分(开口部35)用冲孔加工而成，并带有粘接材料36(图18d)。这里，假设双层柔性基材聚酰亚胺层厚度为25μm，若考虑用后处理法来固定框架，则粘接聚酰亚胺薄膜的厚度必须在50-70μm左右。尤其，粘接聚酰亚胺的区域范围并无特别的限制，也可通过将其设置在装配半导体芯片的部位，像CSP那样，在半导体芯片下面形成外部连接端子。具体地讲，在以导线连接方式装配芯片时，只要最小限度地使导线连接端子38露出，其他区域可全部粘接聚酰亚胺膜。将如此得到的绝缘基板分离成各个配线图形(图18e)，并固定在已特别准备好的、如SUS等的框架43上(图18f)。然后，装配半导体芯片39，并用金线40将半导体芯片和配线图形间接通(图18g)。另外，作为半导体芯片的安装方式，在采用倒焊时，也可在配线图形的一定位置(与半导体芯片外部连接所用电极的位置相对应)设置金属凸块，通过该金属凸块，使半导体芯片与波线图形相接通。然后，放入自动传送模中，用树脂密封材料41进行密封(图18h)在这种情况下，树脂密封材料无特殊限定，比如可以使用含水量在5-80％、含有直径10-20μm的二氧化硅的环氧类树脂等。接着，形成与外部基板的连接部42。作为该连接部42的形成方法，既可采用在图18c的工序后预先通过电解电镀法形成较聚酰亚胺膜要厚一些的凸块的方法，也可采取在树脂密封后由焊锡印刷法形成焊料凸块的方法等。最后由框架切断组件，得到所需的组件(图18i)。
以下对图18中的第16实施例进行更具体的说明。
具体例2
在单面具有厚度12μm的电解铜箔的双层柔性基材(日立化成工业株式会社制造、商品名：“MCF5000I”)铜箔面上，对干膜保护层(日立化成工业株式会社制造、商品名：“PHOTEC HK815”)进行层压，经曝光、显影，得到所需的保护层图形。然后，用氯化铁溶液对铜箔腐蚀加工，用氢氧化钾溶液剥离保护层图形，从而得到所设定的配线图形。然后用准分子激光加工机(住友重型机械工业株式会社制造、商品名：“INDEX200”)、在一定的位置、以一定的数量，形成从绝缘基材一侧达到配线图纹背面的凹部(直径为300μm)。准分子激光的加工条件为：能量密度250mJ/cm2，缩小率3.0，振荡频率200Hz，照射脉冲数300。此后，制造粘接片，该粘接片为：在厚度50μm的聚酰亚胺薄膜(宇部兴产制造、商品名：“UPILEXS”)的单面上，设有厚度10μm的聚酰亚胺类的粘接材料(日立化成工业株式会社制造、商品名：“AS2250”)。用冲孔加工方法除去所设定区域，该设定区域包括在后续工序中设置导线连接端子的区域。这样，通过粘接材料，使聚酰亚胺薄膜与带有配线图形的双层柔性基材经加热而压接。压接条件为：压力20kgf/cm2，温度180℃，加热加压时间为60分钟。然后，由无电解镍及镀金法，在导线连接端子部进行镀镍/金。镀层厚度分别为3μm和0.3μm。将如此得到的基板分离为各配线图形，并固定在另已准备好的SUS框架上。然后，用专用于装配半导体芯片的芯片连接材料(日立化成工业株式会社制造、商品名：“HM-1”)装配半导体芯片。装配条件为：冲压压力5kgf/cm2，粘接温度380℃，压接时间为5秒。经由导线连接使半导体芯片的外部电极部与配线图形相连接。此后，冲压加工呈引导框架状，放入自动传送模中，用半导体专用密封环氧树脂(日立化成工业株式会社制造、商品名：“CL-7700”)，在185℃、90秒钟的条件下进行密封。然后，在前述的凹部处印刷涂敷一定量的焊料，用红外线软溶炉使焊料溶融，形成与外部连接用的凸块。最后，将组件部冲压取出，得到所需的组件。
结合图19、图20和图21，对本发明的第17实施例进行说明。
在支撑体51上，设置多组所需的配线图形52(图19a)。作为该支撑件，除电解铜箔等金属箔外，聚酰亚胺薄膜等绝缘基材也是适用的。
使用绝缘基材时有如下两种方法。第1种方法是，在绝缘基材的设定部位，设置达到配线图形的、未贯通的凹部，在配线图形的露出部位形成外部连接端子。未贯通凹部可利用准分子激光和二氧化碳激光加工形成。第2种方法是，在附带有粘接材料的绝缘基材上预先进行打孔加工，与电解铜箔等进行层压后，对铜箔进行腐蚀加工。
另一方面，在使用金属箔时，首先由光致抗蚀膜等形成保护层图形，然后以金属箔作为阴板，用电镀法形成配线图形。这种情况下，可在通常的电解铜箔和电解铜箔上设置与铜箔的化学腐蚀条件不同的金属(镍、金、锡等)薄层。还有，作为配线图形，铜是可以的，但如前述当以电解铜箔作为支撑体使用时，需要利用与铜箔的腐蚀条件不同的金属作为配线图形，或者，必须在图形镀铜之前就设置一种图形薄层，它能成为铜箔腐蚀的保护层。
然后，利用芯片连接材料53装配半导体元件54，接通半导体元件端子与配线图形(图19b)，利用自动传送注模法和树脂密封材56，将多组半导体元件和配线图形一起密封(19c)。树脂密封材料无特殊的限制，比如，可以使用含水量在5-80％、含有直径10-20μm的二氧化硅的环氧树脂。而且，本发明中，半导体元件的安装方式并不限定为正面焊，比如倒焊的方式也是可以的。具体地讲，在配线图形52上的一定位置，用电镀法形成用于倒焊半导体元件凸块，此后即可使半导体元件的外部连接部与凸块接通。如图20和图21所示，这对后续工序易于分离组件是有效的。其中，图20中具有多个组件，在各组件的分界部设置槽沟59。槽宽和槽深等可通过自动传送模的加工尺寸来控制。另外，在图21中，使用格状中间板60进行自动传送注膜，所述格状中间板60是预先将各组件的相应部分刻槽而形成。然后，当支撑体为金属箔时，利用化学腐蚀等方法除去支撑体，在所设的位置形成外部连接端子57(图19d)。使用绝缘基材作为支撑体时，如前所述，可利用激光等方法有选择地除去所设定部分的绝缘基材。最后，将一起密封的基板切断分离成单元58。而且，为了保护配线图形，也可以在配线图形的露出面上设置焊料保护层。
以下对第17实施例进行具体说明。
具体例3
在边长250mm、厚度35μm的四方形电解铜箔的光泽面上，对感光性干膜保护层(日立化成工业株式会社制造、商品名：″PHOTECHN640″)进行层压，经曝光、显影，形成所需的保护层图形(最少线/间距＝50μm/50μm)。然后，由电镀法形成300个(4区块/250mm×250mm、75个/每区块)同样的配线图形，所述配线图形由厚度0.2μm的镍、30μm的铜、5μm的镍及1μm的软金的镀层构成。接着，利用溶液温度为35℃、浓度为3wt％的氢氧化钾溶液剥离保护层图形，并在85℃温度下干燥15分钟，待切成各块后，采用安装半导体元件的芯片连接材(日立化成工业株式会社制造、商品名：“HM-1”)粘接半导体元件。其粘接条件为：冲压压力5kgf/cm2，温度380℃及压接时间5秒钟。然后，用导线接通半导体元件外部端子与镀金端子部(第2连接部)，并放入自动传送模中，用半导体密封用环氧树脂(日立化成工业株式会社制造、商品名：“CL-7700”)在185℃、90秒钟的条件下，将75个(相当于1块)配线图形一起密封，由此将各配线图形转印至密封材上。然后，采用碱腐蚀方法(Meltex株式会社制造、商品名：“A工艺方法“)腐蚀除去电解铜箔的所需部分。腐蚀液的温度为40℃，喷射压力为1.2kgf/cm2。利用印刷法在外部连接端子部位形成焊料图形，利用红外线软溶炉使焊料溶融，从而形成用于外部连接的凸块。最后，利用金刚石割刀分离各组件部分，得到所需的组件。
具体例4
在边长为250mm、厚35μm的四方形电解铜箔的光泽面上，对感光性干膜保护层(日立化成工业株式会社制造、商品名：“PHOTECHN640”)进行层压，经曝光、显影，形成所需的保护层图形(最少线/间距＝50μm/50μm)。接着，利用电镀法形成300个(4块/250mm×250mm、75个/块)同样的配线图形，所述配线图形由厚度0.2μm的镍、30μm铜、5μm的镍及1μm的软金的镀层构成。然后，利用温度为35℃、浓度3wt％的氢氧化钾溶液，剥离保护层图形，在85℃温度下干燥15分钟后，切断各块，此后利用安装半导体元件的芯片连接材(日立化成工业株式会社制造、商品名：“HM-1”)粘接半导体元件。粘接条件为：冲压压力5kgf/cm2，温度38℃及压接时间5秒钟。然后用导线将半导体元件的外部端子与镀金端子部分(第2连接部)相连通。用已将相当于组件区域位置(15mm×15mm)刻去而成的格状不锈钢板作为中间板，放入自动传送模中，采用半导体密封专用环氧树脂(日立化成工业株式会制造、商品名：“CL-7700”)在温度185℃、时间90秒钟的条件下，将75个(相当于1块)配线图形一起密封，从而将各配线图形转印至密封材上。为使各组件易于从中间板分离，在中间板的格子部设置12°的锥度。然后，采用碱腐蚀方法(Meltex株式会社制造、商品名：“A工艺过程”)除去电解铜箔的所需部分。各组件保持在格子状中间板里。腐蚀液的温度为40℃，压力为1.2kgf/cm2。最后，用印刷法在外部连接端子部位设置焊料图形，并利用红外线软溶炉使焊料溶融，从而形成用于外部连接的凸块，将各组件从中间板部分离，得到所需的组件。
结合图22，对本发明第18实施例进行说明。
在导电性临时支撑体61(图22a)上设置多组所需的保护层图形62(图22b)。并由电镀法在临时支撑体的露出部分设置配线图形63。这种情况下，临时支撑体无特殊限制，比如，也可以在通常的电解铜箔和电解铜箔面上，设置与铜箔具有不同化学腐蚀条件的金属(镍、金、焊锡等)的薄层。另外，作为配线图形可以使用铜，但也可如前所述，当电解铜箔作为临时支撑体使用时，可将与铜箔具有不同腐蚀条件的金属作为配线图形使用，或者，在图形镀铜之前，就必须先设置图形薄层，它为铜箔腐蚀时的保护层。关于临时支撑体的厚度，在对后续工序的可操作性以及安装半导体元件时的尺寸无影响的情况下，并无特别的限制。然后，将临时支撑体作为阴极，在进行金丝连接所需的电镀(通常为镍/金)64之后，除去保护层图形(图22c)。而且，在本发明中，半导体元件的安装方式并不限于正焊方式，如倒焊方式也是适用的。具体地讲，采用电镀法在配线图形63上所需位置设置形成用于倒焊连接的凸块后，即可将半导体元件的外部连接部与凸块接通。
然后，用芯片连接材66粘接半导体元件65，并接通半导体元件的外部连接端子与配线图形(图22d)。此后，将其放入自动传送模中，用树脂密封材料68进行密封(图22e)。此种情况下，树脂密封材料无特别限定，比如，可以使用含水量为5-80wt％、含有直径10-20μm二氧化硅的环氧树脂。
此后，在相当于外部连接端子处，设置所需的金属图形69(图22f)。此种情况下，作为适用的金属，只要在腐蚀除去导电性临时支撑体条件下不被腐蚀即可，比如焊锡、金、镍/金等均可适用。另外，作为形成金属图形的方法，可采用众所周知的电镀法和焊锡印刷法等。而且，当用焊锡印刷法形成金属图形69的情况下，可以利用软溶过程来形成焊锡凸块70。这时，通过调节图形69的厚度，可控制软溶后的焊锡凸块70的高度。然后，以金属图形作为腐蚀保护层，除去临时支撑体所设定的部分，使配线图形露出。
最后，利用冲压加工，或者切割加工法等，分割各组件71(图22g)。尤其，在对露出的配线图形未用镍等耐腐蚀金属进行保护情况下，也可利用众所周知的焊料保护层来覆盖外部连接端子之外的区域。而且，在使用锡作为金属图形时，对软溶工艺并无特别的限定，在分割各组件的前、后均可使用，或者在向外部配线基板上安装各组件时，亦可使用。
以下对第18实施例进行具体说明。
具体例5
在厚度70μm的电解铜箔的光泽面上，对感光干膜保护层(日立化成工业株式会社制造、商品名：“PHOTEC HN640”)进行层压，经曝光、显影，形成所需的保护层图形(最少线/间距＝50μm/50μm)。然后，用电镀法形成由厚度0.2μm的镍、30μm的铜、5μm的镍及1μm的软金组成的配线图形。接着，用溶液温度35℃、浓度3wt％的氢氧化钾溶液剥离保护层图形，在85℃下干燥15分钟后，用安装半导体元件的芯片连接材(日立化成工株式会社制造、商品名：“HM-1”)粘接半导体元件。粘接条件为：冲压压力5kgf/cm，温度380℃及压接时间5秒钟。在用导线接通半导体外部端子与镀金端子部(第2连接部)后，将其放入自动传送模中，使用半导体密封专用的环氧树脂(日立化成工业株式会社制造、商品名：“CL-7700”)，在185℃、用90秒的时间进行密封，将配线图形转印至密封材上。然后，在电解铜箔上对感光干膜保护层(日立化成工业株式会社制造、商品名：“PHOTEC HN340”)进行层压，经曝光、显影，形成所需的保护层图形，然后，用电镀方法设置厚度40μm的焊锡垫片(直经为0·3mmφ)，设置间距为1·0mm)。此后，在剥离干膜保护层后，利用碱腐蚀方法(Metex株式会社制造、商品名：“A工艺方法”)腐蚀除去欲清除部分的电解铜箔。腐蚀液的温度为40℃，喷射压力1·2kgf/cm2。最后，利用红外线软溶炉使焊锡熔融，形成用于外部连接的凸块。
结合图23、图24和图25，对本发明第19实施例进行说明。
利用图23说明安装半导体所用框架的构成。89为半导体安装基板，它由绝缘基材和配线构成。通过基板和连结部90形成多个连接。在连接部90上设有基准位置销孔91。不使用销孔91，也可使用图像识别中的识别标记。在后续工艺中，将以这些基准位置来定位。尤其用树脂对半导体进行浇注时，将洞内的销子插入销孔91以对合位置。
利用图24和图25作进一步说明。在作为导电性临时基板的、厚度0.070mm的电解铜箔81的单面上，用电镀形成厚度0.001mm的镍层(图24、25中省略)。然后对感光性干膜保护层(日立化成工业株式会社制造、商品名：“PHOTEC HN340”)进行层压，经曝光、显影，形成多组配线图形的电镀保护层。此时的曝光量为70mJ/cm2。接着，在众所周知的硫酸铜液中进行电解镀铜，并剥离保护层，形成多组配线82(图24a、图25a)。这里，如图25a所示，也可以考虑在连结部形成镀铜82，由此可以进一步提高已完成的框架的刚度。图24a和图25a所表示的构成，通过下述工艺也可得到：预先准备好由铜/镍薄层/铜这三层组成的基材，并用通常的腐蚀工艺在所述基材的一面形成配线。另外，也可以将这样得到的铜箔81/镍薄层(图中未示)/铜配线82(及82′)的构成作成铜箔/镍配线、镍箔/铜配线等无镍薄层的双层结构。也就是说，金属种类的选择并不限制本实施例的种类，但也有如下选择的适宜标准：当在后续工艺中腐蚀除去临时基板的一部分时(图24c，图25c)，应能使配线有选择地保留。而且，为了成为框架连结部的组成材料，导电性临时基板最好是厚一些，由于后面还有将其一部分腐蚀除去的工序，所以必须选择适当的厚度。作为导电性临时基板的厚度，这取决于材质，比如，使用铜箔时，最好能在0.03-0.3mm左右。然后，在设有多组配线82的铜箔81上的配线一面，粘接聚酰亚胺粘接剂83。这里的聚酰亚胺粘接剂83，并不限于该种材料，比如，也可以利用环氧类粘接膜、在聚酰亚胺膜上涂敷粘贴剂的薄膜等。接着，利用准分子激光加工，形成外部连接端子用孔穴84(图24b、图25b)。为了后续工序中工艺简化，在安装半导体前，预先设置连接端子是合适的。另外，作为形成该孔穴84的方法，此外还可在薄膜上采用钻孔和冲压加工手段预先形成外部连接端子用孔穴84，然后再将该薄膜粘接。而且，这里也可以在孔穴84中充填作为连接端子用的焊锡等金属(相当于图24f、图25f的88)，但在后面的半导体安装工序、树脂密封工艺中，金属突起有时会形成障碍，故最好还是在后续工序中形成。作为半导体元件安装基板部的外部连接端子用孔穴(或端子)，最好能以阵列状形式设置在安装半导体元件一面的背面。
然后，腐蚀除去电解铜箔的一部分，所述电解铜箔为形成配线图形那部分的临时基板。作为该腐蚀液，在本实施例构成的情况下，可以选择较镍相比、铜的溶解速度显著高的腐蚀液和腐蚀条件。在本实施例中，作为腐蚀液是碱腐蚀剂(Meltex株式会社制造、商品名：“A工艺法”)，腐蚀条件比如溶液温度为40℃，喷射压力为1.2kgf/cm2。这里所示的溶液的种类和条件只是个例子而已。通过该工序使基板部的镍薄层露出。在只腐蚀该镍薄层时，可以选择与铜相比、对镍的溶解速度阴显高的腐蚀液和腐蚀条件。在本实施例中，是利用镍腐蚀剂(Meltex株式会社制造、商品名：“Melstrip N 950”)有选择性地进行腐蚀清除。腐蚀液的温度为40℃，喷射压力为1.2kgf/cm2。这里所示的溶液的种类和条件也只是一例而已。经过这样的工序，保留了连接部的临时基板，并得到具有一定刚度的半导体安装用框架(图24c、图25c)。在本实施例中，在该框架的铜配线端子部进行无电解镍——金电镀(图中省略)。为了在后续工序中导线连接芯片，这是必要的，根据需要也可进行这样的表面处理。
然后，装配半导体芯片85。粘接半导体芯片时，使用了半导体用芯片焊接条86(日立化工株式会社制造、商品名：“HM-1”)。这里，在芯片下面无配线时，也可以使用芯片焊接用的银焊料来粘接。此后，利用导线100连接半导体端子与配线(图24d、图25d)。与半导体端子的连接，也可以采用其他方法，如采用倒焊的倒装片连接，以及利用各向异性导电性反粘结剂的粘接。如此形成之后，将该件放入自动传送模中，用半导体密封用环氧树脂(日立化成工业株式会社制造、商品名：“CL-7700”)分别进行密封87(图24e、图25e)。此后，在配线82的连接端子处设置的连接用孔穴中，溶融、形成焊料球88(图24f、图25f)。该焊料球88将成为所谓的外部连接端子。将由连结部102相连的多部半导体装置冲压取出，得到各个半导体装置(图24g、25g)。
在本实施例中，通过采用半导体安装支框架及半导体装置制造方法，在使用聚酰亚胺条等薄膜基板的BGA、CSP等半导体装置制造中，可获得具有足够刚度的框架，并通过利用该框架，可以高精度、高效率地制造半导体装置。
根据本发明，可生产性良好、且稳定地制造能适应半导体芯片高度集成化要求的半导体组件。

Claims (28)

1.半导体元件装载用基板的制造方法，该半导体元件装载用基板具有绝缘性支撑体和在该支撑体的单面上形成的多条配线，其特征在于，具有：
在上述绝缘性支撑体的表面上形成多组半导体元件装载区域和该半导体装载区域的外侧的树脂密封用半导体封装区域的工序；
在上述半导体封装区域中形成金属线焊接端子、且在上述半导体元件装载区域中形成外部连接端子、且形成将该金属线焊接端子和该外部连接端子串接在一起的上述配线的配线形成工序，以及
在形成上述外部连接端端子的地方的上述绝缘性支撑体上形成到达上述外部连接端子的开口部的开口部形成工序。
2.权利要求1所述的半导体元件装载用基板的制造方法，其特征在于：在上述每个半导体元件装载区域中形成两个以上的上述外部连接端子。
3.权利要求1或2所述的半导体元件装载用基板的制造方法，其特征在于：在上述配线的表面上，还具有实施镀镍和金的工序。
4.权利要求1至3中的任何一项所述的半导体元件装载用基板的制造方法，其特征在于：上述绝缘性支撑体是聚酰亚胺薄膜。
5.权利要求1至4中的任何一项所述的半导体元件装载用基板的制造方法，其特征在于：在上述半导体元件装载区域中形成格子状的上述外部连接端子。
6.权利要求1至5中的任何一项所述的半导体元件装载用基板的制造方法，其特征在于：上述开口部的形成实施了打孔加工、钻孔加工、激光加工和湿法蚀刻加工中的至少一种。
7.权利要求1至5中的任何一项所述的半导体元件装载用基板的制造方法，其特征在于：
上述绝缘性支撑体在表面上有粘结剂层，
在上述开口部形成工序之后，
还具有在通过上述粘结剂将上述绝缘性支撑体和金属箔粘结在一起的工序，
上述配线形成工序是通过对上述被粘结的金属箔进行蚀刻来形成上述配线的工序。
8.权利要求1至6中的任何一项所述的半导体元件装载用基板的制造方法，其特征在于：
上述绝缘性支撑体在表面上有金属箔，
上述配线形成工序是通过对上述金属箔进行蚀刻来形成上述配线的工序。
9.半导体元件装载用基板，该半导体元件装载用基板具有绝缘性支撑体和在该支撑体的单面上形成的多条配线，其特征在于，具有：
多组半导体元件装载区域和该半导体装载区域的外侧的树脂密封用半导体封装区域；
上述配线含有将在上述半导体封装区域中形成的金属线焊接端子和在上述半导体元件装载区域中形成的外部连接端子串接在一起的配线，以及
10.权利要求9所述的半导体元件装载用基板，其特征在于：在上述每个半导体元件装载区域中设置有两个以上的上述外部连接端子。
11.权利要求9或10所述的半导体元件装载用基板，其特征在于：在上述配线的表面上，还具有镀镍和金的层。
12.权利要求9至11中的任何一项所述的半导体元件装载用基板，其特征在于：上述绝缘性支撑体是聚酰亚胺薄膜。
13.权利要求9至12中的任何一项所述的半导体元件装载用基板，其特征在于：在上述半导体元件装载区域中形成格子状的上述外部连接端子。
14.权利要求9至13中的任何一项所述的半导体元件装载用基板，其特征在于：上述开口部是通过实施打孔加工、钻孔加工、激光加工和湿法蚀刻加工中的至少一种来打开的。
15.半导体元件装载用基板的制造方法，该半导体元件装载用基板具有绝缘性支撑体和多条配线，其特征在于，具有：
在上述绝缘性支撑体的表面上形成多组半导体元件装载区域和该半导体装载区域的外侧的树脂密封用半导体封装区域的工序；以及
具有形成含有金属线焊接端子、外部连接端子的确定的配线图形的配线形成工序，
上述金属线焊接端子设置在上述树脂密封用半导体封装区域中；
上述外部连接端子设置在上述半导体装载区域中。
16.权利要求15所述的半导体元件装载用基板的制造方法，其特征在于：
上述配线形成工序是形成对具有同一上述图形的半导体元件装载区域及上述半导体封装区域进行排列从而构成上述配线的多个块的工序。
17.权利要求15或16所述的半导体元件装载用基板的制造方法，其特征在于：还具有在上述金属线焊接端子的表面上镀镍和金的工序。
18.权利要求15至17中的任何一项所述的半导体元件装载用基板的制造方法，其特征在于：
上述外部连接端子在上述绝缘性支撑体的装载上述半导体元件的面的背面露出，被配置在对应于上述半导体装载区域及上述半导体封装区域的位置上。
19.权利要求15至18中的任何一项所述的半导体元件装载用基板的制造方法，其特征在于：
上述绝缘性支撑体在表面上有金属箔，
上述配线形成工序是通过对上述金属箔进行蚀刻来形成上述配线的工序。
20.半导体元件装载用基板，该半导体元件装载用基板具有绝缘性支撑体和多条配线，其特征在于：
具有多组半导体元件装载区域和该半导体装载区域的外侧的树脂密封用半导体封装区域；
上述配线具有含有金属线焊接端子和外部连接端子的确定的配线图形，以及
上述金属线焊接端子设置在上述树脂密封用半导体封装区域中；
上述外部连接端子设置在上述半导体装载区域中，
对具有同一上述配线图形的半导体元件装载区域及上述半导体封装区域进行多个排列。
21.权利要求20所述的半导体元件装载用基板，其特征在于：设有对具有同一上述图形的半导体元件装载区域及上述半导体封装区域进行多个排列从而构成的上述配线的多个块。
22.权利要求20或21所述的半导体元件装载用基板，其特征在于：还具有在上述金属线焊接端子的表面上镀镍和金的层。
23.权利要求20至22中的任何一项所述的半导体元件装载用基板，其特征在于：
上述外部连接端子在上述绝缘性支撑体的装载上述半导体元件的面的背面露出，被配置在对应于上述半导体装载区域及上述半导体封装区域的位置上。
24.半导体元件安装用基板，其特征在于：
具有：该半导体元件安装用基板具有用于装载各个半导体元件的多个半导体安装基板部件、用于在上述半导体元件安装基板部之间连结的连结部和对准位置的标记部，
该半导体元件安装用基板部件具有：
上述半导体元件装载区域，
上述半导体元件装载区域的外侧的树脂密封用半导体封装区域，以及
含有上述设置在上述树脂密封用半导体封装区域中的金属线焊接端子和设置在上述半导体元件装载区域的外部连接端子的配线，
上述连结部具有导电层。
25.权利要求24所述的半导体元件安装用基板，其特征在于：上述导电层和上述配线由同一材料构成。
26.权利要求24或25所述的半导体元件安装用基板，其特征在于：在上述配线的表面实施镀镍/金。
27.半导体元件安装用基板的制造方法，具有：用于安装半导体元件的具有各个配线的多个半导体元件安装基板部，将上述多个半导体元件基板部进行连接、有导电层的连结部，对准位置的标记部，上述半导体元件安装基板部具有上述半导体元件装载区域和上述半导体元件装载区域的外侧的树脂密封用半导体封装区域，其特征在于：
具有将含有设置在上述树脂密封用半导体封装区域中的金属线焊接端子和设置在上述半导体元件装载区域的外部连接端子的配线、上述连结部的上述导电层和树脂材料一起形成的配线形工序。
28.权利要求27所述的半导体元件安装用基板的制造方法，其特征在于：上述配线形成工序具有通过电镀形成上述配线和上述导电层的工序。
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EP0751561A1 (en) 1997-01-02

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