CN102842546A - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

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CN102842546A
CN102842546A CN201110193715XA CN201110193715A CN102842546A CN 102842546 A CN102842546 A CN 102842546A CN 201110193715X A CN201110193715X A CN 201110193715XA CN 201110193715 A CN201110193715 A CN 201110193715A CN 102842546 A CN102842546 A CN 102842546A
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dielectric layer
semiconductor package
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CN102842546B (zh
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洪良易
白裕呈
孙铭成
林俊贤
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Siliconware Precision Industries Co Ltd
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Abstract

一种半导体封装件及其制法，包括：具有相对的第一与第二表面及侧面的介电层；铜材的线路层，其形成于该介电层的第一表面上，该线路层具有延伸垫；表面处理层，其形成于该线路层上；半导体芯片，其设于该线路层上并电性连接该表面处理层；以及形成于该介电层的第一表面上的封装胶体，其包覆该半导体芯片、线路层及表面处理层，且外露该介电层的第二表面，又该介电层的侧面与该封装胶体之间具有通孔，使该延伸垫位于该通孔中。借由外露于通孔的延伸垫结合焊球，因铜材与焊锡材料之间的电性连接较佳，所以可提升电性连接的品质。

Description

半导体封装件及其制法
技术领域
本发明有关一种半导体封装件，尤指一种无承载件的半导体封装件。
背景技术
传统以导线架作为芯片承载件的半导体封件的型态及种类繁多，就四边扁平无导脚(Quad Flat Non-leaded，QFN)半导体封装件而言，其特征在于未设置有外导脚，即未形成有如现有四边形平面(Quad Flatpackage，QFP)半导体封装件中用以与外界电性连接的外导脚，如此，将得以缩小半导体封装件的尺寸。
然而伴随半导体产品轻薄短小的发展趋势，传统导线架的QFN封装件往往因其封装胶体厚度的限制，而无法进一步缩小封装件的整体高度，因此，业界便发展出一种无承载件(carrierless)的半导体封装件，借由减低习用的导线架厚度，以令其整体厚度得以较传统导线架式封装件更为轻薄。
请参阅图1，其为第5,830,800号美国专利所揭示的无承载件的半导体封装件，该半导体封装件1主要先于一铜板(未图标)上形成多数电镀焊垫14；再于该铜板上设置半导体芯片16并透过焊线17电性连接半导体芯片16及焊垫14，并进行封装模压制程以形成封装胶体18，再移除该铜板而外露该焊垫14，接着以拒焊层11定义出该焊垫14位置，以供植设焊球19于该焊垫14上，借以完成该半导体封装件1。相关的技术内容也可参阅美国专利第6,770,959、6,989,294、6,933,594及6,872,661等。
前述焊垫的设置数目大致因应布设于芯片的作用表面上的电极垫数目，以使各芯片电极垫借由焊线电性连接至对应的焊垫。然而，当欲使用高度积集化(Highly Integrated)的芯片时，即该芯片具有数量较多或密度较高的电极垫，相对地需布设较多焊垫，而使焊垫与芯片间的距离及焊线的弧长增加；过长的焊线不仅使焊线(Wire Bonding)作业的困难度提升，且于形成封装胶体的模压(Molding)作业进行时，过长的焊线易受树脂模流的冲击而产生偏移(Sweep)或移位(Shift)现象，偏移或移位的焊线则可能彼此触碰而导致短路(Short)问题，影响电性连接品质；此外，若焊垫与芯片间相距过远，则可能使焊线作业难以进行，而造成无法借焊线方式电性连接芯片至焊垫的情况。又，过长的焊线将增加材料成本。
鉴此，美国专利第7,638,879号遂揭示一种利用线路重布置层(Redistribution layer，RDL)技术以使焊垫可延伸至邻近芯片周围，而减少焊线长度或交错情况，且降低焊线的材料成本。如图2所示，该半导体封装件2先将一介电层21借由结合层200形成于一铜材的承载板20上，并于该介电层21上开设多个开孔210，且以电镀方式形成镍/金材25于各该开孔210中；再以电镀方式形成铜材的线路层24于该介电层21与镍/金材25上，且该线路层24的端部为焊垫241；再设置半导体芯片26于该介电层21上，并借焊线27电性连接该半导体芯片26与该焊垫241，且形成封装胶体28以包覆该半导体芯片26及焊线27；最后移除该承载板20与结合层200，而使该介电层21及该镍/金材25外露。
然，现有半导体封装件2中，需以该镍/金材25结合焊锡材料(图未示)以接置于一电路板(图未示)上，但该镍/金材25与焊锡材料之间的电性及散热效果不佳，导致电性连接的品质不佳。
另外，该承载板20为铜材，其材料价格高，导致材料成本提高。
又，该半导体封装件2接置于电路板上时，其先于该电路板的电性连接垫上形成0.1mm的焊锡膏，再将该镍/金材25结合至该焊锡膏上。然若该半导体封装件2发生翘曲(warpage)时，因该焊锡膏太薄，使该镍/金材25无法接置于该焊锡膏上，因而导致电性连接不良。
因此，如何解决上述问题而能提供一种无承载件的半导体封装件及其制法，以提升封装件电性品质并降低成本，实为目前业界亟待解决的课题。
发明内容
为克服现有技术的问题，本发明的主要目的在于提供一种半导体封装件及其制法，可提升电性连接的品质。
本发明之半导体封装件包括：介电层，其具有相对的第一表面与第二表面、及相邻该第一表面与第二表面的侧面；铜材的线路层，其形成于该介电层的第一表面上；表面处理层，其形成于该线路层上；半导体芯片，其设于该线路层上并电性连接该表面处理层；以及封装胶体，其形成于该介电层的第一表面上以包覆该半导体芯片、线路层及表面处理层，且外露该介电层的第二表面，又该介电层的侧面与该封装胶体的间具有通孔，使部分该表面处理层位于该通孔中。
前述的封装件中，该线路层可具有延伸线路，该延伸线路的一端具有设于该介电层的第一表面上的第一接触垫，该延伸线路的另一端为形成于该表面处理层上以外露于该通孔的延伸垫。
前述的封装件中，该铜材的线路层还可具有第二接触垫，其形成于该介电层的第一表面上，且该半导体芯片设于该第二接触垫上，又该介电层的第二表面上具有多个连通该介电层的第一表面的开孔，以外露出该线路层的部分表面。
本发明还提供一种半导体封装件的制法，其包括：提供一由铁合金或铜合金所制的承载板，于该承载板的表面上定义承载区与邻接该承载区外的延伸区；形成介电层于该承载板的承载区上，且该介电层具有外露的第一表面、结合至该承载板上的第二表面、及相邻该第一与第二表面的侧面；形成铜材的线路层于该介电层的第一表面与该承载板延伸区的部分表面上，该线路层具有延伸线路，该延伸线路的两端具有第一接触垫与延伸垫，该第一接触垫形成于该介电层的第一表面上，而该延伸垫形成于该承载板延伸区上；形成表面处理层于该线路层上；将半导体芯片设于该介电层的第一表面上且电性连接该表面处理层；于该承载板与该介电层的第一表面上形成封装胶体，以包覆该半导体芯片与线路层，使该延伸垫位于该介电层侧面与该延伸区上的封装胶体之间；移除该承载板，以外露出该介电层的第二表面，且令该延伸垫外露于该介电层的第二表面与封装胶体表面；以及移除部份该延伸垫，以于该介电层侧面与该封装胶体之间形成通孔。
前述的制法中，形成该线路层与表面处理层的制程，其包括：形成阻层于该介电层的第一表面与该承载板上，且于该阻层上形成多个第一开口，以外露出该承载板的延伸区及连通该延伸区的介电层部分第一表面；形成该线路层于该第一开口中；形成该表面处理层于该线路层上；以及移除该阻层，以外露该承载板延伸区的部分表面。
依上述制法，该阻层还形成有第二开口，以外露出该介电层的另一部分第一表面，且该线路层还形成于该第二开口中，所以还包括于形成该阻层之前，于该介电层上形成多个开孔，以外露出该承载板的承载区表面，且该阻层的第二开口连通该开孔，而该线路层还形成于该第二开口及开孔中，当移除该承载板后，还包括移除该开孔中的铜材，以外露出线路层的部份表面，以作为第二接触垫。另外，于移除部份该延伸垫时，同时移除部份该第二接触垫，以形成焊球于该开孔中。又，前述的制法中，可包括移除该延伸垫的剩余部份，以外露该表面处理层于该通孔中。
另外，前述的封装件及其制法中，可形成焊球于该通孔中，且该表面处理层的结构为形成于该线路层上的金层、形成于该金层上的镍层、及形成于该镍层上的金、铅或银材。
由上可知，本发明半导体封装件及其制法，其借由铜材的线路层的延伸垫外露于通孔，以结合焊球，因铜材与焊锡材料的间的电性连接较佳，且具有更好的导热效果，所以可提升电性连接的品质。
此外，本发明的制法中，该承载板是由铁合金或铜合金所制，所以成本相较于现有技术的纯铜低，因而可降低材料成本。
又，本发明半导体封装件在接置于电路板上时，其可先形成焊球于该通孔中的延伸垫上，再将该焊球结合至0.1mm的焊锡膏上。若本发明半导体封装件发生翘曲(warpage)时，可借由焊球准确接置于该焊锡膏上，所以不易发生电性连接不良的问题。
另外，依前述的本发明半导体封装件及其制法，本发明还提供更具体技术，详如后述。
附图说明
图1用于显示美国专利第5,830,800号的无承载件的半导体封装件的剖面示意图；
图2用于显示美国专利第7,638,879号的无承载件的半导体封装件的剖面示意图；
图3A至图3I为本发明半导体封装件的制法的剖面示意图；其中，图第3D(a)为图3D的局部放大图，图3H’及图3I’为图3H及图3I的另一种实施方式；以及
图4为本发明半导体封装件接置电路板的剖面示意图。
主要组件符号说明
1，2，3，3’     半导体封装件
11               拒焊层
14，241          焊垫
16，26，36       半导体芯片
17，27，37       焊线
18，28，38       封装胶体
19，39           焊球
20，30           承载板
200              结合层
21，31           介电层
210，310，310’  开孔
24，34           线路层
25               镍/金材
31a              第一表面
31b              第二表面
31c，34a         侧面
32               导电层
33               阻层
330              第一开口
330’            第二开口
340              延伸线路
341              第一接触垫
342              延伸垫
343            第二接触垫
35             表面处理层
35a            金层
35b            镍层
35c            金、铅或银材
380，380’     通孔
4              电路板
40             焊锡膏
L              切割线
E              延伸区
S              承载区
d              厚度
h              凸出高度。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，熟悉本领域的技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技艺的人士的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”、“底”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，也当视为本发明可实施的范畴。
请参阅图3A至图3I，其为本发明半导体封装件的制法的剖面示意图。
如图3A所示，提供一铁合金或铜合金所制的承载板30，于该承载板30的表面上定义出承载区S与邻接该承载区S外围的延伸区E。
接着，形成一介电层31于该承载板30的全部承载区S上，且利用图案化制程，于该介电层31上形成多个开孔310(本图中以一个开孔310说明)，以外露出该承载板30承载区S的部分表面。于本实施例中，该介电层31具有外露的第一表面(如图所示的上表面)31a、结合至该承载板30上的第二表面(如图所示的下表面)31b、及相邻该第一表面31a与第二表面31b的侧面31c。
如图3B所示，形成导电层32于该介电层31的第一表面31a、侧面31c、开孔310与该承载板30延伸区E表面上。
如图3C所示，再于该导电层32上形成阻层33，且于该阻层33上形成多个第一开口330，以外露出该承载板30部分延伸区E上的导电层32、及连通该延伸区E的介电层31侧面31c与部分第一表面31a上的导电层32。
于本实施例中，该阻层33还形成有第二开口330’，以外露出该介电层31的另一部分第一表面31a，且该第二开口330’连通该开孔310，以外露出该开孔310上的导电层32。
如图3D所示，借由电镀铜材的方式，形成线路层34于该第一及第二开口330，330’中的导电层32上与该开孔310中的导电层32上，该线路层34具有延伸线路340，该延伸线路340的两端分别具有第一接触垫341与延伸垫342，该第一接触垫341形成于该介电层31的第一表面31a上，而该延伸垫342形成于该承载板30延伸区E上。
接着，形成表面处理层35于该线路层34上。于本实施例中，如图3D(a)所示，该表面处理层35的结构为形成于该线路层34上的金层35a、形成于该金层35a上的镍层35b、及形成该镍层35b上的金、铅或银材35c。
如图3E所示，移除该阻层33及其覆盖的导电层32，以外露出该承载板30延伸区E的部分表面。
如图3F所示，将半导体芯片36设于该承载区S的线路层34上，且以焊线37电性连接该表面处理层35与半导体芯片36。于其它实施例中，该半导体芯片也可以覆晶方式电性连接该表面处理层。
接着，于该承载板30延伸区E的外露表面与该介电层31的第一表面31a上形成封装胶体38，以包覆该半导体芯片36、焊线37与线路层34，使该延伸垫342位于该介电层31侧面31c与该延伸区E上的封装胶体38之间。
如图3G所示，移除该承载板30，以外露出该介电层31的第二表面31b与封装胶体38底面，令该延伸垫342外露于该介电层31的第二表面31b与封装胶体38底面，部分的线路层34也外露于该开孔310，以供作为第二接触垫343。
如图3H所示，移除该延伸垫342的部分材质及其上的导电层32，以于该介电层31的侧面31c与该封装胶体38之间形成通孔380，且移除该开孔310中的铜材，以外露出该第二接触垫343。
于另一实施例中，移除该延伸垫342的剩余部分与该第二接触垫343，以外露该表面处理层35于该通孔380’及该开孔310’中，如图3H’所示。
另外，可进行切单制程，如图3G所示的切割线L，以取得单一半导体封装件3，3’。
如图3I所示，形成焊球39于该通孔380中的延伸垫342上与该开孔310中的第二接触垫343上。
其次，当该半导体芯片36未电性连接该第二接触垫343时，该第二接触垫343可作散热之用；该半导体芯片36电性连接该第二接触垫343时，该第二接触垫343可作电性传导与散热之用。
如图3I’所示，将该焊球39形成于该通孔380或该开孔310中的表面处理层35(金层35a)上，令该焊球39结合至该线路层34的侧面34a，以提高电性及散热效果。
本发明还提供一种半导体封装件3，3’，包括：介电层31，其具有相对的第一表面31a与第二表面31b、及相邻该第一表面31a与第二表面31b的侧面31c；铜材的线路层34，其形成于该介电层31的第一表面31a上；表面处理层35，其形成于该线路层34上；半导体芯片36，设于该线路层34上方并电性连接该线路层34与表面处理层35；以及封装胶体38，其形成于该介电层31的第一表面31a上以包覆该半导体芯片36、线路层34及表面处理层35，且外露该介电层31的第二表面31b，又该介电层31的侧面31c与该封装胶体38之间具有通孔380，380’，以于该通孔380，380’中形成焊球39。
于一实施方式中，部分该表面处理层35位于该通孔380中，且该线路层34具有延伸线路340，该延伸线路340的一端具有设于该介电层31的第一表面31a上的第一接触垫341，该延伸线路340的另一端为形成于该表面处理层35上而外露于该通孔380的延伸垫342。
于另一实施方式中，部分该表面处理层35外露于该通孔380’中。
于该半导体封装件3，3’中，该线路层34具有第二接触垫343，形成于该介电层31的第一表面31a上，令该半导体芯片36设于该第二接触垫343上方。另外，该介电层31的第二表面31b上具有多个连通该介电层31的第一表面31a的开孔310，310’，以外露出该线路层34的部分表面(如第二接触垫343)或该表面处理层35。又包括形成于该开孔310，310’中的焊球39，以电性连接该线路层34。
另外，该表面处理层35的结构为形成于该线路层34上的金层35a、形成于该金层35a上的镍层35b、及形成于该镍层35b上的金、铅或银材35c。
综上所述，本发明半导体封装件3及其制法，借由铜材的延伸垫342外露于该介电层31的侧面31c与该封装胶体38之间的通孔380、或第二接触垫343外露于该开孔310，以结合焊球39；相较于现有技术，本发明半导体封装件3因铜材(延伸垫342)与焊锡材料(焊球39)之间的电性连接较佳，所以有效提升电性连接的品质，且具有更好的导热效果。
其次，本发明半导体封装件3的制法中，该承载板30是由铁合金或铜合金所制，所以成本相较于现有技术的纯铜低，因而可降低材料成本。
又，如图4所示，在将本发明半导体封装件3接置于一电路板4上时，是用形成于该延伸垫342上的焊球39结合至该电路板4上的厚度d约为0.1mm的焊锡膏40上。因该焊球39的凸出高度h约为0.3mm，所以可提供较高的接合凸块(stand-off)，若本发明半导体封装件3发生翘曲(warpage)时，仍可借由焊球39有效接置于该焊锡膏40上，因而不会发生电性连接不良的问题。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉本领域的技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (16)

1.一种半导体封装件，包括：
介电层，其具有相对的第一表面与第二表面、及相邻该第一表面与第二表面的侧面；
铜材的线路层，其形成于该介电层的第一表面上；
表面处理层，其形成于该线路层上；
半导体芯片，其设于该线路层上方并电性连接该线路层与表面处理层；以及
封装胶体，其形成于该介电层的第一表面上以包覆该半导体芯片、线路层及表面处理层，且外露该介电层的第二表面，又该介电层的侧面与该封装胶体之间具有通孔，使部分该表面处理层位于该通孔中。
2.根据权利要求1所述的半导体封装件，其特征在于，该线路层具有延伸线路，该延伸线路的一端具有设于该介电层的第一表面上的第一接触垫，该延伸线路的另一端为形成于该表面处理层上而外露于该通孔的延伸垫。
3.根据权利要求1所述的半导体封装件，其特征在于，该线路层具有第二接触垫，其形成于该介电层的第一表面上，令该半导体芯片设于该第二接触垫上方。
4.根据权利要求1所述的半导体封装件，其特征在于，该介电层的第二表面上具有多个连通该介电层的第一表面的开孔，以外露出该线路层的部分表面。
5.根据权利要求4所述的半导体封装件，其特征在于，该封装件还包括形成于该开孔中的焊球，以电性连接该线路层。
6.根据权利要求1所述的半导体封装件，其特征在于，该表面处理层的结构为形成于该线路层上的金层、形成于该金层上的镍层、及形成于该镍层上的金、铅或银材。
7.根据权利要求1所述的半导体封装件，其特征在于，该封装件还包括形成于该通孔中的焊球。
8.一种半导体封装件的制法，其包括：
提供一承载板，于该承载板的表面上定义承载区与邻接该承载区外的延伸区；
形成介电层于该承载板的承载区上，且该介电层具有外露的第一表面、结合至该承载板上的第二表面、及相邻该第一与第二表面的侧面；
形成铜材的线路层于该介电层的第一表面与该承载板延伸区的部分表面上，该线路层具有延伸线路，该延伸线路的两端具有第一接触垫与延伸垫，该第一接触垫形成于该介电层的第一表面上，而该延伸垫形成于该承载板延伸区上；
形成表面处理层于该线路层上；
将半导体芯片设于该介电层的第一表面上且电性连接该表面处理层；
于该承载板与该介电层的第一表面上形成封装胶体，以包覆该半导体芯片与线路层，使该延伸垫位于该介电层侧面与该延伸区上的封装胶体之间；
移除该承载板，以外露出该介电层的第二表面，且令该延伸垫外露于该介电层的第二表面与封装胶体表面；以及
移除部份该延伸垫，以于该介电层侧面与该封装胶体之间形成通孔。
9.根据权利要求8所述的半导体封装件的制法，其特征在于，形成该承载板的材质为铁合金或铜合金。
10.根据权利要求8所述的半导体封装件的制法，其特征在于，形成该线路层与表面处理层的制程，其包括：
形成阻层于该介电层的第一表面与该承载板上，且于该阻层上形成多个第一开口，以外露出该承载板的延伸区及连通该延伸区的介电层部分第一表面；
形成该线路层于该第一开口中；
形成该表面处理层于该线路层上；以及
移除该阻层，以外露该承载板延伸区的部分表面。
11.根据权利要求10所述的半导体封装件的制法，其特征在于，该阻层还形成有第二开口，以外露出该介电层的另一部分第一表面，且该线路层还形成于该第二开口中。
12.根据权利要求11项所述的半导体封装件的制法，其特征在于，该封装件还包括于形成该阻层之前，于该介电层上形成多个开孔，以外露出该承载板的承载区表面，且该阻层的第二开口连通该开孔，而该线路层还形成于该第二开口及开孔中，当移除该承载板后，还包括移除该开孔中的铜材，以外露出线路层的部份表面，以作为第二接触垫。
13.根据权利要求12所述的半导体封装件的制法，其特征在于，该封装件还包括于移除部份该延伸垫时，同时移除部份该第二接触垫，以形成焊球于该开孔中。
14.根据权利要求8所述的半导体封装件的制法，其特征在于，该表面处理层的结构为形成于该线路层上的金层、形成于该金层上的镍层、及形成该镍层上的金、铅或银材。
15.根据权利要求8所述的半导体封装件的制法，其特征在于，该封装件还包括移除该延伸垫的剩余部份，以外露该表面处理层于该通孔中。
16.根据权利要求8所述的半导体封装件的制法，其特征在于，该封装件还包括形成焊球于该通孔中。
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