TW201041465A - Method of fabricating package substrate - Google Patents

Method of fabricating package substrate Download PDF

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Publication number
TW201041465A
TW201041465A TW98114944A TW98114944A TW201041465A TW 201041465 A TW201041465 A TW 201041465A TW 98114944 A TW98114944 A TW 98114944A TW 98114944 A TW98114944 A TW 98114944A TW 201041465 A TW201041465 A TW 201041465A
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TW
Taiwan
Prior art keywords
layer
electrical contact
protective layer
insulating protective
metal
Prior art date
Application number
TW98114944A
Other languages
Chinese (zh)
Other versions
TWI367706B (en
Inventor
Ying-Tung Wang
Original Assignee
Phoenix Prec Technology Corp
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Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW098114944A priority Critical patent/TWI367706B/en
Publication of TW201041465A publication Critical patent/TW201041465A/en
Application granted granted Critical
Publication of TWI367706B publication Critical patent/TWI367706B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of fabricating a package substrate is proposed, including a substrate body having first and second electrical connecting pads formed on at least a surface thereof; a first insulating layer formed with a plurality of openings therein for correspondingly exposing each of the first and second connecting pads therefrom; a resist layer formed on the first insulating protective layer with an opening for exposing first and second electrical connecting pads and the opening of the first insulating protective layer therefrom; a metal layer formed in the opening of the resist layer; first and second metal bumps formed by removing the resist layer and part of the metal layer higher than the surfaces of the first insulating protective layer. The issue of aligning the openings is eliminated by forming a relative large opening in the resist layer, and also the formation of first and second metal bumps by grinding raises the bottoms of the metal bump and strengthens mechanical structures of the first and second connecting pads.

Description

201041465 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種封裝基板之製法，尤指一種電性接 觸墊與金屬凸塊之間具有較佳強度之封裝基板之製法。 【先前技術】 在現行覆晶式（flip chip)半導體封裝技術中，係於半導 體晶片上設有複數電極墊，並在一具有電性接觸墊之封裝 基板上形成位於該電性接觸墊上之金屬凸塊，且藉由焊料 以對應電性連接該些電極墊與金屬凸塊。 相較於傳統的打線接合（Wire Bond)技術，覆晶技術之 特徵在於半導體晶片與封裝基板間的電性連接係藉由金屬 凸塊而非一般之金線，而該種覆晶技術之優點在於能提高 封裝密度以降低封裝元件尺寸，同時，該種覆晶技術不需 使用長度較長之金線，而能提高電性連接的性能以降低阻 抗。 由於越來越多的產品設計趨向小型化，因此，覆晶技 術亦朝向高I/O數、細間距之趨勢發展。然而，隨著絕緣 保護層開孔與金屬凸塊間距（pitch)的縮小，封裝基板的 可靠度與良率不易維持原有的水準。 請參閱第1A至1E圖，係說明一種習知封裝基板之製 法的剖視示意圖。 如第1A圖所示，係提供一基板本體10，其至少一表 面具有複數第一電性接觸墊111、第二電性接觸墊112、及 線路]]3，於該基板本體10、第一電性接觸墊111、第二 4 ]]]]89 201041465 電性接觸墊Π2、及绅牧11<3， 19 " 形成絕緣保護層12,且嗲 2中對應形成有複數外 ： 觸墊111及弟二電性接觸 乐d生接 ,D n 1R m ^ 】2之絶緣保護層開孔120。 弟1B圖所示，於該絕緣保護層】 弟—電性接觸墊⑴上形成導電層13。 Ο Ο 如第1C®心，於料電層13 該阻層Η中形成有複數阻層開孔14二二=且 開孔120及其周圍之導+ @ u ^ & 7各孩名緣保護層 140。 之W層13對應外露出於各該阻層開孔 如第⑴圖所示’藉由該導電層13以分別於 _中之第-電性接_⑴與其周圍之 = 仏及第二電性接觸墊112與其周圍之絕_ 2、= 分別形金屬凸塊⑸及第二金屬凸塊152。上方 如第1E圖所示’移除該阻層14及其所覆蓋之導電層 以露出該些第—金屬凸塊⑸及第二金屬凸塊152。 μ然而’習知之封裳基板之製法中，為了形成該些第一 及弟-金屬凸塊151，152，必須先形成具有複數阻層開孔 140之阻層14，且該些阻層開孔140分別對應至各該第一 電性接觸墊ill及第二電性接觸整112;當形成細間距之 線路設計時，因各該第—電性接觸墊ln、第二電性接觸 墊112及線路113之間的間距縮小，使各該絕緣保護層開 孔120之間距縮小，故於製程中，需縮小該些絕緣二二 開孔120之尺寸。 、叹θ 當縮小各該絕緣保護層開孔120時，易影響後續各哼 111189 201041465 阻層開孔140之對位，而受限於對位精度，各該阻層開孔 140均需大於各該絕緣保護層開孔12()，方能在該絕緣保護 層開孔120中之第-電性接觸& ιη及第二電性接觸塾 112上形成第一金屬凸塊151及第二金屬凸塊152。 因此，各該絕緣保護層開孔12〇均小於各該阻層開孔 14 0，且於進行細間距製程時，該絕緣保護層開孔12 〇將更 為縮小；惟，當縮小該絕緣保護層開孔12〇時，該第一電 性接觸塾111及第二電性接觸墊112相對地縮小露出的: 積，且該絕緣保護層開孔120底部容易殘留物質，例如該 絕緣保護層Π之殘4 ’將導致形成於該絕緣保護層開^ 12〇中的第-及第二金屬凸塊151，152的底部結構有缺 陷’因而不利於細間距線路之形成。 因此，如何提供一種封裝基板之製法，以避免習知技 術中的金屬凸塊底部之機械強度不佳、且絕緣保護層開孔 底部容易殘留物質，而導致整體良率與可靠度下降等問 題’貫已成爲目前業界亟待克服之課題。 【發明内容】 鑑於上述習知技術之缺失，本發明係提供一種封裝基 板之製法，能避免金屬凸塊底部之機械強度不佳、且絕緣 保護層開孔底部容易殘留物質’而導致整體良率與可^度 下降等問題。 、又 為達上述目的及其他目的，本發明揭露一種封装基板 之製法，包括：提供一基板本體，其至少一表面具有複數 第一電性接觸墊、第二電性接觸墊、及線路，該基板=體 1Π]89 6 201041465 係可為已完成前段線路製程之線路板；於該基板本體、第 一電性接觸墊、第二電性接觸墊、及線路上形成第一絕緣 保護層，且該第一絕緣保護層形成複數對應外露出各該第BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a package substrate, and more particularly to a method of fabricating a package substrate having better strength between an electrical contact pad and a metal bump. [Prior Art] In the current flip chip semiconductor packaging technology, a plurality of electrode pads are disposed on a semiconductor wafer, and a metal on the electrical contact pads is formed on a package substrate having an electrical contact pad. The bumps are electrically connected to the electrode pads and the metal bumps by soldering. Compared with the traditional wire bonding technology, the flip chip technology is characterized in that the electrical connection between the semiconductor wafer and the package substrate is by metal bumps instead of the general gold wires, and the advantages of the flip chip technology. In order to increase the package density and reduce the size of the package components, the flip chip technology does not require the use of a long length of gold wire, but can improve the performance of the electrical connection to reduce the impedance. As more and more product designs tend to be miniaturized, flip chip technology is also moving toward high I/O counts and fine pitches. However, as the pitch of the insulating protective layer and the pitch of the metal bumps are reduced, the reliability and yield of the package substrate are not easily maintained at the original level. Referring to Figures 1A through 1E, there are shown schematic cross-sectional views of a conventional method of packaging a substrate. As shown in FIG. 1A, a substrate body 10 is provided, at least one surface having a plurality of first electrical contact pads 111, a second electrical contact pads 112, and a line]]3, the substrate body 10, the first Electrical contact pad 111, second 4]]]]89 201041465 Electrical contact pad Π2, and 绅牧11<3, 19 " The insulating protective layer 12 is formed, and the 嗲2 is formed with a plurality of outer faces: the contact pad 111 And the second electrical contact, the D n 1R m ^ 2 insulation protection layer opening 120. As shown in FIG. 1B, a conductive layer 13 is formed on the insulating protective layer (1). Ο Ο As in the 1C® core, the electrical layer 13 is formed with a plurality of barrier openings 14 and 2 and the opening 120 and its surrounding guides + @ u ^ & 7 Layer 140. The W layer 13 is exposed to the opening of each of the resist layers as shown in the figure (1), by the conductive layer 13 and the first electrical connection _(1) in the _ and the surrounding = and the second electrical The contact pad 112 is formed with a metal bump (5) and a second metal bump 152 respectively. The resist layer 14 and the conductive layer covered thereon are removed as shown in FIG. 1E to expose the first metal bumps (5) and the second metal bumps 152. However, in the conventional method of forming a substrate, in order to form the first and second metal bumps 151 and 152, a resist layer 14 having a plurality of resistive openings 140 must be formed first, and the resist layers are opened. 140 corresponds to each of the first electrical contact pads ill and the second electrical contact 112; when forming a fine pitch circuit design, each of the first electrical contact pads ln, the second electrical contact pads 112 and The spacing between the lines 113 is reduced, so that the distance between the openings 120 of the insulating protection layer is reduced. Therefore, in the process, the size of the insulating apertures 120 needs to be reduced. When squeezing θ, when the openings 120 of the insulating protective layer are reduced, it is easy to affect the alignment of the subsequent opening 111140 of the 41111 201041465 resist layer, which is limited by the alignment accuracy, and each of the resisting openings 140 needs to be larger than each The insulating protective layer opening 12 () can form the first metal bump 151 and the second metal on the first electrical contact & ι and the second electrical contact 塾 112 in the insulating protective layer opening 120 Bump 152. Therefore, each of the insulating protective layer openings 12 〇 is smaller than each of the resist layer openings 14 0 , and the insulating protective layer opening 12 〇 is further reduced when the fine pitch process is performed; however, when the insulating protection is reduced When the layer opening 12 〇, the first electrical contact 塾 111 and the second electrical contact pad 112 are relatively narrowed to be exposed, and the bottom of the insulating protective layer opening 120 is prone to residual substances, such as the insulating protective layer Π The residue 4' will cause the bottom structures of the first and second metal bumps 151, 152 formed in the insulating protective layer opening to be defective', which is disadvantageous for the formation of fine pitch lines. Therefore, how to provide a method for manufacturing a package substrate is to avoid the problem that the mechanical strength of the bottom of the metal bump in the prior art is not good, and the bottom of the opening of the insulating protective layer is liable to leave substances, resulting in a decrease in overall yield and reliability. It has become an urgent issue to be overcome in the industry. SUMMARY OF THE INVENTION In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for manufacturing a package substrate, which can prevent the mechanical strength of the bottom of the metal bump from being poor, and the bottom of the opening of the insulating protective layer is liable to leave a substance, resulting in an overall yield. And the problem can be reduced. The present invention discloses a method for manufacturing a package substrate, comprising: providing a substrate body having at least one surface having a plurality of first electrical contact pads, a second electrical contact pad, and a line, The substrate=body 1Π]89 6 201041465 may be a circuit board that has completed the front-end line process; forming a first insulating protective layer on the substrate body, the first electrical contact pad, the second electrical contact pad, and the line, and The first insulating protective layer forms a plurality of corresponding external exposures

电性接觸蛩及弟一-电性接觸墊之第一絕緣保護層開孔， 該第一絕緣保護層係可由FR—4樹脂、FR-5樹脂、環氧樹 脂（Epoxy )、聚酯樹脂（p0】yesters )、氰脂（Cy姐咖es咐）、 聚乙醯胺（Polyimide)、雙順丁烯二酸醯亞胺/三氮阱（bt， eimide triazme)、或混合環氧樹脂玻璃 如）所製成；於該第_ # '〇laSS 及第二電性接觸 :墓：、4層、弟-爾觸墊、 層，且該阻層㈣層；於該導電層上形成阻 觸墊、第二電性 阻層開孔’以令該些第-電性接 之導電層外露出於絕緣保護層開孔及其周圍上 或貼合之方式张士 s 1，该阻層係可以印刷、旋涂The first insulating protective layer is electrically connected to the first insulating protective layer of the first contact protective layer, and the first insulating protective layer is made of FR-4 resin, FR-5 resin, epoxy resin (Epoxy), polyester resin ( P0]yesters), cyanide (Cy sister es咐), polyimide (Polyimide), bis-succinimide/trinitride (bt, eimide triazme), or mixed epoxy glass Made in the first _ # '〇laSS and the second electrical contact: the tomb:, the 4th layer, the sir-contact pad, the layer, and the resist layer (four) layer; forming a resistive pad on the conductive layer The second electrical resistive opening is formed such that the conductive layer of the first electrically conductive layer is exposed on the opening of the insulating protective layer and the periphery thereof or is attached thereto. The resist layer can be printed. Spin coating

層，形成該金屬=於該阻層開孔中的導電層上形成金i 之導電層、及移除 阻層及其所覆蓋 層及導電層， 纟巴緣保護層之表面的金屬 電性接觸表面該第—絕緣保護層開孔之第-及第二 第-及第二金^上分獅成第-及第二金屬凸塊，且該 讀第二金屬凸塊不高於該第 '絕緣保護層之表面，‘ 部位之表面塊中間部位之表面低於該第二金 屬凸塊周圍 依上述之封裝 晶焊墊以供結合半 黏著墊。 基板之製法， 導體晶片，而 該第一電性接觸墊可為 苐一電性接觸墊可為夺 覆 面 ^1189 7 201041465 依上述之製法，移除高於該第—絕緣保護層之表面的 金屬層及導電層的方法係可為化學機械研磨或刷磨。 又依上述之封裝基板之製法，復可包括於^入 屬凸塊上接置半導體晶片，該半導触曰 "― 至 干¥月豆B日片之一表面罝有複 數電極墊，該些電極塾係藉由焊料以對應電 第二金屬凸塊，，且復可包括於該基板本體與半導體晶= 間形成底充材料’以形成一封裝纟士構。 00 本發明揭露另一種封裴基板之製法，勺 板本體，其至少-表面具有複數第—電^执提供一基 性接觸墊、及線路，該基板本體係可為 、墊、第二電 程之線路板·’於該基板本體、第—带‘、、、元成前段線路製 接觸墊、及線路上形成第—絕緣保接觸墊、第二電性 護層中形成有複數對應外露出各該且該第一絕緣保 電性接觸墊之第一絕緣保護層開孔乐a =性接觸墊及第二 可由FR-4樹脂、FR-5樹脂、環氧樹=弟—絕緣保護層係 脂（P0lyesters)、氰脂（Cyanate L(Epoxy)、聚酉旨樹 ㈤yimide)、雙順丁稀二酸酿亞：:〇:聚乙酿胺 Bismaleimide triazine)、或混八環 '种二虱阱（BT， _所製成·，於該第—絕緣坡墙纖維 及第二電性接觸墊上形成導電居/卑一電性接觸墊、 層，且該阻層中形成有—第—阻曰層開=導電層上形成胆 孔，令该些第一電性接觸墊上、第—+ 複數第二卩且層間 緣保護層開孔上及其周圍上之導C妾觸墊之第1 孔，且令各該第二電性接觸勢上二外露於該第1 且層聞 嘵性接觸墊之第__ 8 201041465 絕緣保護層開孔上及其周圍上之導電層對應外露於該些第 二阻層開孔，該阻層係可以印刷、旋塗或貼合之方式形成； 於該第一阻層開孔中與該些第二阻層開孔中之導電層上形 成金屬層，形成該金屬層的材料可為銅；移除該阻層及其 所覆蓋之導電層；以及移除高於該第一絕緣保護層之表面 的金屬層及導電層，以於各該第一絕緣保護層開孔之第一 及第二電性接觸墊之表面上分別形成第一及第二金屬凸 塊，且該第一及第二金屬凸塊不高於該第一絕緣保護層之 表面，又該第二金屬凸塊中間部位之表面低於該第二金屬 凸塊周圍部位之表面。 依上述之封裝基板之製法，該第一電性接觸墊可為覆 晶焊墊以供結合半導體晶片，而第二電性接觸墊可為表面 黏著墊。 依上述之製法，移除高於該第一絕緣保護層之表面的 金屬層及導電層的方法可為化學機械研磨或刷磨。 又依上述之封裝基板之製法，復可包括於該些第一金 屬凸塊上接置半導體晶片，該半導體晶片之一表面具有複 數電極墊，該些電極墊係藉由焊料以對應電性連接至各該 第一金屬凸塊，且復可包括於該基板本體與半導體晶片之 間形成底充材料，以形成一封裝結構。 由上可知，本發明之封裝基板之製法，主要係於第一 絕緣保護層開孔中之電性接觸墊上形成金屬凸塊時，於該 阻層中形成單一大阻層開孔以取代習知複數小阻層開孔， 藉由該導電層以形成該金屬層，並在移除該阻層及導電層 9 1Π189 201041465 之後進行研磨製程，以於該㈣―及第二電性接觸塾之表 面上分別形成第—及第二金屬凸塊，俾於形成細間距之線 路設計時’不需考量阻層開孔之對位問題，因而可製作較 習知技術更大之第一絕緣保護層開孔，進而提高金屬凸塊 =部之機械強度、並降低第一絕緣保護層開孔中殘留有物 質的機率’以利於細間距之設計。 【實施方式】 以下係#由特定的具體實例言兒明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示 瞭解本發明之其他優點與功效。 I易也 [第一實施例] 法之第2A至2G圖，係為本發明之基板之製 之乐戶'知例的剖視示意圖。 面且：第2A圖所示’首先，提供-基板本體20，其一表 路^數第-電性接觸墊211、第二電性接觸塾2 ==的另一表面可具有第三電性接觸整-， 塾第一電性接觸_、第二電性接觸 上分別形22f 生接觸塾214 緣保错屉π山 巴豕保。隻層22a、22b，且該第一絕 塾2^及第，有複數_外露出各該第一電性接觸 咖，^^=接_212之第―絕緣保護層開孔 各該第三Li二=護層f5中形成有複數對應外露出 於本〜“由：4之弟一絕緣保護層開孔2 2 0 b。 也歹1，所边之基板本體2G係可為已完成前 J0 1Π189 201041465 段線路製程之線路板，即具有内部線路（未於圖式中表 ;該第一及第二絕緣保護層22a、22b係可由FR_4樹 R-5樹脂、環氧樹脂（Epoxy )、聚酯樹脂（P〇lyestfirci、 示） Ο Ο 7 一 I不 5叉 /百厶厶 a ^z-u Ί/Τ' ^ 比？ r 脂、FR-5樹脂、環氧樹脂（Epoxy )、聚g旨樹脂（P〇lyesters )、 氰脂（Cyanate ester)、聚乙醯胺（p〇lyimide )、雙順丁歸 酿亞胺/三氮啡（BT，Bismaleimide triazine)、咬、'p 合環氧樹脂玻璃纖維（Glass fiber)所製成。所述之第一= :接;f2U係可為覆晶焊整，以供結合晶片，而所述: :笔性接㈣212係可為表轉 陡接觸墊214係可Α措m昂二電 ★仔j純球f，以供結合焊球。 性接奶：2B圖所不’於該第-絕緣保護層22a、第 接觸塾2H、及第二電性接觸塾2曰 弟一電 1如第2C圖所示，於該 升)成Η層23。 碴蛆層24形成有—阻# 书g 23上形成阻層24,且 塾川 層開孔240,以人 211上之導電層23、 7 ,玄些弟一電性接觸 23、第—絕緣保護層開孔2；^ _墊加上之導電層 外露於該阻層開孔240; Α巾，▲及其周圍上之導電層23 塗或貼合之方式形成。〃，4版層24係可以印刷、旋 如第2D圖所示，於該阻 上形成金屬層25,而形成該金屬日=24◦中的導電層23 如第2Ε圖所示，移除⑽且層^ 5之材料係可為銅。 ，以露出該金屬層25及部八#及其所覆蓋之導電層 如第2F圖所示，寿多除高於^弟了巴緣保護層22a。 面之金屬層25及導電層23，γ〔弟一絕緣保護層22a表 孔22〇a之第一電性接觸塾a 1 2各該第-絕緣保護層開 昂二電性接觸墊212之表 ΠΠ89 201041465 面上分別形成第一金屬凸塊25丨 一 該第一金屬凸塊⑸及第二金屬凸d屬Π2::，且 緣保護層22a之表面，又該第_ 尚方…亥第一絕 表面係可低於該第二金屬凸塊2 52 2塊2 5 2中間部位之 另外，移除高於該第—絕緣保謨層2°2之表面以呈凹狀； 及導電層23的方法係可為化學機曰&之表面的金屬層25 、如第2G圖所示，於該些第_金屬凸=磨。 導體晶片26，該半導體晶片％之― 251上接置半 27，且該些電極墊27藉由;^具有複數電極墊 第—金屬凸塊⑸，又於該基板讀=電性連接至各該 之間形成底充材料29，俾以 財導體晶片26 [第二實施例] 俾㈣成—封I结構。 請爹閱第3A至3G m 拉去丄 法之第二實施例的剖視示為本發明之封裝基板之製 面I如第3Α圖所示’首先’提供一基板本體20 I > 於該基板本體目2二另一f面具有第三電性接觸墊214,並 212與線路213、及Z =接觸塾211、第-電性接觸塾 分别炉成μ 土反本體20與第三電性接觸墊214上 保及第二絕緣保護層，且該第一絕緣 川及曰裳 形成有複數對應外露出各該第-電性接觸塾 而讀第=電性接觸塾2]2之第一絕緣保護層開孔， 三電性拉表保5隻層22b十形成有複數對應外露出各該第 生墊214之第二絕緣保護層開孔22〇b。 ]]]189 12 201041465 於本實施例中，所述之基板本體20係可為已完成前 段線路製程之線路板，該第一及第二絕緣保護層22a、22b , 係可由FR-4樹脂、FR-5樹脂、環氧樹脂（Epoxy )、聚酯 樹脂（Polyesters )、氰脂（Cyanate ester )、聚乙酿胺 (Polyimide )、雙順丁烯二酸醯亞胺/三氮阱（BT， • Bismaleimide triazine )、或混合環氧樹脂玻璃纖維（Glass .fiber)所製成。所述之第一電性接觸墊211係可為覆晶焊 墊，以供結合晶片，而所述之第二電性接觸墊212係可為 〇 表面黏著墊，且所述之第三電性接觸墊214係可為植球 塾，以供結合焊球。 如第3B圖所示，於該第一絕緣保護層22a、第一電 性接觸墊211、及第二電性接觸墊212上形成導電層23。 如第3C圖所示，於該導電層23上形成阻層24，且 該阻層24形成有一第一阻層開孔241與複數第二阻層開孔 242，令該些第一電性接觸墊211上、第一電性接觸墊211 ζ\ 之第一絕緣保護層開孔220a上及其周圍上之導電層23外 露於該第一阻層開孔241，且令各該第二電性接觸墊212 上之導電層23、第一絕緣保護層開孔220a上及其周圍上 之導電層23對應外露於該些第二阻層開孔242;其中，該 阻層24係可以印刷、旋塗或貼合之方式形成。 如第3D圖所示，於該第一阻層開孔241中之導電層 23上與該些第二阻層開孔242中之導電層23上形成金屬 層25，且形成該金屬層25之材料係可為銅。 如第3E圖所示，移除該阻層24及其所覆蓋之導電層 13 111189 201041465 23，以露出該金屬層25及部分之第一絕緣保護層22a。 如第3F圖所示，移除高於該第一絕緣保護層22a表 面之金屬層25及導電層23,以於各該第一絕緣保護層開 孔220a之第一電性接觸墊211及第二電性接觸墊212之表 面上分別形成第一金屬凸塊251及第二金屬凸塊252，且 該第一金屬凸塊251及第二金屬凸塊252不高於該第一絕 緣保護層22a之表面，又該第二金屬凸塊252中間部位之 表面係可低於該第二金屬凸塊252周圍之表面，以呈凹 狀；另外，移除高於該第一絕緣保護層22a之表面的金屬 層25及導電層23的方法係可為化學機械研磨或刷磨。 如第3G圖所示，於該些第一金屬凸塊251上接置半 導體晶片26,該半導體晶片26之一表面具有複數電極墊 27，且該些電極墊27藉由焊料28以對應電性連接至各該 第一金屬凸塊251，又於該基板本體20與半導體晶片26 之間形成底充材料29，俾以形成一封裝結構。 综上所述，本發明之封裝基板之製法，主要係於該第 一絕緣保護層開孔220a中之第一電性接觸墊211及第二電 性接觸墊212上分別形成該第一金屬凸塊251及第二金屬 凸塊252時，於該第一絕緣保護層22a、第一電性接觸墊 211、及第二電性接觸墊212上先形成導電層23及阻層 24,且該阻層24僅形成單一之大阻層開孔240以取代習知 之複數小阻層開孔，以於該阻層開孔240中之導電層23 上形成金屬層25，並在移除該阻層24及其所覆蓋之導電 層23後，進行研磨製程，以於該第一及第二電性接觸墊 ]4 1Π189 201041465 211,212上形成不高於該第—絕緣保護層22a表面之第一 ，及第二金屬凸塊251，252;相較於習知技術，當形成細間 •距之線路設計時，不需考量該阻層開孔24〇之對位問題， 因而可製作較大之第一絕緣保護層開孔22〇a，令該第一及 第一电性接觸墊211，212露出較大之面積，以增加該第一 .及第二電性接觸墊211,212分別與該第一及第二金屬凸塊 -251，252之接觸面積，俾能提高該第一金屬凸塊251及第 二金屬凸塊252底部分別與第一及第二電性接觸墊 211，212結合之機械強度，且能降低該第一絕緣保護層開 孔220a中殘留物質的機率，俾以利於細間距之設計。 上述實施例僅例示性說明本發明之原理及其功效，而 =用於限制本發明。任何熟習此項技藝之人士均可在不違 月本毛明之精神及範s壽下’對上述實施例進行修倚與改 變。.因此，本發明之權利保護範圍，應如後述之申專 範圍所列。 〇 【圖式簡單說明】 第1A至1E圖 圖； 係為習知之封裝基板之製法的剖視示音 —弟2A至2G圖係為本發明之封裝基板之製法之 實施例之剖視示意圖；以及 —第3A至3G圖係為本發明之封裝基板之製法之 實施例之剖視示意圖。 【主要元件符號說明】 10 Λ 20 基板本體 Π1189 15 201041465 111 ' 211 第一電性接觸墊 112 、 212 第二電性接觸墊 113 > 213 線路 12 絕緣保護層 120 絕緣保護層開孔 13 > 23 導電層 14、24 阻層 140 、 240 阻層開孔 151 ' 251 第一金屬凸塊 152 ' 252 第二金屬凸塊 214 第三電性接觸墊 22a 第一絕緣保護層 220a 第一絕緣保護層開孔 22b 第二絕緣保護層 220b 第二絕緣保護層開孔 241 第一阻層開孔 242 第二阻層開孔 25 金屬層 26 半導體晶片 27 電極塾 28 焊料 29 底充材料a layer, forming the metal = forming a conductive layer of gold i on the conductive layer in the opening of the resist layer, and removing the resist layer, the layer covered by the resist layer and the conductive layer, and the metal electrical contact of the surface of the protective layer of the barrier layer The first and second second and second metal bumps on the surface of the first insulating and insulating layer are divided into the first and second metal bumps, and the read second metal bump is not higher than the first insulating The surface of the protective layer, the surface of the intermediate portion of the surface portion of the portion is lower than the surrounding of the second metal bump according to the above-mentioned packaged crystal pad for bonding the semi-adhesive pad. a method of manufacturing a substrate, a conductor chip, and the first electrical contact pad can be an electrical contact pad, which can be a snaking surface. 1189 7 201041465. According to the above method, the metal above the surface of the first insulating protective layer is removed. The method of layer and conductive layer can be chemical mechanical polishing or brushing. According to the method for manufacturing the package substrate, the semiconductor wafer is connected to the bump, and the surface of one of the semi-conductive contacts is a plurality of electrode pads. The electrode lanthanum is soldered to correspond to the second metal bump, and may be formed between the substrate body and the semiconductor crystal to form an underfill material to form a package gentleman structure. 00. The invention discloses a method for manufacturing a sealing substrate. The spoon plate body has at least a surface having a plurality of electrodes, and a basic contact pad and a circuit. The substrate can be a pad, a second circuit. The circuit board has a plurality of corresponding contact surfaces formed on the substrate body, the first tape, the contact pads, and the first insulating contact pads, and the second electrical protective layer. And the first insulating protective contact layer of the first insulating protective layer opening hole a = sexual contact pad and the second FR-4 resin, FR-5 resin, epoxy tree = brother - insulating protective layer grease (P0lyesters), cyanate (Cyanate L (Epoxy), 酉 树 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( BT, _ formed, forming a conductive/inferior electrical contact pad and layer on the first insulating wall fiber and the second electrical contact pad, and forming a first-resistive layer in the resist layer = forming a bile hole on the conductive layer, so that the first electrical contact pads, the first - second complex second layer and the interlayer edge The first hole of the C-pad of the conductive layer on and around the opening of the sheath, and the second electrical contact potential of the second layer is exposed to the first layer and the layer of the contact pad is __ 8 201041465 The conductive layer on and around the opening of the insulating protective layer is correspondingly exposed to the second resistive layer opening, and the resistive layer can be formed by printing, spin coating or bonding; in the opening of the first resistive layer Forming a metal layer on the conductive layer in the opening of the second resist layer, the material forming the metal layer may be copper; removing the resist layer and the conductive layer covered thereby; and removing the first insulating layer a metal layer and a conductive layer on the surface of the protective layer, respectively forming first and second metal bumps on the surfaces of the first and second electrical contact pads of the first insulating protective layer opening, and the first And the second metal bump is not higher than the surface of the first insulating protective layer, and the surface of the intermediate portion of the second metal bump is lower than the surface of the portion around the second metal bump. According to the method for manufacturing the package substrate, The first electrical contact pad can be a flip chip for bonding a semiconductor wafer, and the second The contact pad may be a surface adhesive pad. According to the above manufacturing method, the method of removing the metal layer and the conductive layer higher than the surface of the first insulating protective layer may be chemical mechanical polishing or brushing. The semiconductor wafer is connected to the first metal bumps, and the surface of one of the semiconductor wafers has a plurality of electrode pads, and the electrode pads are electrically connected to the first metal bumps by soldering. And forming a bottom filling material between the substrate body and the semiconductor wafer to form a package structure. As can be seen from the above, the method for manufacturing the package substrate of the present invention is mainly for the electricity in the opening of the first insulating protective layer. When a metal bump is formed on the contact pad, a single large resist opening is formed in the resist layer to replace the conventional plurality of small resist opening, the conductive layer is used to form the metal layer, and the resist layer is removed. And the conductive layer 9 1 Π 189 201041465 is followed by a grinding process to form the first and second metal bumps on the surface of the (4) and the second electrical contact 俾, respectively, to form a fine pitch line design 'It is not necessary to consider the alignment problem of the barrier opening, so that the first insulating protective layer opening larger than the conventional technology can be made, thereby improving the mechanical strength of the metal bump=section and lowering the first insulating protective layer. The probability of material remaining in the hole 'to facilitate the design of fine pitch. [Embodiment] The following is a specific embodiment of the invention, and those skilled in the art can understand the other advantages and effects of the invention as disclosed in the specification. [Embodiment 1] The 2A to 2G drawings of the method are schematic cross-sectional views of a known example of the substrate of the present invention. And: in FIG. 2A, firstly, the substrate body 20 is provided, and the other surface of the first electrical contact pad 211 and the second electrical contact =2 == may have a third electrical property. Contact the whole -, the first electrical contact _, the second electrical contact on the shape 22f raw contact 塾 214 edge protection drawer π Shanba 豕. Only the layers 22a, 22b, and the first and second layers are provided with a plurality of _ externally exposed to the first electrical contact coffee, and the first - insulating protective layer openings of the ^ _ 212 are respectively the third Li Second = the protective layer f5 is formed with a plurality of corresponding external exposures in this ~ "by: 4 brothers, an insulating protective layer opening 2 2 0 b. Also 歹 1, the side of the substrate body 2G can be completed before J0 1Π 189 The circuit board of the 201041465 segment line process has an internal circuit (not shown in the figure; the first and second insulating protective layers 22a, 22b can be made of FR_4 tree R-5 resin, epoxy resin (Epoxy), polyester Resin (P〇lyestfirci, show) Ο Ο 7 I I not 5 fork / 厶厶 厶厶 a ^zu Ί / Τ ' ^ ratio ? r fat, FR-5 resin, epoxy resin (Epoxy), poly g resin ( P〇lyesters ), Cyanate ester, p〇lyimide, Bis-imine, Bismaleimide triazine, Bite, 'p-epoxy fiberglass (Glass fiber). The first = : connected; f2U can be flip chip soldering for bonding wafers, and:: pen-connected (four) 212 series can be a table-to-steep contact pad 214 can措m 昂二电★仔j pure ball f for bonding solder balls. Sexual milk: 2B is not in the first insulating protective layer 22a, the first contact 塾2H, and the second electrical contact 塾2曰The first electric power 1 is as shown in Fig. 2C, and the enthalpy layer 23 is formed in the 升 layer 24. The 碴蛆 layer 24 is formed with a resist layer 24 formed on the book g 23, and the 塾 层 layer opening 240 is formed on the person 211 The conductive layer 23, 7 , a younger electrical contact 23, the first insulating protective layer opening 2; ^ _ pad plus the conductive layer exposed to the resistive opening 240; wipes, ▲ and its surroundings The conductive layer 23 is formed by coating or bonding. The 版, 4 plate layer 24 can be printed and rotated as shown in FIG. 2D, and the metal layer 25 is formed on the resist to form the conductive in the metal day=24◦. Layer 23, as shown in Figure 2, removes (10) and the material of layer 5 can be copper. To expose the metal layer 25 and the portion of the layer 8 and the conductive layer covered by it, as shown in Figure 2F, In addition to the upper layer of the protective layer 22a, the surface of the metal layer 25 and the conductive layer 23, γ [the first electrical contact of the surface of the insulating layer 22a of the insulating layer 22a, the first electrical contact 塾 a 1 2 each of the first insulating Protective layer of the second electrical contact pad 212 ΠΠ89 201041465 The first metal bumps 25 are formed on the surface, the first metal bumps (5) and the second metal bumps are Π2::, and the surface of the edge protective layer 22a, and the first _ The surface system may be lower than the intermediate portion of the second metal bump 2 52 2 2 2 2 , and the surface higher than 2° 2 of the first insulating layer may be removed to be concave; and the conductive layer 23 The metal layer 25, which may be the surface of the chemical machine, is shown in Fig. 2G, and the first metal protrusion = grinding. The conductor chip 26, the semiconductor wafer % 251 is connected to the half 27, and the electrode pads 27 have a plurality of electrode pad first metal bumps (5), and the substrate is read = electrically connected to each An underfill material 29 is formed therebetween, and the crucible conductor wafer 26 [second embodiment] 俾 (4) is formed into a sealed I structure. Please refer to the third embodiment of the third embodiment of the present invention. The cross-sectional view of the second embodiment of the present invention is shown in FIG. 3 as a first embodiment of the substrate substrate 20 I > The other substrate surface of the substrate body has a third electrical contact pad 214, and 212 and the line 213, and the Z=contact 塾211, the first electrical contact 炉, respectively, are formed into a soil opposite body 20 and a third electrical property. The second insulating protective layer is protected on the contact pad 214, and the first insulating and the first insulating layer are formed with a plurality of first insulating materials respectively exposing the first electrical contact and reading the first electrical contact 2] The protective layer is opened, and the three-electrode pull-tab ensures that the five layers 22b are formed with a plurality of second insulating protective layer openings 22〇b corresponding to each of the first mats 214. In the present embodiment, the substrate body 20 can be a circuit board that has completed the front-end circuit process, and the first and second insulating protective layers 22a, 22b can be made of FR-4 resin. FR-5 resin, epoxy resin (Epoxy), polyester resin (Polyesters), cyanate ester, polyimide, bis-succinimide/trinitrogen trap (BT, • Bismaleimide triazine), or a mixture of epoxy glass fibers (Glass.fiber). The first electrical contact pad 211 can be a flip chip for bonding the wafer, and the second electrical contact pad 212 can be a germanium surface adhesive pad, and the third electrical property The contact pads 214 can be ball bumps for bonding solder balls. As shown in FIG. 3B, a conductive layer 23 is formed on the first insulating protective layer 22a, the first electrical contact pads 211, and the second electrical contact pads 212. As shown in FIG. 3C, a resist layer 24 is formed on the conductive layer 23, and the resist layer 24 is formed with a first resistive opening 241 and a plurality of second resistive openings 242 for the first electrical contact. The conductive layer 23 on the pad 211 and the first insulating protective layer opening 220a of the first electrical contact pad 211 外 is exposed to the first resistive opening 241, and the second electrical property is made. The conductive layer 23 on the contact pad 212, the conductive layer 23 on the first insulating protective layer opening 220a and the periphery thereof are exposed to the second resistive opening 242; wherein the resist layer 24 can be printed and rotated Formed by coating or lamination. As shown in FIG. 3D, a metal layer 25 is formed on the conductive layer 23 in the first resistive opening 241 and the conductive layer 23 in the second resistive opening 242, and the metal layer 25 is formed. The material can be copper. As shown in FIG. 3E, the resist layer 24 and the conductive layer 13 111189 201041465 23 covered therein are removed to expose the metal layer 25 and a portion of the first insulating protective layer 22a. As shown in FIG. 3F, the metal layer 25 and the conductive layer 23 are removed from the surface of the first insulating protective layer 22a to form the first electrical contact pads 211 and the first insulating insulating layer openings 220a. The first metal bump 251 and the second metal bump 252 are respectively formed on the surface of the second electrical contact pad 212, and the first metal bump 251 and the second metal bump 252 are not higher than the first insulating protective layer 22a. The surface of the second metal bump 252 may be lower than the surface of the second metal bump 252 to be concave; in addition, the surface higher than the first insulating protective layer 22a is removed. The method of metal layer 25 and conductive layer 23 may be chemical mechanical polishing or brushing. As shown in FIG. 3G, a semiconductor wafer 26 is mounted on the first metal bumps 251. One surface of the semiconductor wafer 26 has a plurality of electrode pads 27, and the electrode pads 27 are electrically connected by solder 28. Connected to each of the first metal bumps 251, and an underfill material 29 is formed between the substrate body 20 and the semiconductor wafer 26 to form a package structure. In summary, the method for fabricating the package substrate of the present invention is mainly to form the first metal bump on the first electrical contact pad 211 and the second electrical contact pad 212 in the first insulating protective layer opening 220a. The conductive layer 23 and the resist layer 24 are formed on the first insulating protective layer 22a, the first electrical contact pad 211, and the second electrical contact pad 212, and the resistor is formed on the first insulating protective layer 22a, the first electrical contact pad 211, and the second electrical contact pad 212. The layer 24 only forms a single large resistive opening 240 to replace the conventional plurality of small resist opening to form a metal layer 25 on the conductive layer 23 in the resist opening 240 and to remove the resist 24 After the conductive layer 23 is covered, a polishing process is performed to form a first surface of the first and second electrical contact pads 4 1 Π 189 201041465 211, 212 which is not higher than the surface of the first insulating protective layer 22a, and Two metal bumps 251, 252; compared with the prior art, when forming a fine-distance/distance line design, it is not necessary to consider the alignment problem of the barrier layer opening 24, thereby making a larger first insulation The protective layer opening 22〇a exposes the first and first electrical contact pads 211, 212 to a larger area. Increasing the contact area of the first and second electrical contact pads 211, 212 with the first and second metal bumps -251, 252, respectively, to increase the bottom of the first metal bump 251 and the second metal bump 252 The mechanical strength is combined with the first and second electrical contact pads 211, 212, respectively, and the probability of residual substances in the first insulating protective layer opening 220a can be reduced to facilitate the fine pitch design. The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are used to limit the invention. Anyone who is familiar with the art can make modifications and changes to the above embodiments without violating the spirit and the slogan of the moon. Therefore, the scope of protection of the present invention should be as listed in the scope of the application as described later. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1E are cross-sectional views showing a method of fabricating a conventional package substrate. FIG. 2A to FIG. 2G are schematic cross-sectional views showing an embodiment of a method for manufacturing a package substrate of the present invention; And, FIGS. 3A to 3G are schematic cross-sectional views showing an embodiment of a method of manufacturing a package substrate of the present invention. [Main component symbol description] 10 Λ 20 substrate body Π 1189 15 201041465 111 ' 211 first electrical contact pads 112 , 212 second electrical contact pads 113 > 213 circuit 12 insulation protective layer 120 insulation protective layer opening 13 > 23 conductive layer 14, 24 resistive layer 140, 240 resistive opening 151 ' 251 first metal bump 152 ' 252 second metal bump 214 third electrical contact pad 22a first insulating protective layer 220a first insulating protective layer Opening 22b second insulating protective layer 220b second insulating protective layer opening 241 first resistive opening 242 second resistive opening 25 metal layer 26 semiconductor wafer 27 electrode 塾 28 solder 29 underfill material

Claims (1)

201041465 七、申請專利範圍： 1. 一種封裝基板之製法，係包括： 提供一基板本體，其至少一表面具有複數第一電 性接觸墊、第二電性接觸墊、及線路； 於該基板本體、第一電性接觸墊、第二電性接觸 * 墊、及線路上形成第一絕緣保護層，且該第一絕緣保 . 護層中形成有複數對應外露出各該第一電性接觸墊及 第二電性接觸墊之第一絕緣保護層開孔； 〇 於該第一絕緣保護層、第一電性接觸墊、及第二 電性接觸墊上形成導電層； 於該導電層上形成阻層，且該阻層中形成有一阻 層開孔，以令該些第一電性接觸墊上、第二電性接觸 墊上、第一絕緣保護層開孔上及其周圍上之導電層外 露於該阻層開孔； 於該阻層開孔中之導電層上形成金屬層； Q 移除該阻層及其所覆蓋之導電層；以及 移除高於該第一絕緣保護層之表面的金屬層及導 電層，以於各該第一絕緣保護層開孔之第一及第二電 性接觸墊之表面上分別形成第一金屬凸塊及第二金屬 凸塊，且該第一及第二金屬凸塊不高於該第一絕緣保 護層之表面，又該第二金屬凸塊中間部位之表面係低 於該第二金屬凸塊周圍部位之表面。 2. 如申請專利範圍第1項之封裝基板之製法，其中，該 基板本體係為具有内部線路之線路板。 ]7 111189 201041465 3.如申請專利範圍第〗項之封裝基板之製法，其中，該 =一絕緣保護層係由FR_4樹脂、FR_5樹脂、環氧^ 月曰（Epoxy)、聚酿樹脂（p〇lyesters)、氰脂（。⑽攸 =1)、聚乙酿胺（P〇lyimide)、雙順丁稀二酸酸亞胺/ -氮附（BT，Bismaleimide triazine)、或混合環氧樹 脂玻璃纖維（Glass fiber)所製成。 如申請專利範圍第1項之封裝基板之製法 阻層係以印刷、旋塗或貼合之方式形成。 如申請專利範圍第1項之封裝基板之製法 成該金屬層的材料係為銅。 利範圍第1項之封裝基板之製法，其中，該 弟毛性接觸墊係為覆晶焊塾，以供結 如申請糞剎趑円奸， 卞夺版日日片。 :專1項之封裝基板之製法，其中 弟-電性接觸墊係為表面㈣墊。 μ 圍第1項之封裝基板之製法，其中，移 方；传：緣保護層之表面的金屬層及導電層的 方去係為化學機械研磨或刷磨。 h盾的 如申請專利範圍第i 該些第-金屬凸塊上接置半;二包括於 之-表面具有複數電極塾二二丰—體晶片 對應電性連接至各η 極墊1^由焊料以 構。 —金屬凸塊，俾以形成封裝結 1〇·如申請專利範圍第9 該基板本體與半導體 $基板之山去，復包括於 a日曰片之間形成底充材料。 4. 5. 6. 8. 9. 其中，該 其中，形 111]89 18 201041465 ιι· 一種封裝基板之製法，係包括： 提供一基板本體，其至少一表面具有複數第一電 性接觸墊、第二電性接觸墊、及線路； 於該基板本體、第一電性接觸墊、第二電性接觸 墊、及線路上形成第一絕緣保護層，且該第一絕緣保 護層中形成有複數對應外露出各該第一電性接觸墊及 第二電性接觸墊之第一絕緣保護層開孔； 於該第一絕緣保護層、第一電性接觸墊、及第二 電性接觸墊上形成導電層； 於該導電層上形成阻層，且該阻層中形成有一第 一阻層開孔與複數第二阻層開孔，令該些第一電性接 觸墊上、第一電性接觸墊之第一絕緣保護層開孔上及 其周圍上之導電層外露於該第一阻層開孔，且令各該 第二電性接觸墊上、第二電性接觸墊之第一絕緣保護 層開孔上及其周圍上之導電層對應外露出於該些第二 阻層開孔； 於該第一阻層開孔中與該些第二阻層開孔中之導 電層上形成金屬層； 移除該阻層及其所覆蓋之導電層；以及 移除高於該第一絕緣保護層之表面的金屬層及導 電層，以於各該第一絕緣保護層開孔之第一及第二電 性接觸墊之表面上分別形成第一金屬凸塊及第二金屬 凸塊，且該第一及第二金屬凸塊不高於該第一絕緣保 護層之表面，又該第二金屬&塊中間部位之表面隹低 19 ]]]]89 201041465 於該第二金屬凸塊周圍部位之表面。 α如中請專利範_u項之縣基板之製法，其中 基板本體係具有内部線路之線路板。 〇Λ ]3·如中請專利範㈣u奴職練之製法，发中 =絕緣保護層係由叫樹脂、脱樹脂、、: 月曰（咖朴聚酉旨樹脂（Polyesters)、^(c 1Sma〗eimide tnazine)、或混合環 月曰玻璃纖維（Glass fiber)·成。 其中 該 14.如申請專利範圍第11項之封裝基板之製法 阻層係以印刷、旋塗或貼合之方式形成。 其中，形 .如申請專利範圍第11項之封裝基板之製法 成該金屬層的材料係為銅。 其中，該 16·:::專利範圍第11項之封裝基板之製法，具中， 如申覆晶焊塾，以供結合半導體晶片。 申=利视圍弟！】項之封裝基板之製法 弟一笔性接觸墊係為表面黏著墊。 ^ 18·如申請專利範圍第U項之 除高於該第-絕緣保護層法’其中’移 方法係化學機械研磨或刷磨表面的金屬層及導電層的 19. y請專利範圍第n項之封裝基板之製法，復 金4凸塊上接置半導體晶m半 表面具有複數電極墊，且該些電 ： 對應電性連接至各該第—金屬凸塊，俾 Π1Ι89 20 201041465 結構。 20.如申請專利範圍第19項之封裝基板之製法，復包括於 該基板本體與半導體晶片之間形成底充材料。201041465 VII. Patent application scope: 1. A method for manufacturing a package substrate, comprising: providing a substrate body having at least one surface having a plurality of first electrical contact pads, a second electrical contact pad, and a line; Forming a first insulating protective layer on the first electrical contact pad, the second electrical contact pad, and the circuit, and forming a plurality of corresponding first exposed electrical contact pads in the first insulating protective layer And a first insulating protective layer opening of the second electrical contact pad; forming a conductive layer on the first insulating protective layer, the first electrical contact pad, and the second electrical contact pad; forming a resistance on the conductive layer a conductive layer formed on the first electrical contact pad, the second electrical contact pad, the first insulating protective layer opening and the periphery thereof is exposed in the layer a barrier layer opening; forming a metal layer on the conductive layer in the opening of the resist layer; Q removing the resist layer and the conductive layer covered thereon; and removing a metal layer higher than a surface of the first insulating protective layer And conductive layer, Forming a first metal bump and a second metal bump on the surface of the first and second electrical contact pads of the first insulating protective layer opening, and the first and second metal bumps are not higher than the first The surface of the insulating protective layer and the surface of the intermediate portion of the second metal bump are lower than the surface of the portion around the second metal bump. 2. The method of manufacturing a package substrate according to claim 1, wherein the substrate is a circuit board having internal wiring. [7111189] 201041465 3. The method for manufacturing a package substrate according to the scope of the patent application, wherein the = one insulating protective layer is made of FR_4 resin, FR_5 resin, epoxy resin (Epoxy), polystyrene resin (p〇) Lyesters), cyanide (.(10)攸=1), P〇lyimide, bis, bis (Bismaleimide triazine), or mixed epoxy fiberglass Made by (Glass fiber). The method for forming a package substrate as claimed in claim 1 is formed by printing, spin coating or lamination. The method for producing a package substrate according to claim 1 is that the material of the metal layer is copper. The method for manufacturing a package substrate according to Item 1, wherein the hair contact pad is a flip chip solder joint for the purpose of applying for a fecal brake, and the Japanese version of the film is seized. : A method for manufacturing a package substrate, wherein the electrical contact pad is a surface (four) pad. μ The method of manufacturing the package substrate of the first item, wherein the transfer layer; the metal layer on the surface of the edge protective layer and the conductive layer are chemical mechanical polishing or brushing. The h shield is as claimed in the first part of the first metal bump; and the second surface includes a plurality of electrodes. The surface of the body is electrically connected to each of the η pads. To structure. - Metal bumps, 俾 to form a package junction 1 〇 如 如 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 基板 基板4. The method of manufacturing a package substrate, comprising: providing a substrate body having at least one surface having a plurality of first electrical contact pads, wherein: 111] 89 18 201041465 ιι a second electrical contact pad and a circuit; a first insulating protective layer is formed on the substrate body, the first electrical contact pad, the second electrical contact pad, and the line, and the first insulating protective layer is formed with a plurality of Corresponding to the first insulating protective layer opening exposing the first electrical contact pad and the second electrical contact pad; forming on the first insulating protective layer, the first electrical contact pad, and the second electrical contact pad a conductive layer; a resist layer is formed on the conductive layer, and a first resistive opening and a plurality of second resistive openings are formed in the resistive layer, so that the first electrical contact pads and the first electrical contact pads are formed a conductive layer on and around the opening of the first insulating protective layer is exposed to the first resistive opening, and the first insulating protective layer of the second electrical contact pad and the second electrical contact pad are opened. The conductive layer on and around the hole is exposed to the outside Forming a second metal layer; forming a metal layer on the conductive layer in the opening of the first resist layer; and removing the resist layer and the conductive layer covered thereon; Removing a metal layer and a conductive layer higher than a surface of the first insulating protective layer to form first metal bumps on the surfaces of the first and second electrical contact pads of each of the first insulating protective layer openings And the second metal bump, and the first and second metal bumps are not higher than the surface of the first insulating protective layer, and the surface of the second metal & block intermediate portion is reduced by 19]]]]89 201041465 a surface of a portion around the second metal bump. α is the method of manufacturing the substrate of the patent model _u item, wherein the substrate system has a circuit board of internal wiring. 〇Λ ] 3 · For example, please apply for the patent law (4) u slave training, hair in the middle = insulation protective layer is called resin, de-resin,,: Yue Yue (Polyesters), ^ (c 1Sma〗 eimide Tnazine), or a mixed glass fiber (Glass fiber), wherein the method of forming a barrier layer of the package substrate of claim 11 is formed by printing, spin coating or lamination. The method for manufacturing a package substrate according to claim 11 is that the material of the metal layer is copper. The method for manufacturing the package substrate according to item 11 of the patent scope is: Welded soldering, for the purpose of combining semiconductor wafers. Shen = Lishiweidi!] The method of making the substrate of the package is a surface adhesive pad. ^ 18·If the U of the patent application scope is higher than the The first-insulating protective layer method' wherein the 'shifting method is a chemical mechanical polishing or brushing of the surface of the metal layer and the conductive layer 19. y patent method of the nth aspect of the package substrate, the composite 4 bumps on the semiconductor The crystal m half surface has a plurality of electrode pads, and the Electrically: correspondingly electrically connected to each of the first metal bumps, 俾Π1Ι89 20 201041465 structure. 20. The method of manufacturing a package substrate according to claim 19, comprising forming a bottom between the substrate body and the semiconductor wafer Fill the material. 111189111189
TW098114944A 2009-05-06 2009-05-06 Method of fabricating package substrate TWI367706B (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI411362B (en) * 2011-08-09 2013-10-01 Unimicron Technology Corp Coreless package substrate and manufacturing method thereof
TWI555452B (en) * 2014-08-12 2016-10-21 南亞電路板股份有限公司 Circuit board and method for forming the same
TWI703484B (en) * 2019-10-10 2020-09-01 大陸商業成科技（成都）有限公司 Improved insulation protection structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI411362B (en) * 2011-08-09 2013-10-01 Unimicron Technology Corp Coreless package substrate and manufacturing method thereof
TWI555452B (en) * 2014-08-12 2016-10-21 南亞電路板股份有限公司 Circuit board and method for forming the same
TWI703484B (en) * 2019-10-10 2020-09-01 大陸商業成科技（成都）有限公司 Improved insulation protection structure

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