TWI367706B - Method of fabricating package substrate - Google Patents
Method of fabricating package substrateInfo
- Publication number
- TWI367706B TWI367706B TW098114944A TW98114944A TWI367706B TW I367706 B TWI367706 B TW I367706B TW 098114944 A TW098114944 A TW 098114944A TW 98114944 A TW98114944 A TW 98114944A TW I367706 B TWI367706 B TW I367706B
- Authority
- TW
- Taiwan
- Prior art keywords
- package substrate
- fabricating package
- fabricating
- substrate
- package
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW098114944A TWI367706B (en) | 2009-05-06 | 2009-05-06 | Method of fabricating package substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW098114944A TWI367706B (en) | 2009-05-06 | 2009-05-06 | Method of fabricating package substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201041465A TW201041465A (en) | 2010-11-16 |
TWI367706B true TWI367706B (en) | 2012-07-01 |
Family
ID=44996328
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW098114944A TWI367706B (en) | 2009-05-06 | 2009-05-06 | Method of fabricating package substrate |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI367706B (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI411362B (en) * | 2011-08-09 | 2013-10-01 | Unimicron Technology Corp | Coreless package substrate and manufacturing method thereof |
TWI555452B (en) * | 2014-08-12 | 2016-10-21 | 南亞電路板股份有限公司 | Circuit board and method for forming the same |
CN110703949B (en) * | 2019-10-10 | 2022-05-13 | 业成科技(成都)有限公司 | Improved structure for insulation glue protection |
-
2009
- 2009-05-06 TW TW098114944A patent/TWI367706B/en active
Also Published As
Publication number | Publication date |
---|---|
TW201041465A (en) | 2010-11-16 |
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