CN105514081A - 封装结构及其制法 - Google Patents

封装结构及其制法 Download PDF

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CN105514081A
CN105514081A CN201410610235.2A CN201410610235A CN105514081A CN 105514081 A CN105514081 A CN 105514081A CN 201410610235 A CN201410610235 A CN 201410610235A CN 105514081 A CN105514081 A CN 105514081A
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line layer
insulating barrier
encapsulating structure
electronic component
making
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许诗滨
刘智文
吴唐仪
胡书玮
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Phoenix Pioneer Ltd By Share Ltd
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Phoenix Pioneer Technology Co Ltd
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Abstract

本发明提出一种封装结构及其制法，该制法先于一承载板上以电镀方式形成一线路层，再于该线路层上设置一电子元件，之后于该承载板上形成一绝缘层，以令该绝缘层包覆该线路层与该电子元件，最后移除该承载板，所以借由单一线路层的设计，使该线路层的一表面结合电子元件，而另一表面能结合导电元件，以缩短信号传递路径。

Description

封装结构及其制法
技术领域
本发明涉及一种封装结构，尤其涉及一种单层线路层的封装结构及其制法。
背景技术
随着半导体封装技术的发展，于智能手机、平板、网络、笔记本电脑等产品中，半导体装置(Semiconductordevice)已开发出不同的封装型态，例如，球栅阵列式(Ballgridarray，简称BGA)、四方扁平式半导体封装件(Quad-FlatPackage，简称QFP)或四方扁平无导脚式(QuadFlatNonleadPackage，简称QFN)半导体封装件等。
如图1A所示，现有QFP封装结构1包括：承载座10、位于该承载座10周围的多个导脚11、粘接至该承载座10上并以多个焊线120电性连接该导脚11的电子元件12以及包覆该电子元件12、承载座10、焊线120及导脚11的如封装胶体的绝缘层13，且该导脚11凸伸出该绝缘层13。
然而，现有QFP封装结构1的制法中，该承载座10与多个导脚11来自于导线架，所以无法任意布线，亦即限制线路与接点的设计。例如，现有导线架的一排导脚11的总长约占有400um，该承载座10的总长约占有125um，所以已限制该导脚11的I/O数量与长度(pitch)。
此外，于进行封装时，受限于该导线架的固定尺寸与该焊线120的高度，所以现有QFP封装结构1的整体厚度较厚，且难以薄化。
又，现有QFP封装结构1中，受限于该导线架的设计，导致其导脚11的数量少，也就是接点数量少，因而难以实现高接点数量与薄型化的需求。
另外，虽有利用蚀刻金属板制作线路层的方式取代现有导线架，但蚀刻方式受限于蚀刻设备，而无法制作细线路(finetracepitch)，致使无法制作线宽/线距30/30um以下的线路，所以整体结构不仅难以符合薄化需求，且于制程中易发生翘曲(Warpage)。
如图1B所示，现有BGA封装结构1’能在相同单位面积的封装基板上容纳更多输入/输出接点(I/Oconnection)以符合高度集积化(Integration)的晶片所需。所述的封装结构1’包括：于上侧10a与下侧10b具有线路层11a,11b的承载板10’、设于该承载板10’上侧10a并以多个导电凸块120’电性连接该线路层11a的电子元件12、包覆多个导电凸块120’的如底胶的绝缘层13以及设于该承载板10’下侧10b的线路层11b上的如焊球的导电元件14，且该承载板10’中具有电性连接该线路层11a,11b的导电柱100。因此，该电子元件12以打线接合(wirebonding)或覆晶接合(Flipchip)方式电性连接该承载板10’，再于该承载板10’下侧10b的线路层11b植设导电元件14而进行电性外接，以达到高脚数的目的。
然而，现有BGA封装结构1’中，于更高频使用时或高速操作时，因信号传递路径过长(即导电元件14、线路层11a,11b与导电柱100)而无法提升电性表现，以致于该封装结构1’的效能有所限制。
此外，现有BGA封装结构1’需制作至少两层线路层11a,11b与导电柱100(如钻孔制程，且于导通孔内镀上铜材，以作为层与层间的连接)，所以整体结构难以符合薄化需求，且因生产制程复杂、流程长而难以降低制造成本。
又，现有BGA封装结构1’因需制作较多的连接介面(如导电元件14、线路层11a,11b与导电柱100之间)，且需使用各层材质不相同的复合式承载板10’，所以大幅增加制造成本。
另外，因该承载板10’由多层(多种原材料组成)热膨胀系数(thermalexpansioncoefficient，简称CTE)与电性特质不匹配的材质所构成，特别是材料间的CTE不匹配，所以于制程中容易发生翘曲。
因此，如何避免现有技术中的种种缺失，实已成为目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明提供一种封装结构及其制法，以缩短信号传递路径。
本发明的封装结构，包括：一绝缘层，其具有相对的第一表面及第二表面；一线路层，其为以电镀方式形成于该绝缘层中并外露于该第一表面；以及一电子元件，其嵌埋于该绝缘层中并电性连接该线路层。
本发明还提供一种封装结构的制法，其包括：于一承载板上以电镀方式形成一线路层；于该线路层上设置一电子元件，并令该电子元件电性连接该线路层；于该承载板上形成一具有相对的第一表面及第二表面的绝缘层，以包覆该线路层与该电子元件，且该绝缘层通过其第一表面结合至该承载板上；以及移除该承载板，以外露出该线路层与该绝缘层的第一表面。
由上可知，本发明封装结构及其制法，借由单一线路层的设计，使该线路层的一表面结合电子元件，而另一表面结合焊球，以缩短信号传递路径，因而能减少信号损失，所以能提升电气特性。
此外，本发明封装结构仅需制作一层线路层，且无需制作导电柱或导通孔，所以不仅大幅降低封装结构的厚度以符合薄化的需求，且能大幅降低制造成本。
又，本发明封装结构借由单一线路层作为两连接介面，且因需移除该承载板而可使用简易承载板，所以能大幅降低制造成本。
另外，借由移除该承载板，以避免发生翘曲。
附图说明
图1A为现有QFP封装结构的剖视示意图；
图1B为现有BGA封装结构的剖视示意图；以及
图2A至图2F为本发明的封装结构的制法的剖视示意图；其中，图2E’至图2F’为图2E至图2F的另一实施例。
符号说明
1,1’,2,2’封装结构
10承载座
10’,20承载板
10a上侧
10b下侧
100导电柱
11导脚
11a,11b,21线路层
12,22电子元件
120焊线
120’,220导电凸块
13,23绝缘层
14,24导电元件
20a金属材
21a外露表面
210电性接触垫
211导电迹线
23a第一表面
23b第二表面。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附附图所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2F为本发明的封装结构2,2’的制法的剖视示意图。
如图2A及图2B所示，借由图案化制程于一承载板20上电镀或沉积方式形成一线路层21。
于本实施例中，该承载板20为基材，例如铜箔基板或其它板体，并无特别限制。于本实施例中，以两侧具有含铜的金属材20a的铜箔基板，例如含铁或其它金属材质的基板规格作说明。
此外，该线路层21包含多个电性接触垫210与多个导电迹线211。
因此，本发明的制法中，借由电镀或沉积方式制作该线路层21，因而可依需求布线(routable)，所以能制作细线路(finetracepitch)，即制作线宽/线距30/30um以下的线路。
此外，由于可任意布线，亦即线路与接点的设计不受限。例如，若多个电性接触垫210所占的总长400um，可作为两排接点(现有导线架仅能作为一排接点)。
又，该线路层21的设计不受限，所以该电性接触垫210的数量可依需求增加，也就是接点数量多。
如图2C所示，于该线路层21上设置一电子元件22，且该电子元件22电性连接该线路层21。
于本实施例中，该电子元件22为主动元件、被动元件或其二者组合，且该主动元件例如半导体元件(如晶片)，而该被动元件例如电阻、电容及电感。
此外，该电子元件22借由多个导电凸块220以覆晶方式结合并电性连接多个电性接触垫210。
又，于其它实施例中，该电子元件22也可借由多个焊线(图略)的打线方式电性连接多个电性接触垫210。
如图2D所示，于该承载板20上形成一具有相对的第一表面23a及第二表面23b的绝缘层23，以令该绝缘层23包覆该线路层21与该电子元件22，且该绝缘层23借其第一表面23a结合至该承载板20上。
于本实施例中，该绝缘层23以铸模方式(molding)、涂布方式或压合方式形成于该承载板20上，且形成该绝缘层23的材质为铸模化合物(MoldingCompound)、底层涂料(Primer)或如环氧树脂(Epoxy)的介电材料。
此外，于另一实施例中，该电子元件22的上表面亦可外露于该绝缘层23的第二表面23b。
又，于其它实施例中，也可先形成底胶(图略)以包覆多个导电凸块220，再形成该绝缘层23。
如图2E所示，移除全部该承载板20，以外露出该线路层21与该绝缘层23的第一表面23a。
于本实施例中，该线路层21的外露表面21a作为植球垫，且该线路层21的外露表面21a齐平于该绝缘层23的第一表面23a。
于其它实施例中，如图2E’所示若以蚀刻方式移除该金属材20a，会略蚀刻该线路层21的表面，使该线路层21的外露表面21a微凹于该绝缘层23的第一表面23a。
如图2F及图2F’所示，形成多个如焊球的导电元件24于该绝缘层23的第一表面23a上，且多个导电元件24电性连接该线路层21，以借由多个导电元件24堆叠结合其它电子装置(图略)。
于本实施例中，多个导电元件24结合于该线路层21的外露表面21a上。
本发明封装结构2,2’的制法中，借由单一线路层21的设计，使该线路层21的一表面(即结合该导电凸块220)结合该电子元件22，而另一表面(即该外露表面21a)结合多个导电元件24，以缩短信号传递路径，因而能减少信号损失，所以能提升电气特性。
此外，本发明封装结构2,2’仅需制作一层线路层21，且无需制作导电柱，所以不仅大幅降低该封装结构2,2’的整体厚度以符合薄化的需求，且能大幅降低制造成本。
又，本发明封装结构2,2’借由单一线路层21作为两连接介面(如电性接触垫210与外露表面21a)，且因需移除该承载板20而可使用简易结构(如铜箔基板)作为该承载板20，所以能大幅降低制造成本。
另外，借由移除该承载板20，以避免该封装结构2,2’受该承载板20的影响而发生翘曲的问题。
本发明还提供一种封装结构2，包括：一绝缘层23、一线路层21以及一电子元件22。
该绝缘层23具有相对的第一表面23a及第二表面23b，且形成该绝缘层23的材质为铸模化合物、底层涂料或介电材料。
该线路层21为以电镀方式形成于该第一绝缘层23中并外露于该第一表面23a。例如，该线路层21自该绝缘层23的第一表面23a嵌埋于该绝缘层23中，且该线路层21的外露表面21a齐平或低于该绝缘层23的第一表面23a。
该电子元件22嵌埋于该绝缘层23中并电性连接该线路层21。例如，该电子元件22为主动元件、被动元件或其二者组合。
于一实施例中，该线路层21包含多个电性接触垫210与多个导电迹线211，且多个电性接触垫210结合并电性连接该电子元件22。
于一实施例中，该封装结构2还包括多个导电元件24，结合于该绝缘层23的第一表面23a上并电性连接该线路层21。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (13)

1.一种封装结构，其特征在于，包括：
一绝缘层，其具有相对的第一表面及第二表面；
一线路层，其为以电镀方式形成于该绝缘层中并外露于该第一表面；以及
一电子元件，其嵌埋于该绝缘层中并电性连接该线路层。
2.如权利要求1所述的封装结构，其特征在于，该线路层自该绝缘层的第一表面嵌埋于该绝缘层中。
3.如权利要求1所述的封装结构，其特征在于，外露于该绝缘层的第一表面的该线路层的表面齐平或低于该绝缘层的第一表面。
4.如权利要求1所述的封装结构，其特征在于，该线路层包含多个电性接触垫与多个导电迹线，且所述多个电性接触垫结合并电性连接该电子元件。
5.如权利要求1所述的封装结构，其特征在于，该电子元件为主动元件、被动元件或其二者组合。
6.如权利要求1所述的封装结构，其特征在于，该封装结构还包括多个导电元件，结合于该绝缘层的第一表面上并电性连接该线路层。
7.如权利要求1所述的封装结构，其特征在于，形成该绝缘层的材质为铸模化合物、底层涂料或介电材料。
8.一种封装结构的制法，其特征在于，包括：
于一承载板上以电镀方式形成一线路层；
于该线路层上设置一电子元件，并令该电子元件电性连接该线路层；
于该承载板上形成一具有相对的第一表面及第二表面的绝缘层，以包覆该线路层与该电子元件，且该绝缘层通过其第一表面结合至该承载板上；以及
移除该承载板，以外露出该线路层与该绝缘层的第一表面。
9.如权利要求8所述的封装结构的制法，其特征在于，该线路层的表面齐平或低于该绝缘层的第一表面。
10.如权利要求8所述的封装结构的制法，其特征在于，该线路层包含多个电性接触垫与多个导电迹线，且所述多个电性接触垫结合并电性连接该电子元件。
11.如权利要求8所述的封装结构的制法，其特征在于，该电子元件为主动元件、被动元件或其二者组合。
12.如权利要求8所述的封装结构的制法，其特征在于，该制法还包括形成多个导电元件于该绝缘层的第一表面上，并令所述多个导电元件电性连接该线路层。
13.如权利要求8所述的封装结构的制法，其特征在于，形成该绝缘层的材质为铸模化合物、底层涂料或介电材料。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108735611A (zh) * 2017-04-21 2018-11-02 先进科技新加坡有限公司 制作在可布线衬底上的显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102842546A (zh) * 2011-06-23 2012-12-26 矽品精密工业股份有限公司 半导体封装件及其制法
US20130083503A1 (en) * 2011-09-30 2013-04-04 Unimicron Technology Corporation Packaging substrate having a holder, method of fabricating the packaging substrate, package structure having a holder, and method of fabricating the package structure
CN103367180A (zh) * 2012-03-27 2013-10-23 南茂科技股份有限公司 半导体封装结构及其制作方法
CN103715165A (zh) * 2012-10-02 2014-04-09 矽品精密工业股份有限公司 半导体封装件及其制法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US9735113B2 (en) * 2010-05-24 2017-08-15 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming ultra thin multi-die face-to-face WLCSP

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102842546A (zh) * 2011-06-23 2012-12-26 矽品精密工业股份有限公司 半导体封装件及其制法
US20130083503A1 (en) * 2011-09-30 2013-04-04 Unimicron Technology Corporation Packaging substrate having a holder, method of fabricating the packaging substrate, package structure having a holder, and method of fabricating the package structure
CN103367180A (zh) * 2012-03-27 2013-10-23 南茂科技股份有限公司 半导体封装结构及其制作方法
CN103715165A (zh) * 2012-10-02 2014-04-09 矽品精密工业股份有限公司 半导体封装件及其制法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108735611A (zh) * 2017-04-21 2018-11-02 先进科技新加坡有限公司 制作在可布线衬底上的显示面板

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