WO2017113921A1 - 集成无源器件的框架封装结构及其制备方法 - Google Patents

集成无源器件的框架封装结构及其制备方法 Download PDF

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WO2017113921A1
WO2017113921A1 PCT/CN2016/100956 CN2016100956W WO2017113921A1 WO 2017113921 A1 WO2017113921 A1 WO 2017113921A1 CN 2016100956 W CN2016100956 W CN 2016100956W WO 2017113921 A1 WO2017113921 A1 WO 2017113921A1
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metal
layer
dielectric layer
pad
insulating dielectric
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PCT/CN2016/100956
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English (en)
French (fr)
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任晓黎
孙拓北
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深圳市中兴微电子技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49506—Lead-frames or other flat leads characterised by the die pad an insulative substrate being used as a diepad, e.g. ceramic, plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/76—Apparatus for connecting with build-up interconnects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60015—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using plate connectors, e.g. layer, film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads

Definitions

  • the present invention relates to a semiconductor chip packaging technology, and in particular to a frame package structure for integrating a passive device and a method for fabricating the same.
  • the production of integrated circuits can be divided into three phases: integrated circuit design, integrated circuit fabrication, and integrated circuit packaging.
  • the integrated circuit manufacturing factory completes the fabrication of the integrated circuit
  • the integrated circuit chip is completed by the steps of wafer fabrication, forming an integrated circuit, and cutting the wafer.
  • a plurality of pads are disposed on the wafer, so that the chips formed by the wafer cutting can be connected to a carrier outward through the pads.
  • the carrier can be a lead frame or a package substrate.
  • the chip can be connected to the carrier by wire bonding or flip chip bonding, so that the pads of the chip can be connected to the electrical contacts of the carrier to form a chip package structure.
  • a semiconductor package with a lead frame as a chip carrier such as a Quad Flat No-lead Package (QFN), which has a rectangular appearance, a horizontal soldered end at the bottom of the component, and a semiconductor for the center in the center.
  • QFN Quad Flat No-lead Package
  • the die pad of the chip has a metal soldered end that is electrically connected around the die pad.
  • the semiconductor die is mounted on the central die pad, and the connecting wire electrically connects the metal pad on the semiconductor die to the metal soldering end of the lead frame, and then covers the chip with the encapsulant and the bonding wire to form the semiconductor package.
  • the missing device refers to an electronic component that can display its characteristics without requiring an external power supply, mainly including Resistors, inductors, and capacitors, as well as passive filters, resonators, converters, and switches made up of these. These components have many important functions. Such as bias, decoupling, switching noise suppression, filtering, tuning, and circuit termination.
  • an embodiment of the present invention provides a frame package structure and a preparation method thereof for integrating a passive device, and the technical solution thereof is implemented as follows:
  • a frame package structure for an integrated passive device comprising: a die pad, a first insulating dielectric layer disposed under the die pad, and a metal structure disposed under the first insulating dielectric layer a second insulating dielectric layer disposed under the metal structure layer, and at least one conductive pad disposed on a periphery of the die pad; the at least one conductive pad being connected to the second insulating dielectric layer ;
  • the die pad is provided with at least one active chip, and the at least one active chip is electrically connected to the conductive pad.
  • a metal interconnection layer is disposed in the second insulating dielectric layer
  • the metal interconnect layer is electrically connected to the metal structure layer.
  • the metal interconnect layer is electrically connected to the conductive pad.
  • the die pad, the metal structure layer, and the first insulating dielectric layer form a capacitor element, wherein the die pad serves as an upper plate of the capacitor element;
  • the first insulating dielectric layer serves as a dielectric layer of the capacitive element;
  • the metal structural layer serves as a lower plate of the capacitive element.
  • the metal structure layer is disposed as a coil structure to form an inductance element; the metal structure layer is made of a high resistivity material to form a resistance element.
  • the first insulating dielectric layer functions as an insulating layer between the resistive element, the inductive element, and the die pad.
  • the first insulating dielectric layer when used as a dielectric layer of the capacitive element, it is made of silicon nitride Si 3 N 4 or silicon dioxide SiO 2 material;
  • the first insulating dielectric layer is made of polyimide PI or polyparaphenylene benzobisoxazole PBO material as the insulating layer between the resistive element and the inductive element and the die pad .
  • an upper surface of the at least one active chip is provided with a pad end, the pad end is a metal structure and is electrically connected to the at least one active chip internal circuit; at the pad end A metal connection line is disposed between the conductive pad, and an internal circuit of the at least one active chip is electrically connected to the conductive pad.
  • a method for fabricating a frame package structure of an integrated passive device comprising:
  • the lead frame including a die pad and a conductive pad on a periphery of the die pad;
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • PVD physical vapor deposition
  • the electroplating process forms a layer of a metal conductive material, and the metal conductive material is filled into the via hole to be connected to the metal structure layer, and the excess metal conductive material is removed by photolithography etching, and the second insulating medium is removed by photolithography.
  • At least one active chip is disposed on the upper surface of the die pad, and the at least one active chip is electrically connected to the conductive pad.
  • the electrically connecting the at least one active chip to the conductive pad comprises:
  • the pad end being a metal structure and electrically connected to the at least one active chip internal circuit; and the conductive pad at the pad end Metal connection lines are disposed between the disks such that internal circuits of the at least one active chip are electrically connected to the conductive pads.
  • the method further includes:
  • the metal interconnect layer is electrically connected to the conductive pad.
  • the die pad, the metal structure layer, and the first insulating dielectric layer form a capacitor element, wherein the die pad serves as an upper plate of the capacitor element;
  • An insulating dielectric layer serves as a dielectric layer of the capacitive element;
  • the metal structural layer serves as a lower plate of the capacitive element.
  • the method further includes:
  • the metal structure layer is disposed as a coil structure to form an inductance element; and the metal structure layer is made of a high resistivity material to form a resistance element.
  • the first insulating dielectric layer functions as an insulating layer between the resistive element, the inductive element, and the die pad.
  • the first insulating dielectric layer when used as a dielectric layer of the capacitive element, it is made of silicon nitride Si 3 N 4 or silicon dioxide SiO 2 material;
  • the first insulating dielectric layer functions as the resistive element, the inductive component, and the die pad When the insulating layer is between, it is made of polyimide PI or polyparaphenylene benzobisoxazole PBO material.
  • the frame package structure of the integrated passive device of the embodiment of the present invention is made by fabricating a lead frame including a die pad and a conductive pad on the periphery of the die pad; under the die pad Forming a first insulating dielectric layer on the surface; forming a metal conductive material on the lower surface of the first insulating dielectric layer by an electroplating process, removing excess metal material by photolithography and etching to form a metal structural layer; Forming a second insulating dielectric layer by a process of chemical vapor deposition CVD or physical vapor deposition PVD on the lower surface of the metal structural layer; forming a via hole by photolithography on the second insulating dielectric layer, the via hole penetrating The second insulating dielectric layer is in contact with the metal structural layer; on the second insulating dielectric layer on which the via has been formed, a metal conductive material is formed by a plating process, and the metal conductive material is filled into the via hole And connecting to the metal structure layer, removing
  • the frame package structure of the integrated passive device of the embodiment of the present invention a large number of passive components can be integrated by the conventional process on the back surface of the die pad of the frame package structure, and the structure fully utilizes the blank of the back surface of the die pad in the frame package.
  • the area may provide a passive device for the chip in the frame package of the embodiment of the present invention, and may also provide a passive device for other chips in the whole system without adding additional discrete passive components, and the embodiment of the present invention may Effectively increase the integration density of the entire system.
  • the passive device can be connected to the conductive pad of the frame structure through a horizontal metal trace, and electrically connected to the active chip related signal network through the conductive pad, which greatly shortens the active chip and the Signal transmission paths between source devices improve signal integrity.
  • FIG. 1 is a schematic diagram of a frame package structure of an integrated passive device according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic structural view of a lead frame according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural view of a lead frame after forming a first insulating dielectric layer according to an embodiment of the present invention
  • FIG. 4 is a schematic structural view of a metal structure layer formed according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural view of a second insulating dielectric layer after forming an embodiment of the present invention.
  • FIG. 6 is a schematic structural view of a metal interconnect layer after forming an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a frame encapsulation structure of an integrated passive device according to Embodiment 2 of the present invention.
  • FIG. 8 is a schematic diagram of a frame encapsulation structure of an integrated passive device according to Embodiment 3 of the present invention.
  • FIG. 9 is a schematic diagram of a frame package structure of an integrated passive device according to Embodiment 4 of the present invention.
  • the embodiment of the present invention provides a frame package structure and a preparation method thereof, which are integrated with a passive device, and are implemented by the present invention.
  • the frame package structure of the integrated passive device can integrate the passive device and the active chip into the same frame package structure, thereby effectively improving package integration and greatly shortening the signal between the active chip and the passive device.
  • the transmission path improves signal integrity.
  • the frame package structure of the integrated passive device of the embodiment of the invention includes a die pad; at least one conductive pad, the conductive pad is located around the die pad; and a first insulation is formed on the lower surface of the die pad a dielectric layer; a metal structure layer formed on a lower surface of the first insulating dielectric layer; a second insulating dielectric layer formed on a lower surface of the metal structural layer; and a metal interconnection layer formed in the second insulating dielectric layer; At least one active chip is disposed on the upper surface of the die pad, and the upper surface of the active chip is provided with a pad end, and the active chip may be electrically connected to the conductive pad by metal wire bonding.
  • the die pad can serve as a support for the active chip, and the heat sink of the package system can also serve as an upper plate of the capacitor element; the conductive pad can connect the chip pin to the external pin of the package body.
  • the first insulating dielectric layer can serve as a dielectric layer of the capacitor element, or can serve as an insulating layer between the resistor and the inductor component and the die pad; the metal structure layer can serve as a lower plate of the capacitor component, or Forming the coil structure as the inductance element, the resistance element can also be formed of a high resistivity material; the metal interconnection layer can be electrically connected to the metal structure layer through the via hole, thereby connecting the passive device pin to the conductive pad The passive device pins can also be led out to the outside of the package; the pad ends are metal structures and are electrically interconnected with the internal circuit structure of the active chip.
  • the capacitive element formed by the die pad, the first insulating dielectric layer and the metal structural layer, and the inductor and the resistive component formed by the special structural structure of the metal structural layer may be referred to as passive components.
  • Step one providing a lead frame, the lead frame comprising a die pad and a conductive pad on a periphery of the die pad;
  • Step 2 forming a first insulating dielectric layer on the lower surface of the die pad, and the first insulating layer is formed by a process such as chemical vapor deposition CVD, physical vapor deposition PVD, or the like;
  • Step 3 forming a metal conductive material on the lower surface of the first insulating dielectric layer by an electroplating process, and then removing an unnecessary metal material by a photolithography, etching process or the like to form a metal structural layer, the metal structure
  • the shape of the layer may be a metal plane arranged in an array in a horizontal direction as a lower plate of the capacitor element, a coil structure to constitute an inductor element, or a plane of a high-resistivity conductive material to constitute a resistor element;
  • Step 4 forming a second insulating dielectric layer on a lower surface of the metal structural layer, and the second insulating dielectric layer may be formed by a process such as CVD, PVD, or the like;
  • Step 5 forming a via hole by photolithography on the second insulating dielectric layer, the via hole penetrating the second insulating dielectric layer and contacting the metal conductive material of the metal structural layer, and then forming the via hole
  • a layer of metal conductive material is covered by a process such as electroplating, and the metal conductive material is filled into the via hole and connected with the metal conductive material of the metal structure layer, and finally Removing an unnecessary metal material by photolithography etching to form a metal interconnection layer on an upper surface of the second insulating medium;
  • Step 6 placing an active chip on the upper surface of the die pad, the upper surface of the active chip is provided with a pad end, and the pad end is a metal structure and is electrically interconnected with the internal circuit structure of the chip.
  • a metal bonding wire is formed between the pad end of the upper surface of the active chip and the lead frame conductive pad, thereby electrically connecting the internal circuit of the active chip and the conductive pad.
  • a frame package structure of an integrated passive device includes a die pad 102 and at least one conductive pad 101. a first insulating dielectric layer 103, a metal structural layer 104, a second insulating dielectric layer 105, and a metal interconnect layer 106, wherein the die pad 102 is a conductive metal material, and the die pad 102 can serve as an active chip.
  • the heat sink of the frame package structure of the integrated passive device of the embodiment of the present invention may also serve as an upper plate of the capacitor element; the conductive pad 101 is located around the die pad 102, and the conductive pad 101 is a conductive metal material, the pin of the active chip is connected to the external pin of the frame package structure of the integrated passive device of the embodiment of the present invention; a first insulating dielectric layer 103 is formed on the lower surface of the die pad 102,
  • the first insulating dielectric layer 103 may be made of a high dielectric constant dielectric material such as silicon nitride Si 3 N 4 or silicon dioxide SiO 2 as a dielectric layer of a capacitive element, and the first insulating dielectric layer 103 may also be made of a polyacyl group.
  • the metal structure layer 104 may be one or more metal planar structures placed in the same plane as the lower plate of the capacitor element, or may form a coil structure as the inductance element, and may also form a resistance element for the material of high resistivity; Forming a second insulating dielectric layer 105 on a lower surface of the metal structural layer 104, the second insulating dielectric layer 105 may be a non-conductive material such as an organic polymer; forming a metal interconnect layer in the second insulating dielectric layer 105 106.
  • the metal interconnect layer 106 can be electrically connected to the metal structure layer 104 through a metal conductive material in the via 107.
  • the metal interconnect layer 106 can connect the passive device to the conductive pad 101, thereby
  • the signals related to the active chip 201 are electrically connected, and the passive device may be taken out to the frame package structure of the integrated passive device of the embodiment of the present invention to be connected to other external chips;
  • At least one active chip 201 is disposed on the upper surface of the die pad 102.
  • the upper surface of the active chip 201 is provided with a pad end 202.
  • the pad end 202 is a metal structure and an internal circuit structure of the active chip 201. Electrically interconnected, the active chip 201 can be electrically connected to the conductive pad 101 by metal wire bonding.
  • the pad end 202 is a metal structure and is electrically connected to the internal circuit of the active chip 201; a metal connection line is disposed between the pad end 202 and the conductive pad 101, so that the internal circuit of the active chip 201 It is electrically connected to the conductive pad 101.
  • the capacitor element formed by the die pad 102, the first insulating dielectric layer 103 and the metal structure layer 104, the inductance component, the resistance component, the capacitor component, and the resistance component formed by the special structure of the metal structure layer 104 are both called Passive components.
  • the embodiment of the invention also describes a method for preparing a frame package structure with integrated passive components, comprising the following steps:
  • Step 1 As shown in FIG. 2, a lead frame is provided, the lead frame including a die pad 102 and a conductive pad 101 on the periphery of the die pad.
  • the die pad 102 and the conductive pad 101 are both formed of a conductive metal material;
  • Step two shown in Figure 3, the die in the first insulating dielectric layer 103 is formed under the pad surface 102, the first dielectric insulating layer 103 is formed by PVD, CVD and other deposition processes, the material may be Si 3 A high dielectric constant medium such as N 4 or SiO 2 is used as a dielectric layer of the capacitor element, and an organic polymer such as PI or PBO may be used as an insulating layer between the resistor and the inductor element and the die pad 102;
  • Step 3 as shown in FIG. 4, a metal conductive material is formed on the lower surface of the first insulating dielectric layer 103 by an electroplating process, and the metal conductive material may be copper (CU), aluminum (Al), or silver (Ag).
  • Low-resistivity conductive materials such as gold (Au) constitute a capacitor lower plate and an inductor element,
  • the resistive element can be made of a high resistivity material such as a nickel-chromium alloy or a tantalum nitride.
  • the excess metal material is removed by a photolithography process, an etching process, or the like to form a metal structure layer 104, and the metal structure layer 104 may have a metal plane arranged in an array in a horizontal direction as a lower plate of the capacitor element. Therefore, the first insulating dielectric layer 103 and the die pad 102 together form a capacitive element, and may also be a coil structure to constitute an inductance element, or may be a high-resistivity conductive material plane to constitute a resistive element, the capacitor, the inductor, and the resistive element. Can be called passive devices.
  • Step 4 as shown in FIG. 5, a second insulating dielectric layer 105 is formed on the lower surface of the metal structural layer 104, and the second insulating dielectric layer 105 may be subjected to chemical vapor deposition (CVD) or physical vapor deposition (PVD). And a process deposition is formed, the insulating dielectric material of the second insulating dielectric layer 105 covers the metal structural layer 104, and is filled in the gap between the metal materials of the metal structural layer 104;
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • Step 5 as shown in FIG. 6, a via 107 is formed on the second insulating dielectric layer 105 by photolithography, and the via 107 penetrates the second insulating dielectric layer 105 and is partially metal conductive material with the metal structural layer 104.
  • a layer of metal conductive material is covered by a process such as electroplating, and the metal conductive material is filled into the via 107, and the metal is electrically conductive with the metal structure layer 104.
  • the material is connected, and finally the excess metal material is removed by photolithography etching to form a metal interconnection layer 106 on the upper surface of the second insulating dielectric layer 105, and the metal interconnection layer 106 can connect the passive device pins to
  • the conductive pad 101 is electrically connected to the signal related to the active chip 201, and the passive device pin can be taken out to the frame package structure of the integrated passive device of the embodiment of the present invention, thereby interacting with other external chips. connection;
  • an active chip 201 is disposed on the upper surface of the die pad 102 , and the upper surface of the active chip 201 is provided with a pad end 202 , and the pad end 202 is a metal structure and The internal circuit structure of the active chip 201 is electrically interconnected. Forming a metal bonding wire between the pad end 202 of the upper surface of the active chip 201 and the lead frame conductive pad 101, thereby implementing electrical connection between the internal circuit of the active chip 201 and the conductive pad 101;
  • the metal interconnection layer 106 formed on the lower surface of the second insulating dielectric layer 105 may be a multilayer metal interconnection structure by the method shown in the fifth step of the preparation method of the present invention, thereby An interconnect that meets higher density signals.
  • the frame package structure of the integrated passive device of the embodiment of the present invention a large number of passive components can be integrated by the conventional process on the back surface of the die pad of the frame package structure, and the structure fully utilizes the blank of the back surface of the die pad in the frame package.
  • the area may provide a passive device for the chip in the frame package of the embodiment of the present invention, and may also provide a passive device for other chips in the whole system without adding additional discrete passive components, and the embodiment of the present invention may Effectively increase the integration density of the entire system.
  • the passive device can be connected to the conductive pad of the frame structure through a horizontal metal trace, and electrically connected to the active chip related signal network through the conductive pad, which greatly shortens the active chip and the Signal transmission paths between source devices improve signal integrity.
  • a large number of passive components can be integrated by a conventional process on the back surface of the die pad of the frame package structure, and the structure fully utilizes the blank area on the back surface of the die pad in the frame package, which can be implemented for the present invention.
  • Chips in the frame package of the example provide passive components, It is also possible to provide passive components for other chips in the entire system without adding additional discrete passive components, and embodiments of the present invention can effectively increase the integration density of the entire system.
  • the passive device can be connected to the conductive pad of the frame structure through a horizontal metal trace, and electrically connected to the active chip related signal network through the conductive pad, which greatly shortens the active chip and the Signal transmission paths between source devices improve signal integrity.

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Abstract

一种集成无源器件的框架封装结构及其制备方法，集成无源器件的框架封装结构包括：裸片垫（102），设置于裸片垫下方的第一绝缘介质层（103），设置于第一绝缘介质层下方的金属结构层（104），设置于金属结构层下方的第二绝缘介质层（105），以及，设置于裸片垫外围的至少一个导电焊盘（101）；至少一个导电焊盘与第二绝缘介质层连接；裸片垫上设置有至少一个有源芯片（201），至少一个有源芯片与导电焊盘电连接。

Description

集成无源器件的框架封装结构及其制备方法 技术领域
本发明涉及半导体芯片封装技术，尤其涉及一种集成无源器件的框架封装结构及其制备方法。
背景技术
在半导体产业中，集成电路的生产主要可分为三个阶段：集成电路设计、集成电路制作以及集成电路封装。在集成电路设计完成后，交由集成电路生产工厂完成集成电路制作，集成电路芯片由晶圆制作、形成集成电路以及切割晶圆等步骤完成。当晶圆内部的集成电路制作完成之后，再在晶圆上配置多个焊垫，以使最终由晶圆切割所形成的芯片可经由这些焊垫向外点连接于一承载器。承载器可以为一引线框架或者一封装基板。芯片可以打线接合或者覆晶接合的方式连接至承载器上，使得芯片的这些焊垫可以连接于承载器的电接触点，从而构成芯片封装结构。
以引线框架为芯片承载件的半导体封装，例如方形扁平无引脚封装(QFN，Quad Flat No-lead Package)，其外观多为矩形，元件底部具有水平焊端，在中央有一个用来放置半导体芯片的裸片垫，围绕裸片垫的四周有实现电气连接的金属焊端。半导体裸片安装在中央的裸片垫上，并且连接线将半导体裸片上的金属焊盘电性连接至引线框架的金属焊端，然后以封装胶体包覆所述芯片以及接合引线而形成半导体封装件。
在电子系统中，除了有源的集成电路芯片外，还会用到大量的无源器件，所述无缘器件是指在不需要外加电源的条件下，就可以显示其特性的电子元件，主要包括电阻类，电感类和电容类器件，以及由这些所组成的无源滤波器、谐振器、转换器和开关等。这些元件具有很多重要的功能， 如偏置、去耦、开关噪声抑制、滤波、调谐和电路终端等。
随着网络通讯、电子多媒体产品以及信息化、智能化技术快速发展，集成电路元器件的处理功能日趋重要，并越来越向着小型化、薄型化、集成化、高密度等态势发展，因而有源芯片与无源器件的高密度集成技术面临机遇和挑战。然而现有的框架封装在很多情况下，在系统中都是与分立的无源器件通过电路板走线相连接，从而导致集成度非常低，封装体内空间也没有被有效利用，而过长的电路板走线也会为系统引入更多的信号完整性问题。如何充分利用封装体内的空间，有效地提高框架封装器件的集成密度和整个集成系统的信号传输质量是目前框架封装技术的一个重要课题。
发明内容
为解决上述技术问题，本发明实施例提供了一种集成无源器件的框架封装结构及其制备方法，其技术方案是这样实现的：
一种集成无源器件的框架封装结构，所述框架封装结构包括：裸片垫，设置于所述裸片垫下方的第一绝缘介质层，设置于所述第一绝缘介质层下方的金属结构层，设置于所述金属结构层下方的第二绝缘介质层，以及，设置于所述裸片垫外围的至少一个导电焊盘；所述至少一个导电焊盘与所述第二绝缘介质层连接；
所述裸片垫上设置有至少一个有源芯片，所述至少一个有源芯片与所述导电焊盘电连接。
作为一种实现方式，所述第二绝缘介质层中设置有金属互连层；
所述金属互连层与所述金属结构层电连接。
作为一种实现方式，所述金属互连层与所述导电焊盘电连接。
作为一种实现方式，所述裸片垫、所述金属结构层以及所述第一绝缘介质层形成电容元件，其中，所述裸片垫作为所述电容元件的上极板；所 述第一绝缘介质层作为所述电容元件的介质层；所述金属结构层作为所述电容元件的下极板。
作为一种实现方式，所述金属结构层设置为线圈结构而形成电感元件；所述金属结构层采用高电阻率的材料，而形成电阻元件。
作为一种实现方式，所述第一绝缘介质层作为所述电阻元件、所述电感元件与所述裸片垫之间的绝缘层。
作为一种实现方式，所述第一绝缘介质层作为所述电容元件的介质层时，由氮化硅Si3N4或二氧化硅SiO2材料制成；
所述第一绝缘介质层作为所述电阻元件、所述电感元件与所述裸片垫之间的绝缘层时，由聚酰亚胺PI或聚对苯撑苯并二噁唑PBO材料制成。
作为一种实现方式，所述至少一个有源芯片的上表面设置有焊盘端，所述焊盘端为金属结构且与所述至少一个有源芯片内部电路电连接；在所述焊盘端与所述导电焊盘之间设置金属连接线，所述至少一个有源芯片的内部电路与所述导电焊盘电连接。
一种集成无源器件的框架封装结构的制备方法，所述方法包括：
制作引线框架，所述引线框架包括裸片垫和位于裸片垫外围的导电焊盘；
在所述裸片垫下表面设置第一绝缘介质层；
在所述第一绝缘介质层下表面通过电镀工艺形成一层金属导电材料，通过光刻、刻蚀工艺去除多余的金属材料，而形成金属结构层；
在所述金属结构层的下表面通过化学气相沉积(CVD，Chemical Vapor Deposition)、物理气相沉积(PVD，Physical Vapor Deposition)的工艺淀积形成第二绝缘介质层；
在所述第二绝缘介质层上通过光刻形成过孔，所述过孔穿透所述第二绝缘介质层而与金属结构层接触；在已形成过孔的第二绝缘介质层上，通 过电镀工艺形成一层金属导电材料，并使所述金属导电材料填充到所述过孔内而与金属结构层连接，通过光刻刻蚀去除多余的金属导电材料，而在第二绝缘介质的上表面形成金属互连层；
在所述裸片垫上表面设置至少一个有源芯片，并使所述至少一个有源芯片与所述导电焊盘电连接。
作为一种实现方式，所述使所述至少一个有源芯片与所述导电焊盘电连接，包括：
在所述至少一个有源芯片的上表面设置焊盘端，使所述焊盘端为金属结构且与所述至少一个有源芯片内部电路电连接；在所述焊盘端与所述导电焊盘之间设置金属连接线，使所述至少一个有源芯片的内部电路与所述导电焊盘电连接。
作为一种实现方式，所述方法还包括：
使所述金属互连层与所述导电焊盘电连接。
作为一种实现方式，所述裸片垫、所述金属结构层以及所述第一绝缘介质层形成电容元件，其中，所述裸片垫作为所述电容元件的上极板；所述第一绝缘介质层作为所述电容元件的介质层；所述金属结构层作为所述电容元件的下极板。
作为一种实现方式，所述方法还包括：
使所述金属结构层设置为线圈结构而形成电感元件；使所述金属结构层采用高电阻率的材料，而形成电阻元件。
作为一种实现方式，所述第一绝缘介质层作为所述电阻元件、所述电感元件与所述裸片垫之间的绝缘层。
作为一种实现方式，所述第一绝缘介质层作为所述电容元件的介质层时，由氮化硅Si3N4或二氧化硅SiO2材料制成；
所述第一绝缘介质层作为所述电阻元件、所述电感元件与所述裸片垫 之间的绝缘层时，由聚酰亚胺PI或聚对苯撑苯并二噁唑PBO材料制成。
本发明实施例的集成无源器件的框架封装结构由下述方式制成：制作引线框架，所述引线框架包括裸片垫和位于裸片垫外围的导电焊盘；在所述裸片垫下表面设置第一绝缘介质层；在所述第一绝缘介质层下表面通过电镀工艺形成一层金属导电材料，通过光刻、刻蚀工艺去除多余的金属材料，而形成金属结构层；在所述金属结构层的下表面通过化学气相沉积CVD、物理气相沉积PVD的工艺淀积形成第二绝缘介质层；在所述第二绝缘介质层上通过光刻形成过孔，所述过孔穿透所述第二绝缘介质层而与金属结构层接触；在已形成过孔的第二绝缘介质层上，通过电镀工艺形成一层金属导电材料，并使所述金属导电材料填充到所述过孔内而与金属结构层连接，通过光刻刻蚀去除多余的金属导电材料，而在第二绝缘介质的上表面形成金属互连层；在所述裸片垫上表面设置至少一个有源芯片，并使所述至少一个有源芯片与所述导电焊盘电连接。本发明实施例的集成无源器件的框架封装结构中，可以在框架封装结构的裸片垫背面通过常规工艺集成大量的无源器件，这种结构充分利用了框架封装中裸片垫背面的空白区域，可以为本发明实施例的框架封装体中的芯片提供无源器件，还可以为整个系统中的其他芯片提供无源器件，而不需要增加额外的分立无源器件，本发明实施例可以有效提高整个系统的集成密度。同时，无源器件可以通过一层水平方向的金属走线连接到框架结构的导电焊盘上，通过导电焊盘与有源芯片相关信号网络进行电性连接，极大地缩短了有源芯片与无源器件之间的信号传输路径，提高了信号完整性。
附图说明
图1为本发明实施例一的集成无源器件的框架封装结构示意图；
图2为本发明实施例的引线框架结构示意图；
图3为本发明实施例的引线框架形成第一绝缘介质层后的结构示意图；
图4为本发明实施例的形成金属结构层后的结构示意图；
图5为本发明实施例的形成第二绝缘介质层后的结构示意图；
图6为本发明实施例的形成金属互连层后的结构示意图；
图7为本发明实施例二的集成无源器件的框架封装结构示意图；
图8为本发明实施例三的集成无源器件的框架封装结构示意图；
图9为本发明实施例四的集成无源器件的框架封装结构示意图。
具体实施方式
为了能够更加详尽地了解本发明的特点与技术内容，下面结合附图对本发明的实现进行详细阐述，所附附图仅供参考说明之用，并非用来限定本发明。
为了解决现有框架封装技术中有源芯片与无源器件集成度不够高，电性能损耗大的问题，本发明实施例提供一种集成无源器件的框架封装结构及其制备方法，本发明实施例的集成无源器件的框架封装结构可以将无源器件与有源芯片集成到同一框架封装结构中，从而有效提高了封装集成度，极大地缩短了有源芯片与无源器件之间的信号传输路径，提高了信号完整性。
具体地，本发明实施例的集成无源器件的框架封装结构包括裸片垫；至少一个导电焊盘，所述导电焊盘位于裸片垫四周；在所述裸片垫下表面形成第一绝缘介质层；在所述第一绝缘介质层下表面形成金属结构层；在所述金属结构层下表面形成第二绝缘介质层；在所述第二绝缘介质层中形成金属互连层；在所述裸片垫的上表面放置至少一个有源芯片，所述有源芯片上表面设置有焊盘端，所述有源芯片可以通过金属打线的方式与导电焊盘进行电连接。
所述裸片垫可以作为有源芯片的支撑体，封装系统的散热体，还可以作为电容元件的上极板；所述导电焊盘可将芯片管脚与封装体外部管脚相 连接；所述第一绝缘介质层可以作为电容元件的介质层，也可以作为电阻、电感元件与裸片垫之间的绝缘层；所述金属结构层可以作为电容元件的下极板，也可以形成线圈结构作为电感元件，还可以为高电阻率的材料形成电阻元件；所述金属互连层可以通过过孔与金属结构层进行电连接，从而将无源器件管脚连接到导电焊盘上，也可以将无源器件管脚引出到封装体外；所述焊盘端为金属结构且与有源芯片内部电路结构电性互连。
所述裸片垫、第一绝缘介质层以及金属结构层所形成的电容元件，金属结构层通过特殊物理结构形成的电感、电阻元件均可称为无源器件。
本发明实施例的集成无源器件的框架封装结构的制备方法，包括以下步骤：
步骤一，提供引线框架，所述引线框架包括裸片垫和位于裸片垫外围的导电焊盘；
步骤二，在所述裸片垫下表面形成第一绝缘介质层，所述第一绝缘层通过化学气相沉积CVD、物理气相沉积PVD等工艺淀积形成；
步骤三，在所述第一绝缘介质层下表面通过电镀工艺形成一层金属导电材料，然后通过光刻、刻蚀工艺等工艺去除不需要的金属材料，从而形成金属结构层，所述金属结构层的形状可以为水平方向呈阵列排布的金属平面作为电容元件的下极板，也可以为线圈结构从而构成电感元件，还可以为高电阻率导电材料平面从而构成电阻元件；
步骤四，在所述金属结构层的下表面形成第二绝缘介质层，所述第二绝缘介质层可以通过CVD、PVD等工艺淀积形成；
步骤五，在所述第二绝缘介质层上通过光刻形成过孔，所述过孔穿透第二绝缘介质层并与金属结构层部分金属导电材料相接触，然后在已形成过孔的第二绝缘介质层上，通过电镀等工艺覆盖一层金属导电材料，并且该金属导电材料填充到过孔内，与金属结构层的金属导电材料连接，最后 通过光刻刻蚀去除掉不需要的金属材料，从而在第二绝缘介质的上表面形成金属互连层；
步骤六，在所述裸片垫上表面放置有源芯片，所述有源芯片上表面设置有焊盘端，所述焊盘端为金属结构且与芯片内部电路结构电性互连。在有源芯片上表面的焊盘端与引线框架导电焊盘之间形成金属键合线，从而实现有源芯片内部电路与导电焊盘的电性连接。
以下结合附图，对本发明实施例的技术方案的实质作进一步阐述。
图1为本发明实施例的集成无源器件的框架封装结构示意图，如图1所示，本发明实施例的集成无源器件的框架封装结构包括裸片垫102，至少一个导电焊盘101，第一绝缘介质层103，金属结构层104，第二绝缘介质层105以及金属互连层106，其中，所述裸片垫102为导电金属材料，所述裸片垫102可以作为有源芯片的支撑体，本发明实施例的集成无源器件的框架封装结构的散热体，还可以作为电容元件的上极板；所述导电焊盘101位于裸片垫102四周，所述导电焊盘101为导电金属材料，可将有源芯片的管脚与本发明实施例的集成无源器件的框架封装结构的外部管脚相连接；在所述裸片垫102下表面形成第一绝缘介质层103，所述第一绝缘介质层103可以由氮化硅Si3N4或二氧化硅SiO2等高介电常数介质材料作为电容元件的介质层，所述第一绝缘介质层103也可以由聚酰亚胺(PI)或聚对苯撑苯并二噁唑(PBO)等有机聚合物材料作为电阻、电感元件与裸片垫102之间的绝缘层；在所述第一绝缘介质层103下表面形成金属结构层104，所述金属结构层104可以为一个或者多个在同一平面放置的金属平面结构作为电容元件的下极板，也可以形成线圈结构作为电感元件，还可以为高电阻率的材料形成电阻元件；在所述金属结构层104下表面形成第二绝缘介质层105，所述第二绝缘介质层105可以为有机聚合物等不导电材料；在所述第二绝缘介质层105中形成金属互连层106，所述金属互连层106可以 通过过孔107内的金属导电材料与金属结构层104进行电连接，所述金属互连层106可以将无源器件连接到导电焊盘101上，从而与有源芯片201相关信号进行电连接，也可以将无源器件引出到本发明实施例的集成无源器件的框架封装结构外，从而与其他外部芯片相连；在所述裸片垫102的上表面放置至少一个有源芯片201，所述有源芯片201上表面设置有焊盘端202，所述焊盘端202为金属结构且与有源芯片201内部电路结构电性互连，所述有源芯片201可以通过金属打线的方式与导电焊盘101进行电连接。具体地，焊盘端202为金属结构且与有源芯片201内部电路电连接；在所述焊盘端202与所述导电焊盘101之间设置金属连接线，使有源芯片201的内部电路与导电焊盘101电连接。
所述裸片垫102、第一绝缘介质层103以及金属结构层104所形成的电容元件，金属结构层104通过特殊物理结构形成的电感元件、电阻元件，电容元件电感元件及电阻元件均称为无源器件。
本发明实施例还记载了一种集成无源器件的框架封装结构的制备方法，包括以下步骤：
步骤一，如图2所示，提供引线框架，所述引线框架包括裸片垫102和位于裸片垫外围的导电焊盘101。所述裸片垫102和导电焊盘101均为导电金属材料形成；
步骤二，如图3所示，在所述裸片垫102下表面形成第一绝缘介质层103，所述第一绝缘介质层103通过PVD、CVD等工艺淀积形成，其材料可以为Si3N4、SiO2等高介电常数介质作为电容元件的介质层，也可以为PI、PBO等有机聚合物作为电阻、电感元件与裸片垫102之间的绝缘层；
步骤三，如图4所示，在所述第一绝缘介质层103下表面通过电镀工艺形成一层金属导电材料，所述金属导电材料可以为铜(CU)、铝(Al)、银(Ag)、金(Au)等低电阻率导电材料构成电容下极板和电感元件，也 可以为镍铬合金、氮化钽等高电阻率材料构成电阻元件。然后通过光刻、刻蚀工艺等工艺去除多余的金属材料，从而形成金属结构层104，所述金属结构层104的形状可以为水平方向呈阵列排布的金属平面作为电容元件的下极板，从而与第一绝缘介质层103以及裸片垫102共同构成电容元件，也可以为线圈结构从而构成电感元件，还可以为高电阻率导电材料平面从而构成电阻元件，所述电容、电感、电阻元件均可称为无源器件。
步骤四，如图5所示，在所述金属结构层104的下表面形成第二绝缘介质层105，所述第二绝缘介质层105可以通过化学气相沉积(CVD)、物理气相沉积(PVD)等工艺淀积形成，第二绝缘介质层105的绝缘介质材料覆盖金属结构层104，且填充于金属结构层104金属材料之间的空隙处；
步骤五，如图6所示，在所述第二绝缘介质层105上通过光刻形成过孔107，所述过孔107穿透第二绝缘介质层105并与金属结构层104部分金属导电材料相接触，然后在已形成过孔107的第二绝缘介质层105上，通过电镀等工艺覆盖一层金属导电材料，并且该金属导电材料填充到过孔107内，与金属结构层104的金属导电材料连接，最后通过光刻刻蚀去除掉多余的金属材料，从而在第二绝缘介质层105的上表面形成金属互连层106，所述金属互连层106可以将无源器件管脚连接到导电焊盘101上，从而与有源芯片201相关信号进行电连接，也可以将所述无源器件管脚引出到本发明实施例的集成无源器件的框架封装结构外，从而与其他外部芯片连接；
步骤六，如图1所示，在所述裸片垫102上表面放置有源芯片201，所述有源芯片201上表面设置有焊盘端202，所述焊盘端202为金属结构且与有源芯片201内部电路结构电性互连。在有源芯片201上表面的焊盘端202与引线框架导电焊盘101之间形成金属键合线，从而实现有源芯片201内部电路与导电焊盘101的电性连接；
进一步地，如图7所示，在图6所示的封装结构的基础上，在金属互 连层106下方通过植球、电镀等工艺形成金属焊球，从而与其他封装结构或者裸芯片进行电性连接。
进一步地，如图8所示，以本发明的制备方法步骤五所示的方法，在第二绝缘介质层105的下表面形成的金属互连层106可以为多层的金属互连结构，从而满足更高密度信号的互连。
进一步地，如图9所示，在裸片垫102上表面可以通过现有多芯片集成工艺集成更多的有源芯片，从而形成框架多芯片封装结构。
本发明实施例的集成无源器件的框架封装结构中，可以在框架封装结构的裸片垫背面通过常规工艺集成大量的无源器件，这种结构充分利用了框架封装中裸片垫背面的空白区域，可以为本发明实施例的框架封装体中的芯片提供无源器件，还可以为整个系统中的其他芯片提供无源器件，而不需要增加额外的分立无源器件，本发明实施例可以有效提高整个系统的集成密度。同时，无源器件可以通过一层水平方向的金属走线连接到框架结构的导电焊盘上，通过导电焊盘与有源芯片相关信号网络进行电性连接，极大地缩短了有源芯片与无源器件之间的信号传输路径，提高了信号完整性。
本发明实施例所记载的技术方案之间，在不冲突的情况下，可以任意组合。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。
工业实用性
本发明实施例的技术方案，可以在框架封装结构的裸片垫背面通过常规工艺集成大量的无源器件，这种结构充分利用了框架封装中裸片垫背面的空白区域，可以为本发明实施例的框架封装体中的芯片提供无源器件， 还可以为整个系统中的其他芯片提供无源器件，而不需要增加额外的分立无源器件，本发明实施例可以有效提高整个系统的集成密度。同时，无源器件可以通过一层水平方向的金属走线连接到框架结构的导电焊盘上，通过导电焊盘与有源芯片相关信号网络进行电性连接，极大地缩短了有源芯片与无源器件之间的信号传输路径，提高了信号完整性。

Claims (15)

  1. 一种集成无源器件的框架封装结构，所述框架封装结构包括：裸片垫，设置于所述裸片垫下方的第一绝缘介质层，设置于所述第一绝缘介质层下方的金属结构层，设置于所述金属结构层下方的第二绝缘介质层，以及，设置于所述裸片垫外围的至少一个导电焊盘；所述至少一个导电焊盘与所述第二绝缘介质层连接；
    所述裸片垫上设置有至少一个有源芯片，所述至少一个有源芯片与所述导电焊盘电连接。
  2. 根据权利要求1所述的集成无源器件的框架封装结构，其中，所述第二绝缘介质层中设置有金属互连层；
    所述金属互连层与所述金属结构层电连接。
  3. 根据权利要求1所述的集成无源器件的框架封装结构，其中，所述金属互连层与所述导电焊盘电连接。
  4. 根据权利要求1至3任一项所述的集成无源器件的框架封装结构，其中，所述裸片垫、所述金属结构层以及所述第一绝缘介质层形成电容元件，其中，所述裸片垫作为所述电容元件的上极板；所述第一绝缘介质层作为所述电容元件的介质层；所述金属结构层作为所述电容元件的下极板。
  5. 根据权利要求1至3任一项所述的集成无源器件的框架封装结构，其中，所述金属结构层设置为线圈结构而形成电感元件；所述金属结构层采用高电阻率的材料，而形成电阻元件。
  6. 根据权利要求4所述的集成无源器件的框架封装结构，其中，所述第一绝缘介质层作为所述电阻元件、所述电感元件与所述裸片垫之间的绝缘层。
  7. 根据权利要求6所述的集成无源器件的框架封装结构，其中，所述第一绝缘介质层作为所述电容元件的介质层时，由氮化硅Si3N4或二氧化硅 SiO2材料制成；
    所述第一绝缘介质层作为所述电阻元件、所述电感元件与所述裸片垫之间的绝缘层时，由聚酰亚胺PI或聚对苯撑苯并二噁唑PBO材料制成。
  8. 根据权利要求6所述的集成无源器件的框架封装结构，其中，所述至少一个有源芯片的上表面设置有焊盘端，所述焊盘端为金属结构且与所述至少一个有源芯片内部电路电连接；在所述焊盘端与所述导电焊盘之间设置金属连接线，所述至少一个有源芯片的内部电路与所述导电焊盘电连接。
  9. 一种集成无源器件的框架封装结构的制备方法，所述方法包括：
    制作引线框架，所述引线框架包括裸片垫和位于裸片垫外围的导电焊盘；
    在所述裸片垫下表面设置第一绝缘介质层；
    在所述第一绝缘介质层下表面通过电镀工艺形成一层金属导电材料，通过光刻、刻蚀工艺去除多余的金属材料，而形成金属结构层；
    在所述金属结构层的下表面通过化学气相沉积CVD、物理气相沉积PVD的工艺淀积形成第二绝缘介质层；
    在所述第二绝缘介质层上通过光刻形成过孔，所述过孔穿透所述第二绝缘介质层而与金属结构层接触；在已形成过孔的第二绝缘介质层上，通过电镀工艺形成一层金属导电材料，并使所述金属导电材料填充到所述过孔内而与金属结构层连接，通过光刻刻蚀去除多余的金属导电材料，而在第二绝缘介质的上表面形成金属互连层；
    在所述裸片垫上表面设置至少一个有源芯片，并使所述至少一个有源芯片与所述导电焊盘电连接。
  10. 根据权利要求9所述的集成无源器件的框架封装结构的制备方法，其中，所述使所述至少一个有源芯片与所述导电焊盘电连接，包括：
    在所述至少一个有源芯片的上表面设置焊盘端，使所述焊盘端为金属结构且与所述至少一个有源芯片内部电路电连接；在所述焊盘端与所述导电焊盘之间设置金属连接线，使所述至少一个有源芯片的内部电路与所述导电焊盘电连接。
  11. 根据权利要求9所述的集成无源器件的框架封装结构的制备方法，其中，所述方法还包括：
    使所述金属互连层与所述导电焊盘电连接。
  12. 根据权利要求10至11任一项所述的集成无源器件的框架封装结构的制备方法，其中，所述裸片垫、所述金属结构层以及所述第一绝缘介质层形成电容元件，其中，所述裸片垫作为所述电容元件的上极板；所述第一绝缘介质层作为所述电容元件的介质层；所述金属结构层作为所述电容元件的下极板。
  13. 根据权利要求10至11任一项所述的集成无源器件的框架封装结构的制备方法，其中，所述方法还包括：
    使所述金属结构层设置为线圈结构而形成电感元件；使所述金属结构层采用高电阻率的材料，而形成电阻元件。
  14. 根据权利要求13所述的集成无源器件的框架封装结构的制备方法，其中，所述第一绝缘介质层作为所述电阻元件、所述电感元件与所述裸片垫之间的绝缘层。
  15. 根据权利要求13所述的集成无源器件的框架封装结构的制备方法，其中，所述第一绝缘介质层作为所述电容元件的介质层时，由氮化硅Si3N4或二氧化硅SiO2材料制成；
    所述第一绝缘介质层作为所述电阻元件、所述电感元件与所述裸片垫之间的绝缘层时，由聚酰亚胺PI或聚对苯撑苯并二噁唑PBO材料制成。
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US8263437B2 (en) * 2008-09-05 2012-09-11 STATS ChiPAC, Ltd. Semiconductor device and method of forming an IPD over a high-resistivity encapsulant separated from other IPDS and baseband circuit
CN103996663A (zh) * 2013-02-18 2014-08-20 英飞凌科技股份有限公司 半导体模块及其形成方法

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CN110739396A (zh) * 2019-11-11 2020-01-31 武汉新芯集成电路制造有限公司 一种芯片结构、圆晶结构及其制造方法
CN110739396B (zh) * 2019-11-11 2023-08-08 武汉新芯集成电路制造有限公司 一种芯片结构、晶圆结构及其制造方法

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