WO2012129822A1 - 带有绝缘体填充的阱结构的封装基板及其制造方法 - Google Patents

带有绝缘体填充的阱结构的封装基板及其制造方法 Download PDF

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Publication number
WO2012129822A1
WO2012129822A1 PCT/CN2011/072701 CN2011072701W WO2012129822A1 WO 2012129822 A1 WO2012129822 A1 WO 2012129822A1 CN 2011072701 W CN2011072701 W CN 2011072701W WO 2012129822 A1 WO2012129822 A1 WO 2012129822A1
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Prior art keywords
metal
well structure
filled
package substrate
insulator
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PCT/CN2011/072701
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English (en)
French (fr)
Inventor
陈俊
陈高鹏
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锐迪科创微电子（北京）有限公司
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Publication of WO2012129822A1 publication Critical patent/WO2012129822A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
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    • H01L2224/05554—Shape in top view being square
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
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    • H01L2924/30—Technical effects
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    • H01L2924/30107—Inductance

Definitions

  • the present invention relates to the field of packaging of multi-chip modules, and more particularly to a package substrate with an insulator-filled well structure and a method therefor. Background technique
  • a Multi Chip Module consists of a plurality of semiconductor dies in a package, and the interconnection between the semiconductor dies is accomplished by metal bond wires and metal interconnects on the substrate.
  • the substrate used in the multi-chip module package is a multilayer interconnection substrate, which can be fabricated by low temperature co-fired ceramic (LTCC) technology or multilayer laminate substrate.
  • LGA Local Area Network
  • the metal interconnect of the LGA substrate can be used to fabricate RF inductive components, Surface Mounted Device (SMD) solder pads.
  • RF circuits used in the field of wireless communication usually cannot be integrated into a single chip because they require matching devices such as inductors and capacitors to make matching networks and filtering networks.
  • the inductors, capacitors, etc. can be mounted to achieve package integration.
  • the number of metal layers is usually 2 to 4 layers, and devices such as inductors, capacitors and even filters are mounted inside.
  • FIG. la it is a schematic diagram of a multi-chip module packaged in a 2-layer metal layer LGA.
  • the multi-chip module 100 includes two dies U1 and U2 mounted on its upper surface metal layer. Through the bonding wires 108, the corresponding die bonding pads on U1 and U2 can be connected to each other, or the die bonding pads on U1 and U2 can be connected to corresponding pins 107 on the LGA substrate, or The die bond pads on U1 and U2 are connected to corresponding substrate bond pads on the upper surface of the LGA substrate.
  • the traces on the surface metal layer on the upper surface of the LGA substrate are formed into a planar spiral structure, and the inductive components, such as the planar spiral inductors 101 and 102 shown in FIG. Since the thickness of the metal layer in the LGA package can be several tens or even hundreds of micrometers, the parasitic resistance of the planar spiral inductor produced is small, so that the inductance component has a high quality factor (Q value), which is to improve the radio frequency. The performance of the circuit is very meaningful. As shown in FIG.
  • the die bond pad on the die U2 is connected to one end of the planar spiral inductor 102 through a bonding wire 108; the other end of the planar spiral inductor 102 is connected to the lower surface metal layer of the LGA substrate through the via 103.
  • One end of the trace 104; the other end of the trace 104 is connected to the pin 107 of the LGA module, which achieves an electrical connection between the die bond pad on the die U2 and the LGA module pin 107.
  • an SMD element can be mounted, as shown by 109 in FIG.
  • the SMD component 109 can typically be a passive component such as a resistor, a capacitor, an inductor, a diode, etc., and the SMD component 109 can be easily connected to the die and the module pins in the module through the bonding wires 108 and the LGA substrate metal layer routing. . It can be seen that the LGA package provides great flexibility for signal interconnects in multi-chip modules, especially in RF applications, which can integrate high quality passive components (such as high Q planar spiral inductors). , SMD components, etc.), making RF multi-chip modules have higher performance.
  • the LGA package form also has some drawbacks.
  • the manufacturing process of the LGA substrate is very complicated, and it requires a series of materials such as lamination, drilling, filling of an electrically and thermally conductive material, lithographic etching of a metal layer, plating of metal, etc., making the LGA package expensive.
  • the LGA substrate material is usually made of a resin material having poor thermal conductivity, heat dissipation of the chip is also greatly limited in high power applications.
  • the metal layer on the back side of the LGA needs to be traced, which destroys the integrity of the grounded metal pad on the back side or reduces the area of the grounded metal pad on the back side, which is not conducive to the sticking of the semiconductor device of the LGA package on the PCB. Installed.
  • the Quad Flat Non-leaded Package is a metal frame-based leadless package with a large exposed die attach pad (DAP, Die Attach Paddle) at the center of the package. , with thermal conductivity.
  • the integrated passive passive device (IPD) process is used to fabricate passive components such as inductors and capacitors required in the RF circuit on a semiconductor die, thereby enabling a relatively simple RF power amplifier on the QFN.
  • Module front-end module.
  • Figure lb shows a multi-chip module in a QFN package.
  • the QFN package mounts the semiconductor die directly on the metal frame (dies Ul, U2, and U3 as shown in Figure lb), making the manufacturing process much more compact than the LGA package.
  • the QFN metal frame cannot provide interconnect traces, so that multiple chips can only be interconnected by inter-chip metal bond wires, which cannot meet the design requirements of most multi-chip modules.
  • the back metal needs to be directly grounded, and the largest possible back ground metal pad is required to reduce the parasitic grounding inductance to provide good RF grounding, ensuring that the chip's electrical performance will not be deterioration.
  • the current wireless communication product design requires that the RF power amplifier module and the RF front-end module be as small as possible, and their power specifications are not reduced. Therefore, the large ground metal pad on the back side is also beneficial to the heat dissipation of the module. Summary of the invention
  • the technical problem to be solved by the present invention is to provide a package substrate with an insulator-filled well structure and a method for fabricating the same, which solves the problems of inflexible wiring and low radio frequency inductance of the multi-chip module substrate produced by the prior art.
  • the present invention provides a package substrate with an insulator-filled well structure, wherein the package substrate has at least one well, and the well is filled with an insulating material to form a well structure, and The upper surface of the well structure has a metal pattern.
  • the metal pattern is a metal trace directly connected to a pin of the package substrate, a solder pad of a surface mount device, a substrate bond pad or a solder ball of a flip chip mounted semiconductor chip Pad.
  • the metal trace is a single layer or a plurality of metal traces.
  • the present invention also provides a method for manufacturing a package substrate with an insulator-filled well structure, comprising:
  • the well is filled with an insulating material to form a well structure, and a metal pattern is formed on the upper surface of the well structure after the insulating material is filled.
  • a masking process is performed on the upper and lower surfaces of the metal frame, and then at least one well is formed on the metal frame by etching or etching.
  • the upper surface of the well structure after filling the insulating material is formed into a metal pattern by plating metal or depositing metal.
  • the metal pattern is further a metal trace directly connected to a pin of the package substrate, a solder pad of a surface mount device, a substrate bond pad or a solder of a flip chip mounted semiconductor chip Ball pad.
  • the metal pattern is covered by an insulating material.
  • the metal trace is further a single layer or a plurality of metal traces.
  • FIG. 1a is a schematic diagram of a conventional multi-chip module using a 2-layer metal layer LGA package
  • FIG. 1b is a schematic diagram of a conventional multi-chip module using a QFN package
  • FIG. 3 is a front view of a package substrate with an insulator-filled well structure according to Embodiment 2 of the present invention
  • FIG. 3b is a front view of a package substrate according to Embodiment 2 of the present invention
  • FIGS. 3a and 3d are cross-sectional views of the package substrate with an insulator-filled well structure along the line AA shown in FIGS. 3a and 3b according to Embodiment 2 of the present invention
  • FIG. 4a is a strip according to Embodiment 3 of the present invention
  • 4 is a front view of a package substrate having an insulator-filled well structure
  • FIG. 4b is a schematic rear view of a package substrate with an insulator-filled well structure according to Embodiment 3 of the present invention
  • FIG. 4c is a cross-sectional view of the package substrate with the insulator-filled well structure of FIG. 4a and 4b taken along line BB of FIG. 4a;
  • 4a is a cross-sectional view of the package substrate with an insulator-filled well structure according to the third embodiment of the present invention, which is molded along a tangent line BB shown in FIGS. 4a and 4b;
  • FIG. 5a to FIG. A schematic diagram of a second method of fabricating a package substrate having an insulator-filled well structure;
  • FIGS. 6a to 6c are schematic views showing a third method of fabricating a package substrate having an insulator-filled well structure according to Embodiment 5 of the present invention.
  • the main idea of the present invention is to solve the problems that the package substrate of the existing multi-chip module is inflexible, and the radio frequency inductance value is low.
  • the present invention provides a multi-chip module package substrate and method for manufacturing a process cartridge, which is inexpensive, has a large large-area ground pad, and has good heat dissipation performance. The specific embodiments are described in detail below, but are not intended to limit the invention.
  • a first embodiment of the present invention provides a method for manufacturing a package substrate with an insulator-filled well structure metal frame (WES, Well Embedded Substrate), which is specifically fabricated.
  • the process is:
  • a metal plate 201 of a suitable thickness may be used, which may be made of copper, aluminum, iron, copper alloy or nickel-iron alloy, and the upper and lower surfaces of the metal plate 201 are flat.
  • the material may be selected according to the actual application, and the present invention is not specifically limited.
  • a mask for defining a pattern is coated or mounted on the upper and lower surfaces of the metal plate 201, as shown in Fig. 2b, an upper surface mask 202 and a lower surface mask 203.
  • the masked metal plate 201 is etched (or etched, etc.), and the wells 204, 205, 206 are etched downward from the upper surface of the metal plate 201.
  • P means that the thickness of the portion which is etched on the metal plate and which is etched away is smaller than the thickness of the metal plate, and the definition of "well” can be understood with reference to Fig. 2c. From the above, the position of the well is defined by the upper surface mask 202 in step 2b.
  • the well 204 and the holes 207 and 208 formed in the above-described steps are filled with an insulating material such as resin or plastic.
  • an insulating material such as resin or plastic.
  • a WES package substrate having a flat upper and lower surface is obtained.
  • a well structure 209 and hole structures 210, 211 are formed on the WES package substrate.
  • the "well structure" in the present invention is formed by filling a "well” with an insulating material composed of a bottom metal and an insulating material thereon.
  • there is a metal support around the insulating material in the well structure which may be a side wall that completely surrounds the well structure or may be partially enclosed.
  • the side wall is completely surrounded by the surrounding metal, and in another embodiment of the invention, the side structure of the well structure may be partially surrounded by the surrounding metal.
  • a metal trace 212 is formed by a method of plating metal (or an equivalent technique such as depositing metal). It should be noted here that the metal trace 212 formed in this step further includes a bonding pad (referred to as a substrate bonding pad) that can be used for metal wire bonding, and can be used for mounting SMD (Surface Mounted Devices, a surface mount device) solder pad of the component, a solder ball pad which can be used for flip-chip mounting of the semiconductor chip, and the like; and a metal formed on the well structure 209 by adding a step of depositing an insulating dielectric layer, a photolithography mask, or the like Trace 212 can be a multi-layer structure.
  • a bonding pad referred to as a substrate bonding pad
  • SMD Surface Mounted Devices, a surface mount device solder pad of the component, a solder ball pad which can be used for flip-chip mounting of the semiconductor chip, and the like
  • Trace 212 can be a multi-layer structure.
  • the sealing process is usually performed on the WES substrate of the die and SMD component mounting and bonding industry described above, using a sealing resin 215 or the like, so that the upper surface of the WES package substrate
  • the die and SMD components, as well as the bond wires, etc., are completely encapsulated in the sealing material, i.e., the metal pattern described in the Summary of the Invention is covered by an insulating material.
  • a multi-chip module 300 is fabricated using a WES package substrate as described in the above fabrication process.
  • the upper surface metal DAP portion 302 of the WES package substrate is mounted with two semiconductor dies U1 and U2.
  • the die bond pads on the two semiconductor dies U1 and U2 are connected to each other by bond wires 303; the bond wires 303 can also connect the die bond pads on the two semiconductor dies U1 and U2 to The corresponding WES package substrate pins 304 or DAP portion 302.
  • the DAP portion 302 and the pins 304 around it are made of a metal material, and the 308 and 305 indicated by the hatched portions are insulating materials, wherein the portion 305 indicated by the broken line frame is a well structure, and the well structure 305 is Surface, metal traces are fabricated using the foregoing process steps, as shown in FIG. 3a, including planar spiral inductors 306, solder pads 309 to which SMD devices 307 are mounted, their corresponding traces, and bond pads 310 of the substrate.
  • the planar spiral inductor 306, the mounted SMD component 307 can be connected to the bonding pad 310 of the semiconductor die, the WES substrate pin 304, etc., so as to be fabricated or mounted on the well structure.
  • the components on the upper surface of 305 are connected to the circuit.
  • the metal traces formed on the upper surface of the well structure 305 by electroplating or deposition can usually have a thickness of several tens of micrometers or more, so that the parasitic resistance is small and the inductance Q is high. Helps improve the performance of multi-chip modules for RF applications.
  • the rear view of the multi-chip module 300 shows that although the metal traces are formed on the well structure, the back surface of the 302 portion is still large-area and regular in shape, and its integrity is due to the well structure. It has been preserved, which is also an object of the invention for the WES substrate proposed by the present invention. It should be noted that the WES package substrate, which maximizes the area of the ground pad, provides a good electrical grounding and thermal path for the semiconductor die, which is very helpful to improve the performance of multi-chip modules for RF applications. From the cross-sectional view (in the tangential direction of A-A) as shown in Fig.
  • a cross-sectional view of the multi-chip module after completion of the resin sealing (in the tangential direction of A-A), 312 is a sealing material.
  • the multi-chip module packaging manufacturing process single-chip based on the WES package substrate increases the well structure definition and fabrication, and the metal connection manufacturing process on the well structure only in the conventional QFN package fabrication process, and the complexity is far. Far less than the LGA packaging process.
  • high-Q metal traces, planar spiral inductors, multilayer interconnect structures, and mounted SMD components can be fabricated on the top surface of the well structure. Etc., there is greater interconnect flexibility than QFN packages.
  • the WES package substrate provides a grounded metal pad with a maximized area, providing a good electrical grounding and thermal path for the semiconductor die. Therefore, the WES package substrate structure proposed by the present invention has a single manufacturing process, is inexpensive, has a large large-area ground pad, has good heat dissipation performance, and provides a high quality internal interconnection method.
  • the WES package substrate has a separate well structure 305.
  • a plurality of well structures can be fabricated on the WES package substrate as needed in a specific implementation.
  • the WES package substrate has two separate dashed frames 404 and 410 (shown in phantom in Figure 4a).
  • the dotted frame 404 of the well structure is characterized in that its side wall is completely surrounded by the metal frame, and other patterns such as metal traces and SMD solder pads can be formed on the flat upper surface thereof, as shown in the figure.
  • the dashed frame 410 of the well structure is characterized in that its side wall is surrounded by the metal frame portion, and other patterns such as metal traces and SMD solder pads can be formed on the flat upper surface thereof, as shown in FIG. 4a.
  • Fig. 4b a schematic view of the back side of the multichip module 400, it can be seen that despite the metal traces formed on the dashed frames 404 and 410 of the well structure, the back side of the DAP portion 402 is still large and complete in shape and regular in shape.
  • a cross-sectional view of the multi-chip module after completion of the resin sealing is a sealing material.
  • the embodiment of the present invention further provides a method for manufacturing a package substrate with an insulator-filled well structure metal frame fabrication (WES, Well Embedded Substrate). As shown in FIGS. 5a to 5d, the specific steps of the method include:
  • a metal plate 801 of appropriate thickness is coated or placed on the upper and lower surfaces with masks 802, 803 and then etched (etched).
  • Another metal plate 807 of appropriate thickness is coated or placed on the upper and lower surfaces with masks 808, 809 and then etched (etched).
  • a metal plate 901 having a suitable thickness is coated or placed on the upper and lower surfaces with masks 902 and 903, and then etched (etched).
  • the manufacturing method and flow of the WES package substrate described above are merely examples of forming a WES package substrate, and are not limited to the WES package substrate manufacturing method. Any method having the same technical effect as the above manufacturing process can be used to fabricate a WES package substrate, forming a well-filled well structure on the WES package substrate, and fabricating metal traces on the upper surface of the well structure. Since the well structure is embedded in the metal frame, the exposed ground metal pad portion on the back surface of the WES package substrate is not affected by the fabrication of the well structure, and a large area of the exposed metal pad can still be maintained.
  • the manufacturing process of the multi-chip module package manufacturing process based on the WES package substrate can be seen, and the steps of defining the well structure and manufacturing, and the metal wiring manufacturing on the well structure are added only in the conventional QFN package manufacturing process, and the complexity is far. Far less than the LGA packaging process.
  • the WES package substrate provides a grounded metal pad with a maximized area, providing a good electrical grounding and thermal path for the semiconductor die.
  • the WES package substrate structure proposed by the present invention has a single manufacturing process, is inexpensive, has a large large-area ground pad, has good heat dissipation performance, and provides a high quality internal interconnection method.
  • the invention may, of course, be embodied in various other forms and modifications without departing from the spirit and scope of the invention.

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Description

带有绝缘体填充的阱结构的封装基板及其制造方法 技术领域
本发明涉及多芯片模块的封装领域， 具体地说， 本发明涉及一种带有绝缘 体填充的阱结构的封装基板及其方法。 背景技术
多芯片模块（ MCM, Multi Chip Module )是在一个封装内包含了多个半导 体管芯， 并且半导体管芯之间的互连是通过金属键合线及基板上的金属互连线 完成。 通常， 多芯片模块封装所采用的基板是一块多层互连基板， 可以由低温 共烧陶瓷（ LTCC, Low Temperature Co-fired Ceramic )技术或多层层压基板制 造。 LGA ( Land Grid Array )封装是多芯片模块常用的一种半导体封装形式， 其采用多层层压基板， 在金属材料层上可以制作互连走线； 相邻的不同金属材 料层由绝缘材料层隔离； 位于不同金属材料层上的走线可以通过贯穿绝缘材料 层的过孔相互连接。 LGA基板的金属互连可以用于制作射频电感元件、表面贴 装元件（SMD, Surface Mounted Device )焊接焊盘。 用于无线通信领域的射频 电路由于需要用电感、 电容等无源器件制作匹配网络和滤波网络， 通常不能做 到单芯片集成。 采用 LGA封装形式则可以通过贴装电感、 电容等方式以达到 封装集成的目的。 目前， 射频功率放大器模块以及集成有射频天线开关的射频 前端模块产品绝大多数是采用 LGA封装， 金属层数通常为 2到 4层， 同时内 部贴装有电感、 电容甚至滤波器等器件。
如图 la所示， 为一个采用 2层金属层 LGA封装的多芯片模块的示意图。 如图所示，多芯片模块 100中包含两个贴装在其上表面金属层的管芯 U1和 U2。 通过键合线 108, 可以将 U1和 U2上相应管芯键合焊盘相互连接起来， 或者将 U1和 U2上的管芯键合焊盘连接到 LGA基板上的相应管脚 107, 也可以将 U1 和 U2上的管芯键合焊盘连接到 LGA基板上表面的相应基板键合焊盘上。 将 LGA基板上表面金属层上的走线制作为平面螺旋结构， 可以实现电感元件， 如 图 la中所示的平面螺旋电感 101及 102。 由于通常 LGA封装中金属层的厚度 可以达到几十甚至上百微米， 使得其制作的平面螺旋电感的寄生电阻很小， 从 而使电感元件有较高的品质因子（Q值），这对于提高射频电路的性能是非常有 意义的。 如图 la所示， 管芯 U2上的管芯键合焊盘通过键合线 108连接到了平 面螺旋电感 102的一端； 平面螺旋电感 102的另外一端通过过孔 103连接到了 LGA基板下表面金属层的走线 104的一端；走线 104的另外一端连接到了 LGA 模块的管脚 107, 这就实现了管芯 U2上管芯键合焊盘与 LGA模块管脚 107的 相互电气连接。 并且， 在 LGA基板上表面上， 还可以贴装 SMD元件， 如图 la 中所示的 109。 SMD元件 109通常可以是电阻、 电容、 电感、 二极管等无源器 件， 通过键合线 108及 LGA基板金属层走线， SMD元件 109可以非常方便地 连接到模块内的管芯及模块的管脚。 可以看到， LGA封装形式为多芯片模块内 的信号互连提供了^艮大的灵活性， 尤其是在射频应用中， 它可以集成高质量的 无源器件（如高 Q值的平面螺旋电感、 SMD元件等）， 使得射频多芯片模块具 有较高的性能。
然而， LGA封装形式也有一些缺点。 首先， LGA基板的制造工艺非常复 杂， 需要经过一系列材料层压、 钻孔、 填充导电导热材料、 光刻腐蚀金属层、 电镀金属等步骤， 使得 LGA封装的价格昂贵。
其次， 由于 LGA基板材料通常是用导热性能不佳的树脂材料制作， 在大 功率应用下芯片散热也受到很大限制。 并且， 通常 LGA 背面金属层都需要走 线， 就破坏了其背面接地金属焊盘的完整性， 或使其背面接地金属焊盘的面积 减小， 不利于 LGA封装的半导体器件在 PCB上的贴装。
无引线方形扁平封装（ QFN, Quad Flat Non-leaded package )是一种基于金 属框架的无引脚封装， 其封装中央位置有大面积棵露的管芯贴装焊盘（DAP, Die Attach Paddle ), 具有导热作用。 采用集成无源器件（ IPD, Integrated Passive Device )工艺， 将射频电路中所需的电感、 电容等无源器件制作在一个半导体 管芯上，进而可以在 QFN上实现功能较为筒单的射频功率放大器模块、前端模 块。 如图 lb所示为一个采用 QFN封装的多芯片模块。 QFN封装在金属框架上 直接贴装半导体管芯（如图 lb中所示的管芯 Ul、 U2和 U3 ), 使得制造工艺比 LGA封装筒单得多。 然而， 相对于 LGA封装形式， QFN金属框架上不能提供 互连走线， 使得多芯片之间仅能通过芯片间金属键合线互连， 不能满足多数多 芯片模块设计要求。
美国专利 US7154169中所提出的技术方案， 通过在 QFN管脚之间安置金 属线形成非相邻管脚间互连， 也未能很好解决芯片间互连问题。 并且， 为了放 置这种互连金属线，会导致金属框架 DAP背面接地金属焊盘形状不规则且接地 面积减小， 而规则的背面接地金属焊盘是保证工业生产焊接良率的重要条件。 另外， 该专利也提出了在管脚间贴装电容元件， 但是实际上很多电容需要贴装 在芯片之间或者与电感元件串联使用， 其方案也不能满足此要求。
对于射频功率放大器模块及射频前端模块而言，其背面金属需要直接接地， 并且要求有尽可能大的背面接地金属焊盘来降低寄生接地电感以提供良好的射 频接地， 保证芯片的电气性能不会恶化。 当前无线通信产品设计要求射频功率 放大器模块及射频前端模块尺寸尽可能小， 而其功率指标并未降低， 因此尽可 能大的背面接地金属焊盘也有利于模块的散热。 发明内容
本发明所要解决的技术问题是提供一种带有绝缘体填充的阱结构的封装基 板及其制造方法， 以解决现有技术所生产的多芯片模块基板走线不灵活， 射频 电感值低等问题。
为解决上述技术问题， 本发明提供了一种带有绝缘体填充的阱结构的封装 基板， 其特征在于， 所述封装基板具有至少一个阱， 所述阱中填充有绝缘材料 形成阱结构， 且所述阱结构的上表面上具有金属图形。
进一步地， 其中， 所述金属图形为与所述封装基板的管脚直接相连的金属 走线、 贴装表面贴装器件的焊接焊盘、 基板键合焊盘或倒扣安装半导体芯片的 焊球焊盘。
进一步地， 其中， 所述金属走线为单层或多层的金属走线。
为解决上述技术问题， 本发明还提供了一种带有绝缘体填充的阱结构的封 装基板制造方法， 其特征在于， 包括：
在金属框架上制作至少一个阱；
在所述阱中填充绝缘材料形成阱结构， 在填充完绝缘材料后的所述阱结构 的上表面制作金属图形。
进一步地， 其中， 在金属框架上下表面进行掩膜处理， 然后再通过腐蚀或 刻蚀在所述金属框架上制作至少一个阱。
进一步地， 其中， 在填充完绝缘材料后的所述阱结构的上表面通过电镀金 属或淀积金属方式制作金属图形。 进一步地， 其中， 所述金属图形进一步为与所述封装基板的管脚直接相连 的金属走线、 贴装表面贴装器件的焊接焊盘、 基板键合焊盘或倒扣安装半导体 芯片的焊球焊盘。 进一步地， 其中， 所述金属图形被绝缘材料覆盖。 进一步地， 其中， 所述金属走线进一步为单层或多层的金属走线。 与现有技术相比， 本发明所述的带有绝缘体填充的阱结构的封装基板及其 制造方法， 解决了现有技术所生产的多芯片模块基板走线不灵活， 射频电感值 低等问题； 且制造工艺筒单、 价格便宜、 有完整的大面积接地焊盘、 同时具有 良好的散热性能， 并提供了高质量的内部互连方法。 附图说明
图 la为现有的采用 2层金属层 LGA封装的多芯片模块的示意图； 图 lb为现有的采用 QFN封装的多芯片模块的示意图； 图 2a至图 2i为本发明实施例一所述的带有绝缘体填充的阱结构的封装基 板的制造方法示意图； 图 3a 为本发明实施例二所述的带有绝缘体填充的阱结构的封装基板的正 面示意图； 图 3b 为本发明实施例二所述的带有绝缘体填充的阱结构的封装基板的背 面示意图；
图 3c及图 3d为本发明实施例二所述的带有绝缘体填充的阱结构的封装基 板的沿图 3a和 3b所示切线 A-A的剖面图； 图 4a 为本发明实施例三所述的带有绝缘体填充的阱结构的封装基板的正 面示意图； 图 4b 为本发明实施例三所述的带有绝缘体填充的阱结构的封装基板的背 面示意图；
图 4c 为本发明实施例三所述的带有绝缘体填充的阱结构的封装基板沿图 4a和 4b所示切线 B-B的剖面图； 图 4d 为本发明实施例三所述的带有绝缘体填充的阱结构的封装基板沿图 4a和 4b所示切线 B-B塑封之后的剖面图； 图 5a至图 5d为本发明实施例四所述的带有绝缘体填充的阱结构的封装基 板的第二种制造方法示意图； 图 6a至图 6c为本发明实施例五所述的带有绝缘体填充的阱结构的封装基 板的第三种制造方法示意图。 具体实施方式
本发明的主要思想是解决现有的多芯片模块的封装基板走线不灵活， 射频 电感值低等问题。 本发明提供了制造工艺筒单、 价格便宜、 有完整的大面积接 地焊盘、 同时具有良好的散热性能的多芯片模块封装基板及方法。 以下对具体 实施方式进行详细描述， 但不作为对本发明的限定。
为实现多芯片模块的封装基板， 如图 2a至 2i所示， 本发明实施例一提供 一种带有绝缘体填充的阱结构金属框架（WES , Well Embedded Substrate )的封 装基板的制造方法， 具体制作流程为：
(a) 如图 2a所示， 取一块厚度合适的金属板 201 , 其材料可以为铜、 铝、 铁、 铜合金或镍铁合金等， 并且金属板 201上下表面平整。 这里可以根据实际 应用选取材料， 本发明不做具体限定。
(b) 在金属板 201上下表面涂覆或贴装用于定义图形的掩膜， 如图 2b所 示， 上表面掩膜 202及下表面掩膜 203。
(c) 如图 2c所示， 对所述带掩膜的金属板 201进行腐蚀（或刻蚀等等同 技术）， 从金属板 201上表面向下腐蚀出阱 204、 205、 206。
这里在本发明中， " P并"指的是在金属板上腐蚀出来， 并且其腐蚀掉的部分 的厚度小于金属板的厚度， 可以参照图 2c理解 "阱" 的定义。 由上可知， 阱的 位置由步骤 2b中上表面掩膜 202所定义。
(d) 在所述带有阱 204、 205、 206的金属板 201上下表面涂覆或贴装用于 定义图形的掩膜， 如图 2d所示的上表面掩膜 202及下表面掩膜 203。
(e) 对所述带有阱 204、 205、 206且带掩膜的金属板 201进行腐蚀（或刻 蚀等等同技术）， 从金属板 201下表面向上腐蚀。 如图 2e可知， 由于在本步骤 的腐蚀中， 原先的阱 205、 206底部的金属板部分被腐蚀掉， 从而出现如图 2e 所示的孔 207及 208, 他们完全贯穿了金属板 201的厚度， 而阱 204仍然保持 不变。 在这里需要说明的是， 在本发明中， 需要区分 "孔" 及 "阱" 的区别， 通过参照图 2e, 可以更加容易理解其区别。 如图 2e所示， 在此步骤完成之后， 金属板 201上形成了 WES封装基板管脚 216部分及管芯贴装区域 (DAP)217部 分。
(f) 采用树脂或塑料等绝缘材料填充上述步骤形成的阱 204及孔 207、 208, 如图 2f所示， 得到了上下表面都平整的 WES封装基板。 这一步骤完成之 后， 在 WES封装基板上形成了阱结构 209及孔结构 210、 211。 这里需要说明 的是， 本发明中 "阱结构" 是由绝缘材料填充 "阱" 而形成的， 阱结构由底部 金属以及其上的绝缘材料组成。 通常阱结构中绝缘材料周围有金属支撑， 所述 周围金属可以是完全包围阱结构的侧围， 也可以是部分包围。 例如在如图 2f 中， 虚线框所示的阱结构 209, 其侧围被周围金属所完全包围， 而在本发明的 另外一个实施例中， 阱结构侧围可以被周围金属所部分包围。
(g) 如图 2g所示， 在上述 WES封装基板的阱结构 209的上表面上， 采 用电镀金属 (或淀积金属等等同技术)的方法， 形成金属走线 212。这里需要注意 的是，本步骤形成的金属走线 212,还包括可以用于金属线键合的键合焊盘（称 为基板键合焊盘）、 可以用于贴装 SMD ( Surface Mounted Devices, 表面贴装器 件）元件的焊接焊盘、 可以用于倒扣安装半导体芯片的焊球焊盘等； 并且， 通 过增加淀积绝缘介质层、 光刻掩膜等步骤， 阱结构 209上制作的金属走线 212 可以是多层结构。
(h) 上述几个步骤已经完成了 WES 封装基板制造的基本步骤， 在基于 WES封装基板的半导体封装制造中，本步骤将半导体管芯芯片 213贴装在 WES 封装基板中金属板 201的管芯贴装区域 (DAP)217上表面、 将 SMD元件贴装在 制作于阱结构 209上的焊接焊盘上。然后进行金属线键合作业，采用键合线 214 完成管芯键合焊盘、基板键合焊盘及 WES管脚之间的相应互连，如图 2h所示。
(i) 为了完成基于 WES封装基板的半导体器件的封装， 通常在上述完成 管芯和 SMD元件贴装及键合作业的 WES基板上采用密封树脂 215等材料进行 密封作业， 使得 WES封装基板上表面、 管芯和 SMD元件以及键合线等都完全 包覆在密封材料中， 即发明内容中所述的金属图形被绝缘材料覆盖。 这就完成 了基于 WES基板的半导体器件的封装， 如图 2i所示。 如图 3a至 3d所示， 为采用本发明所提出的 WES基板封装的一个多芯片 模块， 作为本发明的实际操作的第一个实施例。 一个多芯片模块 300, 其采用 了如上述制作流程所制作的 WES封装基板， WES封装基板的上表面金属 DAP 部分 302贴装了两个半导体管芯 U1及 U2。 两个半导体管芯 U1及 U2上的管 芯键合焊盘， 通过键合线 303相互连接； 键合线 303还可以将两个半导体管芯 U1及 U2上的管芯键合焊盘连接到相应的 WES封装基板管脚 304上或者 DAP 部分 302上。
如图 3a所示， DAP部分 302及其周围的管脚 304为金属材料， 阴影部分 标示的 308、 305则为绝缘材料， 其中虚线框所标示的 305部分为阱结构， 在阱 结构 305的上表面， 采用前述工艺步骤制作了金属走线， 如图 3a所示， 包括了 平面螺旋电感 306、贴装 SMD元件 307的焊接焊盘 309及其相应走线以及基板 的键合焊盘 310等。 通过键合线 303 , 可以将平面螺旋电感 306、 贴装 SMD元 件 307连接到半导体管芯的键合焊盘 310、 WES基板管脚 304等进行互连， 从 而可以将制作或贴装在阱结构 305上表面的元件连接到电路之中。 这里需要说 明的是， 通过电镀或淀积方式在阱结构 305上表面制作的金属走线， 其厚度通 常可以高达数十微米甚至更高， 使得其寄生电阻很小， 电感 Q值很高， 这有助 于提高射频应用多芯片模块的性能。
如图 3b所示为多芯片模块 300的背面示意图，可以看到尽管阱结构上制作 了金属走线， 302 部分的背面仍然是大面积完整且形状规则的， 其完整性由于 采用了阱结构而得到了保全， 这也是本发明所提出的 WES基板的一个发明目 的。 这里需要说明的是， WES封装基板这种面积最大化的接地焊盘， 为半导体 管芯提供了良好的电气接地及导热通路， 非常有助于提高射频应用多芯片模块 的性能。 从如图 3c所示的剖面图 （沿 A-A切线方向）上， 也可以看到阱结构 的阱结构 305部分与金属板 302、 WES封装基板管脚 304、 孔结构 308在厚度 方向上的关系。 如图 3d所示为完成树脂密封之后的多芯片模块的剖面图 （沿 A-A切线方向）， 312为密封材料。
如上所述， 可以看到基于 WES封装基板的多芯片模块封装制作工艺筒单， 仅在普通 QFN封装制作工艺上增加了阱结构定义及制作、阱结构上金属连线制 作等步骤， 复杂度远远低于 LGA封装工艺。 同时， 由于在阱结构上表面可以 制作高 Q值的金属走线、 平面螺旋电感、 多层互连线结构以及贴装 SMD元件 等， 相对于 QFN封装有更大的互连灵活性。 并且， WES封装基板能够提供面 积最大化的背面接地金属焊盘， 为半导体管芯提供了良好的电气接地及导热通 路。 因此， 本发明所提出的 WES封装基板结构， 制造工艺筒单、 价格便宜、 有完整的大面积接地焊盘、 同时具有良好的散热性能， 并提供了高质量的内部 互连方法。
需要说明的是， 在上述实施例中， WES封装基板上具有一个独立的阱结构 305。 事实上， 根据本发明所提出的技术方案， 在具体实施中可以根据需要在 WES封装基板上制作多个阱结构。
如图 4a至 4d所示的实际操作的第二个实施例， WES封装基板上具有两个 独立的阱结构的虚线框 404及 410 (如图 4a中虚线框所示）。 其中阱结构的虚 线框 404的特点是， 其侧围被金属框架完全包围， 并且可以在其平整的上表面 上制作金属走线及 SMD 焊接焊盘等其他图形， 如图中所示的平面螺旋电感 405、 贴装 SMD元件 406的焊接焊盘 411以及基板键合焊盘 412。 而阱结构的 虚线框 410的特点是， 其侧围被金属框架部分包围， 并且可以在其平整的上表 面上制作金属走线及 SMD焊接焊盘等其他图形， 如图 4a中所示的平面螺旋电 感 408、 连接到 WES封装基板管脚 401的金属走线 407、 贴装 SMD元件 409 的焊接焊盘以及基板键合焊盘。 如图 4b所示为多芯片模块 400的背面示意图， 可以看到尽管阱结构的虚线框 404及 410上制作了金属走线， DAP部分 402的 背面仍然是大面积完整且形状规则的。 从如图 4c所示的剖面图 （沿 B-B切线 方向）上， 也可以看到阱结构的虚线框 410部分与管芯贴装区域 402、 孔结构 403、 管脚 401在厚度方向上的关系。 如图 4d所示为完成树脂密封之后的多芯 片模块的剖面图 （沿 B-B切线方向）， 414为密封材料。
此外， 本发明实施例还提供另外一种带有绝缘体填充的阱结构金属框架 制作（WES, Well Embedded Substrate )的封装基板的制造方法， 如图 5a至 5d 所示， 该方法具体步骤包括：
( a )将一块厚度合适的金属板 801 ,上下表面涂覆或贴装掩膜 802、 803 , 然后进行腐蚀（刻蚀）。
( b )将另外一块厚度合适的金属板 807, 上下表面涂覆或贴装掩膜 808、 809, 然后进行腐蚀（刻蚀）。
( c )将上述步骤（a )及步骤（b )得到的腐蚀后的两块金属板拼接在一 起， 如图 5c所示， 可以看到本步骤形成了孔 813、 814及阱 815。
( d )采用树脂或塑料等绝缘材料填充上述步骤形成的阱 815及孔 813、 814, 得到阱结构 818及孔结构 816、 817。 如图 5d所示可以看到， 这里形成的 阱结构 818及孔结构 816、 817与如图 2h中所示的阱结构 209及孔结构 210、 211是等价的。
如图 6a至 6c所示， 对于上述实施例来说， WES封装基板的制造方法的 另外一种制作流程：
( a )将一块厚度合适的金属板 901 ,上下表面涂覆或贴装掩膜 902、 903 , 然后进行腐蚀（刻蚀）。
( b )在腐蚀过的金属板上填充绝缘材料 907、 908、 909, 形成如图 6b 所示的结构。
( c )在上述金属板 905、 904及 906部分上淀积（或称填充）金属材料， 形成金属 911、 912、 913及 914部分， 如图 6c所示。 可以看到， 这里形成的阱 结构 910及孔结构 907、 908与如图 2h中所示的阱结构 209及孔结构 210、 211 是等价的。
需要说明的是，上述 WES封装基板的制造方法及流程，仅作为形成 WES 封装基板的示例， 而非对 WES封装基板制造方法的限定。 任何与上述制造流 程具有等同技术效果的方法， 都可以用于制造 WES封装基板， 在 WES封装基 板上形成绝缘材料填充的阱结构， 并在所述阱结构上表面制作金属走线。 由于 所述阱结构嵌入金属框架， 使得 WES封装基板背面棵露的接地金属焊盘部分 不受阱结构的制造影响， 仍然可以保持大面积的棵露金属焊盘。
如上所述， 可以看到基于 WES封装基板的多芯片模块封装制造工艺筒单， 仅在普通 QFN封装制造工艺上增加了阱结构定义及制造、阱结构上金属连线制 造等步骤， 复杂度远远低于 LGA封装工艺。 同时， 由于在阱结构上表面可以 制作高 Q值的金属走线、 平面螺旋电感、 多层互连线结构以及贴装 SMD元件 等， 相对于 QFN封装有更大的互连灵活性。 并且， WES封装基板能够提供面 积最大化的背面接地金属焊盘， 为半导体管芯提供了良好的电气接地及导热通 路。 因此， 本发明所提出的 WES封装基板结构， 制造工艺筒单、 价格便宜、 有完整的大面积接地焊盘、 同时具有良好的散热性能， 并提供了高质量的内部 互连方法。 当然， 本发明还可有其他多种实施例， 在不背离本发明精神及其实质的情 些相应的改变和变形都应属于本发明所附的权利要求的保护范围。

Claims

权利要求书
1、一种带有绝缘体填充的阱结构的封装基板， 其特征在于， 所述封装基板 具有至少一个阱， 所述阱中填充有绝缘材料形成阱结构， 且所述阱结构的上表 面上具有金属图形。
2、如权利要求 1所述一种带有绝缘体填充的阱结构的封装基板，其特征在 于， 所述金属图形为与所述封装基板的管脚直接相连的金属走线、 贴装表面贴 装器件的焊接焊盘、 基板键合焊盘或倒扣安装半导体芯片的焊球焊盘。
3、如权利要求 2所述一种带有绝缘体填充的阱结构的封装基板，其特征在 于， 所述金属走线为单层或多层的金属走线。
4、一种带有绝缘体填充的阱结构的封装基板制造方法，其特征在于，包括： 在金属框架上制作至少一个阱；
在所述阱中填充绝缘材料形成阱结构， 在填充完绝缘材料后的所述阱结构 的上表面制作金属图形。
5、 如权利要求 4所述一种带有绝缘体填充的阱结构的封装基板制造方法， 其特征在于， 在金属框架上下表面进行掩膜处理， 然后再通过腐蚀或刻蚀在所 述金属框架上制作至少一个阱。
6、 如权利要求 5所述一种带有绝缘体填充的阱结构的封装基板制造方法， 其特征在于， 在填充完绝缘材料后的所述阱结构的上表面通过电镀金属或淀积 金属方式制作金属图形。
7、 如权利要求 6所述一种带有绝缘体填充的阱结构的封装基板制造方法， 其特征在于， 所述金属图形进一步为与所述封装基板的管脚直接相连的金属走 线、 贴装表面贴装器件的焊接焊盘、 基板键合焊盘或倒扣安装半导体芯片的焊 球焊盘。
8、如权利要求 6或 7中任一所述一种带有绝缘体填充的阱结构的封装基板 制造方法， 其特征在于， 所述金属图形被绝缘材料覆盖。
9、 如权利要求 7所述一种带有绝缘体填充的阱结构的封装基板制造方法， 其特征在于， 所述金属走线进一步为单层或多层的金属走线。
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