WO2020191616A1 - 具有随机信号发生器件的集成装置、制备方法及电子设备 - Google Patents

具有随机信号发生器件的集成装置、制备方法及电子设备 Download PDF

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Publication number
WO2020191616A1
WO2020191616A1 PCT/CN2019/079684 CN2019079684W WO2020191616A1 WO 2020191616 A1 WO2020191616 A1 WO 2020191616A1 CN 2019079684 W CN2019079684 W CN 2019079684W WO 2020191616 A1 WO2020191616 A1 WO 2020191616A1
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Prior art keywords
layer
chip
pad
pads
random signal
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PCT/CN2019/079684
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English (en)
French (fr)
Inventor
陆斌
沈健
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2019/079684 priority Critical patent/WO2020191616A1/zh
Priority to CN201980000484.0A priority patent/CN112005496A/zh
Publication of WO2020191616A1 publication Critical patent/WO2020191616A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/84—Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Definitions

  • the embodiments of the present invention relate to the field of electronics, and more specifically, to an integrated device with a random signal generating device, a manufacturing method, and electronic equipment.
  • Random numbers are the core of computer security and encryption.
  • a device that can generate high-quality true random numbers is the key to ensuring system security.
  • TRNG True Random Number Generator
  • An integrated device, a manufacturing method and electronic equipment with a random signal generating device are provided, which can simplify the design of the random signal generating device, improve its applicability, and have a simple manufacturing process and can reduce costs.
  • an integrated device with a random signal generating device including:
  • a chip, the chip is provided with a plurality of pads
  • the random signal generating device includes:
  • At least one pad of the plurality of pads At least one pad of the plurality of pads
  • part or all of the pads of the chip can be used as an electrode plate of the random signal generating device, which can not only realize the integration of the random signal generating device into the chip, but also save the circuit between the random signal generating device and the chip. Connection, thereby reducing the complexity of the integrated device and simplifying its structure.
  • an electronic device including:
  • the integrated device with random signal generating device described in the first aspect is the integrated device with random signal generating device described in the first aspect.
  • a method for preparing an integrated device with a random signal generating device including:
  • the resistance conversion layer and the upper electrode plate are removed.
  • the random signal generating device by using part or all of the pads of the chip as an electrode plate of the random signal generating device, not only can the random signal generating device be integrated into the chip, but also the random signal generating device and the chip can be saved. Circuit connection, thereby reducing the complexity of the integrated device and simplifying its structure. In addition, fabricating random signal generating devices directly on the pads of the chip can simplify the fabrication process, thereby reducing costs.
  • an electronic device including:
  • An integrated device with random signal generating device prepared based on the method described in the third aspect.
  • 1 to 4 are schematic structural diagrams of an integrated device with a random signal generating device according to an embodiment of the present application.
  • FIG. 5 is a schematic flowchart of a method for preparing an integrated device with a random signal generating device according to an embodiment of the present application.
  • the embodiment of the application provides an integrated device including a random signal generating device (also called a True Random Number Generator (TRNG)), a preparation method of the integrated device, and an electronic device including the integrated device.
  • TRNG Random Signal Generator
  • the integrated device including TRNGs may include one or more TRNGs that can be used to generate random signals, and the random signals can be used to generate random numbers for encryption or decryption.
  • the integrated device including the TRNG in the embodiment of the present application can simplify the design of the TRNG and improve the applicability.
  • the integrated device in the embodiment of the present application can be applied to any chip that requires security protection.
  • the integrated device including TRNG may be a fingerprint chip including TRNG.
  • the TRNG may be used to generate a random signal
  • the fingerprint chip may be used to After the light signal reflected or scattered by the upper finger and fingerprint information is generated based on the light signal, the fingerprint signal can be encrypted based on the random signal generated by TRNG to form encrypted fingerprint information, and then the encrypted fingerprint information is sent Give the image processing unit or the processor of the electronic device to ensure the security of fingerprint information, especially for remote fingerprint authentication scenarios, to ensure the secure transmission of fingerprint information.
  • the image processing unit or the processor of the electronic device receives the encrypted fingerprint information, it can decrypt the encrypted fingerprint information based on the random signal.
  • the integrated device can be used as a biometric sensor, such as an optical fingerprint sensor, to implement biometric sensing operations. Specifically, when the user places a finger on the top of the display screen, the integrated device receives the optical signal formed by the reflection of the finger, converts the optical signal into an electrical signal, and encrypts the electrical signal. The electrical signal can reflect the fingerprint information of the user's finger.
  • a biometric sensor such as an optical fingerprint sensor
  • the area where the integrated device is located is the sensing area of the integrated device.
  • the sensing area may be located below the display area of the display screen. Therefore, when the user needs to unlock the terminal device or perform other biometric verification, he only needs to press his finger on the display screen, which is located on the display screen.
  • the integrated device in the sensing area can perform fingerprint sensing operations.
  • the integrated device being a biometric sensor is only an example of this application, and this application is not limited to this.
  • the integrated device can be applied to any chip with TRNG, such as a chip of an electronic device or a chip of an internal component of an electronic device.
  • Fig. 1 is a schematic structural diagram of an integrated device according to an embodiment of the present application.
  • the integrated device may include a chip 20 and a random signal generating device 10.
  • the random signal generating device 10 is used to generate a random signal, and the random signal is used to ensure that the chip 20 receives or sends data safely.
  • the random signal is used to encrypt data generated by the chip 20 or to decrypt encrypted data received by the chip 20.
  • the chip 20 may be provided with multiple pads, and the multiple pads may be uniformly or unevenly distributed on any surface of the chip. Some or all of the plurality of pads can be used as an electrode plate of the random signal generating device 10, thus, it is not only possible to integrate the random signal generating device 10 into the chip without increasing the chip area. 20, and can save the circuit connection between the random signal generating device 10 and the chip 20, thereby reducing the complexity of the integrated device and simplifying its structure.
  • the chip 20 may be provided with three pads 232.
  • the random signal generating device 10 may include a resistance conversion layer 12 and an upper electrode plate 14.
  • the resistance conversion layer 12 is disposed on the pad 232 and the upper electrode. Between the plates 14.
  • the material of the upper electrode plate 14 may be an active material layer, and the resistance conversion layer 12 is disposed between the pad 232 and the active material layer. At this time, the pad 232 acts as the random signal generator.
  • the lower electrode 11 of the device 10 and the active material layer serve as the upper electrode of the random signal generating device 10.
  • the upper electrode plate 14 may be provided on the upper surface of the resistance conversion layer 12 in the form of a pad, a metal layer, a metal wire or other forms, which is not specifically limited in this application.
  • the resistance conversion layer 12 is provided between the pad 232 and the upper plate 14, when a predetermined threshold voltage is applied between the pad 232 and the upper plate 14, the pad 232 The resistance conversion layer 12 and the upper plate 14 are similar to a capacitor. After a period of time, the pad 232, the resistance conversion layer 12 and the upper plate 14 will be converted into a resistor. At this time, the resistance conversion layer 12 There is a current used to generate a random signal.
  • the random signal generating device 10 can also use other working principles to generate a random signal, which is not specifically limited in this application.
  • the resistance conversion layer may be a silicon oxide layer, a silicon nitride layer or a silicon oxynitride layer, which includes an active material whose atomic ratio is a preset threshold, such as an active metal.
  • the preset threshold value ranges from 0.1% to 50%.
  • the thickness of the resistance conversion layer ranges from 5 nm to 10 nm.
  • the active metal is preferably silver (Ag), but also metals such as copper (Cu), calcium (Ca), gold (Au), platinum (Pt), etc.
  • the active material can also be other types of materials, as long as its function is the same or similar to that of the active metal.
  • the resistance conversion layer is a 10 nm thick silicon oxide layer containing Ag with an atomic ratio of about 20%.
  • the random signal generating device 10 may further include an active material layer 13 to improve the performance of the random signal generating device 10.
  • the active material layer 13 may be disposed between the resistance conversion layer 12 and the upper electrode plate 14. Of course, the active material layer 13 may also be disposed between the pad 232 and the resistance conversion layer 12, that is, in the structure shown in FIG. 1, the resistance conversion layer 12 and the active material The position of layer 13 can be interchanged, which is not specifically limited in this application.
  • the thickness of the active material layer 13 may be less than the thickness of the resistance conversion layer 12, and may also be greater than or equal to the thickness of the resistance conversion layer 12, which is not specifically limited in this application.
  • the active material layer 13 may be the aforementioned active metal, for example, the active material layer may be Ag with a thickness of 5 nm.
  • FIG. 1 is only an example of this application and should not be construed as a limitation to this application.
  • the integrated device may include a plurality of resistance conversion layers 12 and a plurality of active material layers 13 including a plurality of active material layers. In this case, the plurality of resistance conversion layers 12 and the plurality of active material layers 13 Alternate settings.
  • the chip in the embodiment of the present application may be any chip with pads, and the chip 20 will be exemplified below with reference to FIG. 1.
  • the chip 20 may include a substrate 21, a device layer 22 and a third insulating layer 23.
  • the base 21 may also be referred to as a substrate or a substrate.
  • the device layer 22 is disposed above the substrate 21; the third insulating layer 23 is disposed above the device layer 22, and a second connection layer 231 is disposed inside the third insulating layer 23.
  • the second connection layer 231 is used to connect external devices, and/or the second connection layer 231 is used to connect devices of the device layer in different regions, and the third insulating layer 23 is away from the device layer 22
  • a third opening is formed on the surface of the third opening for exposing the second connection layer 231, and a pad 232 is provided at the third opening.
  • the chip 20 may be a chip with a pad (Pad) prepared on one surface before entering the integrated process, for example, the pad 232 shown in FIG.
  • the second connection layer 231 (including at least one connection line) of the third insulating layer 23 is electrically connected to the device layer 22.
  • the pad 232 can be understood as a pin connecting the chip 20 to the outside world.
  • the upper surface of the chip 20 is the surface where the pads have been prepared before entering the integrated process flow, and the surface opposite to the upper surface of the chip 20 is the lower surface of the substrate 21 of the chip 20 .
  • the material of the substrate 21 may be a standard substrate material involved in integrated circuit manufacturing or thin film technology, and the specific material model of the substrate 21 is not limited in the embodiment of the present application.
  • silicon wafers, glass materials or polyimide materials for example, silicon wafers, glass materials or polyimide materials.
  • the device layer 22 may be various doped regions prepared on the substrate 21 and/or various thin films deposited to form various devices with different functions and/or circuits.
  • n-type or p-type doped wells, dielectric layers and metal electrode layers form transistors, capacitors, resistors, and amplifiers.
  • the embodiment of the present application does not specifically limit the manufacturing process of the device layer 22.
  • the manufacturing process of the device layer 22 may be a prior art manufacturing process.
  • the number of layers of the second connection layer 231 may be determined according to the connection requirements between the various layers inside the device layer 22 and the connection requirements between the various layers inside the device layer 22 and external devices. However, this application does not limit the specific number of layers.
  • the integrated device may also be provided with at least one connecting terminal, the at least one connecting terminal is connected to the exposed pad of the chip 20 and the random signal generating device 10 by a gold wire, and the at least one connecting terminal is used for electrical Connect to external devices.
  • the base 21 may be provided with the at least one connection terminal.
  • metal bumps can also be directly provided on the exposed pads of the chip 20 and the upper electrode positions of the random signal generating device 10, and the metal bumps are used to electrically connect to external devices. This allows the integrated device to be electrically interconnected and signal transmission with other peripheral circuits or other elements of the equipment to which the integrated device belongs.
  • Fig. 2 is another example of the integrated device of the present application.
  • the integrated device may include a first insulating layer 24 in addition to the chip 20 and the random signal generating device 10 shown in FIG. 1.
  • the first insulating layer 24 may be disposed above the chip 20.
  • the first insulating layer 24 is provided with a first opening passing through the first insulating layer 24 at the position of the pad 232, and the first opening is used to expose the pad 232, and the pad 232 is When the random signal generating device 10 is provided, the first opening is used to expose the random signal generating device 10.
  • the shape of the first opening is an inverted trapezoid.
  • the first opening on the cross section of the first insulating layer 24 may also have a square or rectangular shape, which is not specifically limited in the embodiment of the present application.
  • Fig. 3 is another example of the integrated device of the present application.
  • the integrated device may include the chip 20, the random signal generating device 10 and the first insulating layer 24 as shown in FIG. 2, and may also include a first connection layer 31.
  • the first connection layer 31 may be disposed above the first insulating layer 24, one end of the first connection layer 31 is connected to the random signal generating device 10, and the other end of the first connection layer 31 is connected to the The exposed pads of the chip 20 are connected. As a result, the connection distance between the random signal generating device 10 and the chip 20 can be reduced, thereby improving the working efficiency of the integrated device.
  • Fig. 4 is another example of the integrated device of the present application.
  • the integrated device may include the chip 20, the random signal generating device 10, the first insulating layer 24, and the first connection layer 31 as shown in FIG. 3, and may also include a second insulating layer 32.
  • the first connection layer 31 is provided between the first insulating layer 24 and the second insulating layer 32.
  • the second insulating layer 32 is provided with a second opening passing through the second insulating layer 24 at the position of the first pad, and the second opening is used to expose the first pad, and the first The pads include pads on the chip 20 excluding the pads connected to the random signal generating device 10 and the pads provided with the random signal generating device 10.
  • the second opening is used to expose the pads on the chip 20 other than the pads connected to the random signal generating device 10 and the pads provided with the random signal generating device 10 .
  • the shape of the second opening is an inverted trapezoid.
  • the second opening may also be rectangular and square in the cross section of the second insulating layer 32, which is not specifically limited in the embodiment of the present application.
  • the size of the second opening on the surface of the second insulating layer 32 close to the first insulating layer 24 may be equal to or similar to the size of the first opening on the first insulating layer 24. The size of the opening close to the surface of the second insulating layer 32.
  • the electronic device may be various types of devices including the integrated device.
  • the electronic device may be a terminal device such as a TV, a mobile phone, a tablet computer, or an e-book.
  • FIG. 5 is a schematic flowchart of a method for preparing an integrated device with a random signal generating device according to an embodiment of the present application.
  • the method 40 for preparing an integrated device may include:
  • a resistance conversion layer and an upper electrode plate are formed on the surface of the chip provided with a plurality of pads, and the resistance value conversion layer is arranged between at least one of the plurality of pads and the upper electrode plate. That is, the resistance conversion layer is arranged between the at least one pad and the upper electrode plate.
  • the resistance conversion layer and the upper electrode plate may be formed on the surface of the chip provided with pads by a deposition process or an electroplating process.
  • the deposition process includes, but is not limited to, a physical vapor deposition (Physical Vapor Deposition, PVD) process and/or a chemical vapor deposition (Chemical Vapor Deposition, CVD) process.
  • the resistance conversion layer is a silicon oxide layer, a silicon nitride layer or a silicon oxynitride layer, which includes an active metal whose atomic ratio is a preset threshold.
  • the preset threshold value ranges from 0.1% to 50%.
  • the thickness of the resistance conversion layer ranges from 5 nm to 10 nm.
  • a resistance conversion layer, an active material layer and an upper plate may be formed on the surface of the chip provided with a plurality of pads, wherein the resistance conversion layer and the active material The layer is arranged between the at least one pad and the upper electrode plate. The positions of the resistance conversion layer and the active material layer can be interchanged.
  • step S40 optionally, after alternately forming a plurality of conversion layers and a plurality of active material layers on the surface of the chip provided with a plurality of pads, the upper electrode plate may be formed.
  • step S40 taking the integrated device including an active material layer as an example, first, by using a PVD or CVD process, a resistance conversion layer, an active material layer, and an upper electrode are sequentially deposited on the surface of the chip provided with the pad.
  • the resistance conversion layer may be silicon oxide, silicon nitride or silicon oxynitride, which may contain a certain proportion (0.1%-50%) of active metal.
  • the active metal is preferably silver (Ag), but also metals such as copper (Cu), calcium (Ca), gold (Au), platinum (Pt), etc.
  • the resistance conversion layer is a 10 nm-thick silicon oxide layer containing about 20 atomic% Ag, and the active material layer may be 5 nm-thick Ag.
  • the method 40 may further include:
  • the resistance conversion layer and the upper electrode plate are removed. That is, after step S40 is completed, photolithography combined with an etching process can be used to retain the film structure of the resistance conversion layer and the upper plate (and the active material layer) at the predetermined one or several pad positions, and remove the remaining area The film structure.
  • an etching process or a stripping process may be used to remove the resistance conversion layer and the upper electrode plate at a position other than at least one pad of the chip.
  • the etching process may include at least one of the following processes: a dry etching process, a wet etching process, and a laser etching process.
  • the dry etching process may include at least one of the following etching processes: using tetrafluoromethane (CF 4 ) and sulfur hexafluoride (SF 6 ) as etching gas ) Reactive ion etching (reactive ion etching), plasma etching (plasma etching) and ion beam etching (ion beam etching).
  • the etching rate can be changed by changing the mixing ratio of the etching gas.
  • the chemical raw materials of the wet etching process may include, but are not limited to, an etching solution containing hydrofluoric acid.
  • an etching method combining dry etching and wet etching, or laser etching combined with wet etching can effectively ensure the shape of the etching and the flatness of the bottom surface Wait.
  • step S41 using a lift-off process to remove the resistance conversion layer and the upper electrode plate at a position other than at least one pad of the chip as an example, firstly, a plurality of solder joints are provided. The surface of the chip of the pad is spin-coated with a layer of photoresist; then through exposure and development, the photoresist gap is opened at the predetermined pad position; then the resistance conversion layer and the upper electrode plate are deposited; and finally removed Photoresist and a film layer covering it to obtain the integrated device.
  • the original pad of the chip is used as the bottom electrode, and a random signal generating device is fabricated on the pad by depositing or electroplating a resistance conversion layer, an active material layer, and an upper electrode, combined with an etching process. Finally, connect the random signal generating device to the prefabricated peripheral circuit on the chip to realize the complete function of the random signal generating device.
  • the method 40 shown in FIG. 5 may further include:
  • a first insulating layer is formed on the chip; the first insulating layer is provided with a first opening at the position of the plurality of pads, and the first opening is used to expose the plurality of pads except for the at least A pad other than the pad and the random signal generating device.
  • the shape of the first opening is an inverted trapezoid.
  • the method 40 shown in FIG. 5 may further include:
  • a first connection layer is formed on the first insulating layer; one end of the first connection layer is connected to the random signal generating device, and the other end of the first connection layer is connected to the exposed pad of the chip .
  • the method 40 shown in FIG. 5 may further include:
  • a second insulating layer is formed on the first connection layer; the second insulating layer is provided with a second opening passing through the second insulating layer at the position of the first pad, and the second opening is used for The first pad is exposed, and the first pad includes the at least one of the plurality of pads and a pad other than the pad connected to the random signal generating device.
  • the shape of the second opening is an inverted trapezoid.
  • the method 40 shown in FIG. 5 may further include:
  • a third insulating layer and a second connection layer are formed on the device layer.
  • the second connection layer is disposed inside the device layer
  • the third insulating layer is formed with a third opening on the surface away from the device layer, and the third opening is used to expose the second connection
  • the third opening is provided with pads
  • the second connection layer is used to connect external devices
  • the second connection layer is used to connect devices on the device layer in different regions.
  • the substrate may be a semiconductor substrate, and the material of the semiconductor substrate includes, but is not limited to: silicon, germanium, III-V elements (silicon carbide (SiC), gallium nitride (GaN), and gallium arsenide (GaAs)) Etc.), or a combination of the above different materials.
  • the semiconductor substrate may also include an epitaxial layer structure, such as a silicon-on-insulator (SOI) structure, for insulating the substrate.
  • SOI silicon-on-insulator
  • the semiconductor substrate can be a whole wafer or a part cut from the wafer.
  • the device layer is inside and on the upper surface of the semiconductor substrate.
  • the device layer may include a variety of semiconductor devices (transistors, capacitors, etc.) manufactured by existing integrated circuit processing techniques such as photolithography, doping, etching, oxidation, and deposition. Etc.), used to realize chip logic operations, storage and other functions.
  • the third insulating layer is an insulating material layer located on the upper surface of the semiconductor substrate. Its implementation methods include but are not limited to: thermal oxidation, chemical vapor deposition CVD (Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition, LPCVD), etc. ), Atomic layer deposition (ALD), spin coating or spray coating.
  • thermal oxidation chemical vapor deposition CVD (Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition, LPCVD), etc.
  • Atomic layer deposition (ALD) Atomic layer deposition
  • insulating materials include but are not limited to: silicon dioxide (SiO 2 ), cloth glass (spin-on-glass, SOG), silicon-containing glass (USG, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphorus Silicon glass (Boro-phospho-silicate Glass, BPSG), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbide (SiCO), carbon nitride (CN x ), polyimide (Polyimide) ), Parylene, benzocyclobutene (BCB), etc., of course, can also be a combination of the above-mentioned multiple materials.
  • the second connection layer is arranged inside the third insulating layer and is used to connect different regions (or different devices) of the device layer to realize electrical interconnection of the chips.
  • the processes that can be used to make the second connection layer include but are not limited to: PVD, Metal-organic Chemical Vapor Deposition (MOCVD), electroplating, Damascus process, etc.
  • the material can be heavily doped polysilicon, or various metals such as aluminum, tungsten, copper, titanium, gold, etc., it can also be low-resistivity compounds such as titanium nitride, tantalum nitride, or the above-mentioned conductive materials combination.
  • the method 40 shown in FIG. 5 may further include:
  • the process of packaging the integrated device can adopt an existing process, which is not specifically limited in this application.
  • At least one connecting terminal and a gold wire may be formed on the substrate, the at least one connecting terminal is connected to the exposed pad of the chip and the random signal generating device through the gold wire, and the at least one connecting terminal is used for To be electrically connected to external devices.
  • wire bonding can be used to connect the pad of the chip and the upper electrode of the random signal generating device to the lead frame with gold wires.
  • plastic packaging is used to obtain integrated TRNG semiconductor chips.
  • metal bumps are formed at the exposed pads of the chip and the upper electrode positions of the random signal generating device, and the metal bumps are used to electrically connect to external devices.
  • solder balls or metal bumps are made at the upper electrode of the pad and the random signal generating device, and finally the chip is soldered to the circuit board or substrate in the form of an inverted pile to complete the package.
  • the various embodiments of the method 40 for preparing an integrated device listed above can be executed by a robot or a numerical control processing method, and the equipment software or process used to execute the method 40 can be executed by executing a computer program stored in a memory. Code to perform the above method 40.
  • the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, rather than corresponding to the embodiments of the present application.
  • the implementation process constitutes any limitation.
  • the disclosed integrated device, the components in the integrated device, and the method for preparing the integrated device can be implemented in other ways.
  • the integrated device embodiments described above are only exemplary.
  • the division of the layers is only a logical function division, and there may be other division methods in actual implementation.
  • multiple layers or devices may be combined or integrated, for example, the upper electrode plate and the active material layer may be combined into one layer. Or some features (such as the active material layer) can be ignored or not prepared.

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Abstract

提供了一种具有随机信号发生器件的集成装置、制备方法及电子设备，所述集成装置包括：芯片，所述芯片设置有多个焊盘；随机信号发生器件；其中，所述随机信号发生器件包括：所述多个焊盘中的至少一个焊盘；阻值转换层和上极板，所述阻值转换层设置在所述至少一个焊盘和所述上极板之间。本申请中，通过在芯片的部分或全部焊盘可以作为所述随机信号发生器件的一个电极板，不仅能够实现将随机信号发生器件集成到芯片，而且能够节省随机信号发生器件和芯片之间的电路连接，进而降低集成装置的复杂度并简化其结构；此外，能够简化制作工艺并降低成本。

Description

具有随机信号发生器件的集成装置、制备方法及电子设备 技术领域
本发明实施例涉及电子领域，并且更具体地，涉及具有随机信号发生器件的集成装置、制备方法及电子设备。
背景技术
随机数是计算机安全、加密的核心。一个能产生高质量真随机数的装置是确保系统安全的关键。
真随机数生成器(True Random Number Generator,TRNG)是一类利用物理过程(热力学噪声、量子现象等)而不是计算机程序来生成随机数的装置。然而，现有技术中的TRNG，大多实现方式复杂，难以实现规模化扩展应用。
发明内容
提供了一种具有随机信号发生器件的集成装置、制备方法及电子设备，能够简化随机信号发生器件的设计，提高其可应用性，并且制作工艺简单，能够降低成本。
第一方面，提供了一种具有随机信号发生器件的集成装置，包括：
芯片，所述芯片设置有多个焊盘；
随机信号发生器件；
其中，所述随机信号发生器件包括：
所述多个焊盘中的至少一个焊盘；
阻值转换层和上极板，所述阻值转换层设置在所述至少一个焊盘和所述上极板之间。
本申请中，通过芯片的部分或全部焊盘可以作为所述随机信号发生器件的一个电极板，不仅能够实现将随机信号发生器件集成到芯片，而且能够节省随机信号发生器件和芯片之间的电路连接，进而降低集成装置的复杂度并简化其结构。
第二方面，提供了一种电子设备，包括：
第一方面所述的具有随机信号发生器件的集成装置。
第三方面，提供了一种制备具有随机信号发生器件的集成装置的方法，包括：
在芯片的设置有多个焊盘的表面形成阻值转换层和上极板，所述阻值转换层设置在所述多个焊盘中的至少一个焊盘和所述上极板之间；
在所述芯片的至少一个焊盘之外的位置，去除所述阻值转换层和所述上极板。
本申请中，通过将芯片的部分或全部焊盘可以作为所述随机信号发生器件的一个电极板，不仅能够实现将随机信号发生器件集成到芯片，而且能够节省随机信号发生器件和芯片之间的电路连接，进而降低集成装置的复杂度并简化其结构。此外，直接在芯片的焊盘上制作随机信号发生器件，能够简化其制作工艺，进而降低成本。
第四方面，提供了一种电子设备，包括：
基于第三方面所述的方法制备的具有随机信号发生器件的集成装置。
附图说明
图1至图4是本申请实施例的具有随机信号发生器件的集成装置的示意性结构图。
图5是本申请实施例的制备具有随机信号发生器件的集成装置的方法的示意性流程图。
具体实施方式
本申请实施例提供了一种包括随机信号发生器件(也称真随机数生成器(True Random Number Generator，TRNG))的集成装置、该集成装置的制备方法以及包括该集成装置的电子设备，所述包括TRNG的集成装置可以包括一个或多个TRNG，所述TRNG能够用于生成随机信号，所述随机信号可以用于生成用于加密或解密的随机数。
本申请实施例的包括TRNG的集成装置能够简化TRNG的设计，提高可应用性。
本申请实施例中的集成装置可以应用于任何需要安全保障的芯片。
以所述集成装置应用于指纹芯片为例，所述包括TRNG的集成装置可以是包括TRNG的指纹芯片，此时，所述TRNG可以用于生成随机信号，所 述指纹芯片用于接收经由显示屏上方的手指反射或散射的光信号，并基于该光信号生成指纹信息后，可以基于TRNG生成的随机信号对所述指纹信号进行加密，形成加密后的指纹信息，然后将加密后的指纹信息发送给图像处理单元或电子设备的处理器，以保证指纹信息的安全性，特别是针对远距离指纹认证的场景，能够保证指纹信息的安全传输。类似地，所述图像处理单元或电子设备的处理器接收到加密后的指纹信息后，可以基于所述随机信号对加密后的指纹信息进行解密。
或者说，所述集成装置可以作为生物特征传感器，例如光学指纹传感器，用于实现生物特征感应操作。具体地，用户将手指放置于显示屏的上方时，所述集成装置接收到经由手指反射后形成的光信号，并将所述光信号转化为电信号后对所述电信号进行加密，所述电信号能够反映用户手指的指纹信息。
在指纹识别过程中，所述集成装置的所在区域为所述集成装置的感应区域。所述感应区域可以位于显示屏的显示区域的下方，由此，用户在需要对所述终端设备进行解锁或者其他生物特征验证的时候，只需要将手指按压在位于所述显示屏上，位于所述感应区域的集成装置就可以进行指纹感应操作。
应理解，集成装置为生物特征传感器仅为本申请的一种示例，本申请并不限于此。例如，所述集成装置可以应用于具有TRNG的任一芯片，例如电子设备的芯片或者电子设备的内部部件的芯片等。
下面将结合结合图1至图5，详细介绍本申请实施例的集成装置以及制备集成装置的方法。
需要说明的是，为便于说明，在本申请的实施例中，相同的附图标记表示相同的部件，并且为了简洁，在不同实施例中，省略对相同部件的详细说明。应理解，附图示出的本申请实施例中的各种部件的厚度、长宽等尺寸，以及集成装置的整体厚度、长宽等尺寸仅为示例性说明，而不应对本申请构成任何限定。
图1是本申请实施例的集成装置的示意性结构图。
如图1所示，所述集成装置可以包括芯片20和随机信号发生器件10。随机信号发生器件10用于生成随机信号，所述随机信号用于保证所述芯片20安全接收或发送数据。例如，所述随机信号用于对所述芯片20生成的数 据加密或者对所述芯片20接收的到加密数据进行解密。
本申请中，所述芯片20可以设置有多个焊盘，所述至多个焊盘可以均匀地或者不均匀地分布在芯片的任一表面。所述多个焊盘中的部分或全部焊盘可以作为所述随机信号发生器件10的一个电极板，由此，不仅能够实现在不增加芯片面积的基础上将随机信号发生器件10集成到芯片20，而且能够节省随机信号发生器件10和芯片20之间的电路连接，进而降低集成装置的复杂度并简化其结构。
请继续参见图1，所述芯片20可以设置有3个焊盘232。
以设置在中间的焊盘232为例，所述随机信号发生器件10可以包括阻值转换层12和上极板14，所述阻值转换层12设置在所述焊盘232和所述上极板14之间。所述上极板14的材料可以是活性材料层，所述阻值转换层12设置在所述焊盘232和所述活性材料层之间，此时所述焊盘232作为所述随机信号发生器件10的下电极11，所述活性材料层作为所述随机信号发生器件10的上电极。
所述上极板14可以以焊盘、金属层、金属线或者其他形式设置在所述阻值转换层12的上表面，本申请对此不做具体限定。
由于所述焊盘232和所述上极板14之间设置有所述阻值转换层12，在所述焊盘232和上极板14之间施加预定阈值的电压时，所述焊盘232、阻值转换层12和上极板14类似一个电容，在经过一段时间后，所述焊盘232、阻值转换层12和上极板14会转换为一个电阻，此时阻值转换层12存在用于生成随机信号的电流。
当然，随机信号发生器件10也可以采用其他工作原理生成随机信号，本申请对此不做具体限定。
所述阻值转换层可以为氧化硅层、氮化硅层或氮氧化硅层，其包括原子比例为预设阈值的活性材料，例如活性金属。可选地，所述预设阈值的范围为0.1％～50％。可选地，所述阻值转换层的厚度范围为5nm～10nm。所述活性金属优选是银(Ag)，还可以是铜(Cu)、钙(Ca)、金(Au)、铂(Pt)等金属。当然，所述活性材料也可以是其它类型的材料，只要其功能与活性金属的功能相同或类似。优选地，阻值转换层是10nm厚的含有约20％原子比例的Ag的氧化硅层。
请继续参见图1，所述随机信号发生器件10还可以包括活性材料层13， 以提升所述随机信号发生器件10的性能。
所述活性材料层13可以设置在所述阻值转换层12和所述上极板14之间。当然，所述活性材料层13也可以设置在所述焊盘232和所述阻值转换层12之间，即在图1所示的结构中，所述阻值转换层12和所述活性材料层13的位置可以互换，本申请对此不做具体限定。
所述活性材料层13的厚度可以小于所述阻值转换层12的厚度，也可以大于或等于所述阻值转换层12的厚度，本申请对此不做具体限定。所述活性材料层13可以是前文所述的活性金属，例如，所述活性材料层可以是5nm厚的Ag。
应理解，图1仅为本申请的一个示例，不应理解为对本申请的限制。
例如，在其他可替代实施例中，芯片20的多个焊盘可以设置有所述随机信号发生器件10。又例如，所述集成装置可以包括多个阻值转换层12和多个活性材料层13包括多个活性材料层，此时所述多个阻值转换层12和所述多个活性材料层13交替设置。
还应理解，本申请实施例的芯片可以是任一具有焊盘的芯片，下面结合图1对芯片20进行示例性说明。
如图1所示，所述芯片20可以包括基底21、器件层22以及第三绝缘层23。所述基底21也可称为基板或衬底。所述器件层22设置在所述基底21的上方；所述第三绝缘层23设置在所述器件层22的上方，所述第三绝缘层23的内部设置有第二连接层231，所述第二连接层231用于连接外部器件，和/或，所述第二连接层231用于连接所述器件层在不同区域上的器件，所述第三绝缘层23在背离所述器件层22的表面形成有第三开口，所述第三开口用于露出所述第二连接层231，所述第三开口处设置有焊盘232。
本实施例中，芯片20在进入本集成工艺流程之前可以是已经在其一表面制备有焊盘(Pad)的芯片，例如，如图1所示的焊盘232，所述焊盘232通过所述第三绝缘层23的第二连接层231(包括至少一条连接线)电连接至器件层22。所述焊盘232可以理解为芯片20与外界连接的管脚。在本申请实施例中，芯片20的上表面即为进入本集成工艺流程之前表面已制备有焊盘的一面，与所述芯片20的上表面相对的一面即为芯片20的基底21的下表面。
所述基底21的材料可以是集成电路制造或薄膜工艺涉及的标准基底材 料，本申请实施例对基底21的具体材料型号不做限定。例如硅晶圆、玻璃材料或聚酰亚胺材料。
器件层22可以是在基底21上制备的各种不同掺杂区，和/或沉积的各种不同的薄膜，用以形成各种不同功能的器件，和/或电路。例如，n型或p型掺杂井、介电层和金属电极层，形成晶体管、电容、电阻、放大器。应理解，本申请实施例对所述器件层22的制作工艺不做具体限定。例如，所述器件层22的制作工艺可以是现有技术的制作工艺。
第二连接层231的层数可以根据所述器件层22内部各个层之间的连接需求以及所述器件层22内部各个层与外部器件的连接需求确定。但本申请对其具体层数不做限定。
所述集成装置还可以设置有至少一个连接端，所述至少一个连接端通过金线连接至所述芯片20外露的焊盘和所述随机信号发生器件10，所述至少一个连接端用于电连接至外部器件。例如，所述基底21上可以设置有所述至少一个连接端。当然，也可以在所述芯片20外露的焊盘和所述随机信号发生器件10的上电极位置直接设置金属凸点，所述金属凸点用于电连接至外部器件。使得所述集成装置可以与其他外围电路或者所述集成装置所属设备的其他元件的电性互连和信号传输。
图2是本申请的集成装置的另一示例。
如图2所示，所述集成装置除了包括如图1所示的芯片20和随机信号发生器件10之外，还可以包括第一绝缘层24。第一绝缘层24可以设置在所述芯片20的上方。所述第一绝缘层24在所述焊盘232的位置设置有贯通所述第一绝缘层24的第一开口，所述第一开口用于露出所述焊盘232，所述焊盘232上设置有随机信号发生器件10时，所述第一开口用于露出所述随机信号发生器件10。可选地，所述第一开口的形状为倒梯形。当然，所述第一开口在所述第一绝缘层24的截面上也可以为正方形或长方形等形状，本申请实施例对此不做具体限定。
图3是本申请的集成装置的再一示例。
如图3所示，所述集成装置可以包括如图2所示的芯片20、随机信号发生器件10以及第一绝缘层24之外，还可以包括第一连接层31。第一连接层31可以设置在所述第一绝缘层24的上方，所述第一连接层31的一端与所述随机信号发生器件10相连，所述第一连接层31的另一端与所述芯片20的 外露的焊盘相连。由此，能够减少随机信号发生器件10和芯片20之间的连接距离，进而提高所述集成装置的工作效率。
图4是本申请的集成装置的再一示例。
如图4所示，所述集成装置可以包括如图3所示的芯片20、随机信号发生器件10、第一绝缘层24以及第一连接层31之外，还可以包括第二绝缘层32。所述第一连接层31设置在所述第一绝缘层24和所述第二绝缘层32之间。所述第二绝缘层32在所述第一焊盘的位置设置有贯通所述第二绝缘层24的第二开口，所述第二开口用于露出所述第一焊盘，所述第一焊盘包括所述芯片20上的的除与所述随机信号发生器件10相连的焊盘和设置有所述随机信号发生器件10的焊盘之外的焊盘。换句话说，所述第二开口用于露出所述芯片20上的的除与所述随机信号发生器件10相连的焊盘和设置有所述随机信号发生器件10的焊盘之外的焊盘。可选地，所述第二开口的形状为倒梯形。当然，所述第二开口在所述第二绝缘层32的截面上也可以为长方形后正方形，本申请实施例对此不做具体限定。可选地，所述第二开口在所述第二绝缘层32的靠近所述第一绝缘层24的表面的开口尺寸可以等于或近似于所述第一开口在所述第一绝缘层24的靠近所述第二绝缘层32的表面的开口尺寸。
本申请还提供了一种电子设备，所述电子设备可以是包括所述集成装置的各种类型的设备。例如，所述电子设备可以是电视、手机、平板电脑或电子书等终端设备。
图5是本申请实施例的制备具有随机信号发生器件的集成装置的方法的示意性流程图。
如图5所示，所述制备集成装置的方法40可包括：
步骤S40：
在芯片的设置有多个焊盘的表面形成阻值转换层和上极板，所述阻值转换层设置在所述多个焊盘中的至少一个焊盘和所述上极板之间。即所述至少一个焊盘和所述上极板之间设置有所述阻值转换层。
在一些实施例中，可以通过沉积工艺或电镀工艺，在所述芯片的设置有焊盘的表面形成所述阻值转换层和所述上极板。所述沉积工艺包括但不限于物理气相沉积(Physical Vapor Deposition，PVD)工艺和/或化学气相沉积(Chemical Vapor Deposition，CVD)工艺。所述阻值转换层为氧化硅层、氮 化硅层或氮氧化硅层，其包括原子比例为预设阈值的活性金属。可选地，所述预设阈值的范围为0.1％～50％。可选的，所述阻值转换层的厚度范围为5nm～10nm。
在步骤S40中，可选地，可以在所述芯片的设置有多个焊盘的表面形成阻值转换层、活性材料层和上极板，其中，所述阻值转换层和所述活性材料层设置在所述至少一个焊盘和所述上极板之间。所述阻值转换层和所述活性材料层的位置可以互换。
在步骤S40中，可选地，可以在所述芯片的设置有多个焊盘的表面交替形成多个转换层和多个活性材料层后，形成所述上极板。
在步骤S40中，以所述集成装置包括活性材料层为例，首先利用PVD或CVD工艺，在设置有焊盘的芯片的表面依次沉积阻值转换层、活性材料层、上电极。所述阻值转换层可以是氧化硅、氮化硅或氮氧化硅，其可以包含一定比例(0.1％-50％)的活性金属。所述活性金属优选是银(Ag)，还可以是铜(Cu)、钙(Ca)、金(Au)、铂(Pt)等金属。优选地，阻值转换层是10nm厚的含有约20％原子比例的Ag的氧化硅层，所述活性材料层可以是5nm厚的Ag。
请继续参见图5，所述方法40还可包括：
步骤S41：
在所述芯片的至少一个焊盘之外的位置，去除所述阻值转换层和所述上极板。即在步骤S40完成后，可以利用光刻结合刻蚀工艺，在预定的一个或几个焊盘位置，保留阻值转换层和上极板(以及活性材料层)的膜层结构，去除剩余区域的膜层结构。
在一些实施例中，可以采用刻蚀工艺或剥离工艺，在所述芯片的至少一个焊盘之外的位置，去除所述阻值转换层和所述上极板。所述刻蚀工艺可以包括以下工艺中的至少一种：干法刻蚀工艺、湿法刻蚀工艺和激光刻蚀工艺。进一步地，所述干法蚀刻(dry etching)工艺可以包括以下刻蚀工艺中的至少一种：采用将四氟甲烷(CF 4)和六氟化硫(SF 6)用作蚀刻气体(etching gas)的反应性离子蚀刻(reactive ion etching)、等离子体蚀刻(plasma etching)以及离子束刻蚀(ion beam etching)等。可以通过改变蚀刻气体的混合比可以改变蚀刻速度。所述湿法刻蚀工艺的化学原料可以包括但不限于含氢氟酸的刻蚀液。在本申请的一些实施例中，采用干法刻蚀与湿法刻蚀相结合的刻 蚀方法，或者采用激光刻蚀结合湿法刻蚀的方法，能够有效保证刻蚀的形状以及底面平整度等。
在步骤S41中，以采用剥离(Lift-off)工艺在所述芯片的至少一个焊盘之外的位置去除所述阻值转换层和所述上极板为例，首先在设置有多个焊盘(pad)的芯片的表面旋涂一层光刻胶；然后通过曝光、显影，在预定的pad位置打开光刻胶缺口；接着沉积所述阻值转换层和所述上极板；最后去除光刻胶及覆盖在其上方的膜层，得到所述集成装置。
本申请中，以芯片原本的焊盘作为下电极，通过沉积或电镀阻值转换层、活性材料层、上电极，并结合刻蚀工艺，在焊盘上制作随机信号发生器件。最后，将随机信号发生器件连接至芯片上预制的外围电路，进而实现完整的随机信号发生器件功能。
在一些实施例中，图5所示的方法40还可包括：
在所述芯片上形成第一绝缘层；所述第一绝缘层在所述多个焊盘的位置设置有第一开口，所述第一开口用于露出所述多个焊盘除所述至少一个焊盘之外的焊盘和所述随机信号发生器件。可选地，所述第一开口的形状为倒梯形。
在一些实施例中，图5所示的方法40还可包括：
在所述第一绝缘层上形成第一连接层；所述第一连接层的一端与所述随机信号发生器件相连，所述第一连接层的另一端与所述芯片的外露的焊盘相连。
在一些实施例中，图5所示的方法40还可包括：
在所述第一连接层上形成第二绝缘层；所述第二绝缘层在所述第一焊盘的位置设置有贯通所述第二绝缘层的第二开口，所述第二开口用于露出第一焊盘，所述第一焊盘包括所述多个焊盘中的所述至少一个焊盘和与所述随机信号发生器件相连的焊盘之外的焊盘。可选地，所述第二开口的形状为倒梯形。
在一些实施例中，图5所示的方法40在执行步骤S41之前还可包括：
制备芯片。
具体地，在基底上形成器件层后，在所述器件层上形成第三绝缘层和第二连接层。其中，所述第二连接层设置在所述器件层的内部，所述第三绝缘层在背离所述器件层的表面形成有第三开口，所述第三开口用于露出所述第 二连接层，所述第三开口处设置有焊盘，所述第二连接层用于连接外部器件，和/或，所述第二连接层用于连接所述器件层在不同区域上的器件。
应理解，可以利用现有的制备半导体芯片的制备方法制备芯片。本申请对此不做具体限定。
所述基底可以是半导体衬底，所述半导体衬底的材料包括但不限于：硅、锗、III-V族元素(碳化硅(SiC)、氮化镓(GaN)以及砷化镓(GaAs)等)，或上述不同材料的组合。所述半导体衬底还可以包含外延层结构，例如硅晶绝缘体(silicon-on-insulator，SOI)结构，用于绝缘所述衬底。所述半导体衬底可以是一整片晶圆，也可以是从晶圆截取的一部分。
所述器件层为在半导体衬底内部及上表面，所述器件层可以包括通过光刻、掺杂、刻蚀、氧化、沉积等已有集成电路加工工艺制作的多种半导体器件(晶体管、电容等)，用以实现芯片逻辑运算、存储等功能。
所述第三绝缘层为位于在半导体衬底上表面的绝缘材料层。其实现方式包括但不限于：热氧化、化学气相沉积CVD(等离子体增强化学的气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)、低压力化学气相沉积法(Low Pressure Chemical Vapor Deposition，LPCVD)等)、原子层沉积(Atomic layer deposition，ALD)、旋涂或喷涂。其绝缘材料包括但不限于：二氧化硅(SiO 2)、布玻璃(spin-on-glass，SOG)、含硅玻璃(USG，磷硅玻璃(PSG)，硼硅玻璃(BSG)，硼磷硅玻璃(Boro-phospho-silicate Glass，BPSG))、氮化硅(SiN)、碳氮化硅(SiCN)、碳氧化硅(SiCO)、氮化碳(CN x)、聚酰亚胺(Polyimide)、帕里纶(Parylene)、苯并环丁烯(BCB)等，当然也可以是上述多种材料的组合。
所述第二连接层设置在第三绝缘层内部，用于连接器件层的不同区域(或不同器件)，用以实现芯片的电互联。制作第二连接层可以使用的工艺包括但不限于：PVD、金属有机物化学气相沉积(Metal-organic Chemical Vapor Deposition，MOCVD)、电镀、大马士革工艺等。其材料可以是重掺杂多晶硅，或者是铝、钨、铜、钛、金等各类金属，也可以是氮化钛、氮化钽等低电阻率的化合物，或者是上述几种导电材料的组合。
在一些实施例中，图5所示的方法40还可包括：
封装所述集成装置。
封装所述集成装置的工艺可以采用现有工艺，本申请对其不做具体限 定。
例如，可以在所述基底上形成至少一个连接端和金线，所述至少一个连接端通过金线连接至所述芯片外露的焊盘和所述随机信号发生器件，所述至少一个连接端用于电连接至外部器件。话句话说，可以利用引线键合(wire bonding)的方式，将芯片的pad及随机信号发生器件的上电极，用金线全部连接到引线框架上。最后塑封，得到集成TRNG的半导体芯片。
又例如，在所述芯片外露的焊盘和所述随机信号发生器件的上电极位置，形成金属凸点，所述金属凸点用于电连接至外部器件。换句话说，在pad及随机信号生成器件的上电极处，制作锡球或金属凸点，最后利用倒桩的形式，将芯片焊接到电路板或基板上，完成封装。
应理解，方法实施例与集成装置的实施例可以相互对应，类似的描述可以参照集成装置的具体实施例。为了简洁，在此不再赘述。
还应理解，上述列举的制备集成装置的方法40的各实施例，可以通过机器人或者数控加工方式来执行，用于执行所述方法40的设备软件或工艺可以通过执行保存在存储器中的计算机程序代码来执行上述方法40。
需要说明的是，在不冲突的前提下，本申请描述的各个实施例和/或各个实施例中的技术特征可以任意的相互组合，组合之后得到的技术方案也应落入本申请的保护范围。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的制备方法，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请所提供的几个实施例中，应该理解到，所揭露的集成装置、集成装置内的部件和制备集成装置的方法，可以通过其它的方式实现。例如，以上所描述的集成装置实施例仅仅是示例性的。例如，所述层的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。例如多个层或器件可以结合或者可以集成，例如，所述上极板和所述活性材料层可以合并为 一个层。或一些特征(例如活性材料层)可以忽略或不制备。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (36)

  1. 一种具有随机信号发生器件的集成装置，其特征在于，包括：
    芯片，所述芯片设置有多个焊盘；
    随机信号发生器件；
    其中，所述随机信号发生器件包括：
    所述多个焊盘中的至少一个焊盘；
    阻值转换层和上极板，所述阻值转换层设置在所述至少一个焊盘和所述上极板之间。
  2. 根据权利要求1所述的集成装置，其特征在于，所述集成装置还包括：
    活性材料层；
    所述活性材料层设置在所述至少一个焊盘和所述上极板之间。
  3. 根据权利要求2所述的集成装置，其特征在于，所述集成装置包括多个阻值转换层和多个活性材料层，所述多个转换层和所述多个活性材料层交替设置。
  4. 根据权利要求1至3中任一项所述的集成装置，其特征在于，所述上极板的材料为活性材料。
  5. 根据权利要求1至4中任一项所述的集成装置，其特征在于，所述集成装置还包括：
    第一绝缘层；
    所述第一绝缘层设置在所述芯片的上方，所述第一绝缘层在所述多个焊盘的位置设置有贯通所述第一绝缘层的第一开口，所述第一开口用于露出所述多个焊盘中除所述至少一个焊盘之外的焊盘和所述随机信号发生器件。
  6. 根据权利要求5所述的集成装置，其特征在于，所述第一开口的形状为倒梯形。
  7. 根据权利要求5或6所述的集成装置，其特征在于，所述集成装置还包括：
    第一连接层；
    所述第一连接层设置在所述第一绝缘层的上方，所述第一连接层的一端与所述随机信号发生器件相连，所述第一连接层的另一端与所述芯片的外露的焊盘相连。
  8. 根据权利要求7所述的集成装置，其特征在于，所述集成装置还包括：
    第二绝缘层；
    所述第一连接层设置在所述第一绝缘层和所述第二绝缘层之间，所述第二绝缘层设置有贯通所述第二绝缘层的第二开口，所述第二开口用于露出所述多个焊盘中的除所述至少一个焊盘和与所述随机信号发生器件相连的焊盘之外的焊盘。
  9. 根据权利要求8所述的集成装置，其特征在于，所述第二开口的形状为倒梯形。
  10. 根据权利要求1至9中任一项所述的集成装置，其特征在于，所述芯片包括：
    基底；
    器件层，所述器件层设置在所述基底的上方；
    第三绝缘层，所述第三绝缘层设置在所述器件层的上方，所述第三绝缘层的内部设置有第二连接层，所述第二连接层用于连接外部器件，和/或，所述第二连接层用于连接所述器件层在不同区域上的器件，所述第三绝缘层在背离所述器件层的表面形成有第三开口，所述第三开口用于露出所述第二连接层，所述第三开口处设置有焊盘。
  11. 根据权利要求1至10中任一项所述的集成装置，其特征在于，所述基底设置有至少一个连接端，所述至少一个连接端通过金线连接至所述芯片外露的焊盘和所述随机信号发生器件，所述至少一个连接端用于电连接至外部器件。
  12. 根据权利要求1至10中任一项所述的集成装置，其特征在于，所述芯片外露的焊盘的位置和所述随机信号发生器件的上电极的位置设置有金属凸点，所述金属凸点用于电连接至外部器件。
  13. 根据权利要求1至12中任一项所述的集成装置，其特征在于，所述阻值转换层为氧化硅层、氮化硅层或氮氧化硅层，其包括原子比例为预设阈值的活性材料。
  14. 根据权利要求13所述的集成装置，其特征在于，所述预设阈值的范围为0.1％～50％。
  15. 根据权利要求1至14中任一项的集成装置，其特征在于，所述阻值转换层的厚度范围为5nm～10nm。
  16. 一种电子设备，其特征在于，包括：
    权利要求1至15中任一项所述的集成装置。
  17. 一种制备具有随机信号发生器件的集成装置的方法，其特征在于，包括：
    在芯片的设置有多个焊盘的表面形成阻值转换层和上极板，所述阻值转换层设置在所述多个焊盘中的至少一个焊盘和所述上极板之间；
    在所述芯片的至少一个焊盘之外的位置，去除所述阻值转换层和所述上极板。
  18. 根据权利要求17所述的方法，其特征在于，所述在芯片的设置有多个焊盘的表面形成阻值转换层和上极板，包括：
    在所述芯片的设置有多个焊盘的表面形成阻值转换层、活性材料层和上极板，所述活性材料层设置在所述至少一个焊盘和所述上极板之间。
  19. 根据权利要求18所述的方法，其特征在于，所述在所述芯片的设置有多个焊盘的表面形成阻值转换层、活性材料层和上极板，包括：
    在所述芯片的设置有多个焊盘的表面交替形成多个转换层和多个活性材料层后，形成所述上极板。
  20. 根据权利要求17至19中任一项所述的方法，其特征在于，所述上极板的材料为活性材料。
  21. 根据权利要求17至20中任一项所述的方法，其特征在于，所述方法还包括：
    在所述芯片上形成第一绝缘层；
    所述第一绝缘层在所述多个焊盘的位置设置有贯通所述第一绝缘层的第一开口，所述第一开口用于露出所述多个焊盘除所述至少一个焊盘之外的焊盘和所述随机信号发生器件。
  22. 根据权利要求21所述的方法，其特征在于，所述第一开口的形状为倒梯形。
  23. 根据权利要求21或22所述的方法，其特征在于，所述方法还包括：
    在所述第一绝缘层上形成第一连接层；
    所述第一连接层的一端与所述随机信号发生器件相连，所述第一连接层的另一端与所述芯片的外露的焊盘相连。
  24. 根据权利要求23所述的方法，其特征在于，所述方法还包括：
    在所述第一连接层上形成第二绝缘层，所述第二绝缘层设置有贯通所述第二绝缘层的第二开口，所述第二开口用于露出所述多个焊盘中的除所述至少一个焊盘和与所述随机信号发生器件相连的焊盘之外的焊盘。
  25. 根据权利要求24所述的方法，其特征在于，所述第二开口的形状为倒梯形。
  26. 根据权利要求17至25中任一项所述的方法，其特征在于，所述在芯片的设置有多个焊盘的表面形成阻值转换层和上极板之前，所述方法还包括：
    在基底上形成器件层；
    在所述器件层上形成第三绝缘层和第二连接层，所述第二连接层设置在所述器件层的内部，所述第三绝缘层在背离所述器件层的表面形成有第三开口，所述第三开口用于露出所述第二连接层，所述第三开口处设置有焊盘，所述第二连接层用于连接外部器件，和/或，所述第二连接层用于连接所述器件层在不同区域上的器件。
  27. 根据权利要求17至26中任一项所述的方法，其特征在于，所述方法还包括：
    在所述基底上形成至少一个连接端和金线，所述至少一个连接端通过金线连接至所述芯片外露的焊盘和所述随机信号发生器件，所述至少一个连接端用于电连接至外部器件。
  28. 根据权利要求17至26中任一项所述的方法，其特征在于，所述方法还包括：
    在所述芯片外露的焊盘位置和所述随机信号发生器件的上电极的位置，形成金属凸点，所述金属凸点用于电连接至外部器件。
  29. 根据权利要求17至28中任一项所述的方法，其特征在于，所述阻值转换层为氧化硅层、氮化硅层或氮氧化硅层，其包括原子比例为预设阈值的活性金属。
  30. 根据权利要求29所述的方法，其特征在于，所述预设阈值的范围为0.1％～50％。
  31. 根据权利要求17至30中任一项的方法，其特征在于，所述阻值转换层的厚度范围为5nm～10nm。
  32. 根据权利要求31所述的方法，其特征在于，所述在芯片的设置有多 个焊盘的表面形成阻值转换层和上极板，包括：
    通过沉积工艺或电镀工艺，在所述芯片的设置有多个焊盘的表面形成所述阻值转换层和所述上极板。
  33. 根据权利要求32所述的方法，其特征在于，所述沉积工艺包括：
    物理气相沉积PVD工艺和/或化学气相沉积CVD工艺。
  34. 根据权利要求17至33中任一项所述的方法，其特征在于，所述在所述芯片的至少一个焊盘之外的位置，去除所述阻值转换层和所述上极板，包括：
    采用刻蚀工艺或剥离工艺，在所述芯片的至少一个焊盘之外的位置，去除所述阻值转换层和所述上极板。
  35. 根据权利要求34所述的方法，其特征在于，所述刻蚀工艺包括以下工艺中的至少一种：
    干法刻蚀工艺、湿法刻蚀工艺和激光刻蚀工艺。
  36. 一种具有随机信号发生器件的集成装置，其特征在于，包括：
    根据权利要求17至35中任一项所述的方法制备的具有随机信号发生器件的集成装置。
PCT/CN2019/079684 2019-03-26 2019-03-26 具有随机信号发生器件的集成装置、制备方法及电子设备 WO2020191616A1 (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101010876A (zh) * 2004-06-30 2007-08-01 露崎典平 随机脉冲产生源及使用该源产生随机数和/或概率的半导体器件、方法和程序
US20160028544A1 (en) * 2012-11-15 2016-01-28 Elwha Llc Random number generator functions in memory
CN109165007A (zh) * 2018-05-25 2019-01-08 武汉华芯纳磁科技有限公司 基于自旋轨道耦合效应和热扰动的真随机数发生器

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2768276B1 (fr) * 1997-09-10 2000-06-02 Inside Technologies Generateur d'alea
US6385033B1 (en) * 2000-09-29 2002-05-07 Intel Corporation Fingered capacitor in an integrated circuit
FR2817361B1 (fr) * 2000-11-28 2003-01-24 St Microelectronics Sa Generateur de signal aleatoire
TWI286372B (en) * 2003-08-13 2007-09-01 Phoenix Prec Technology Corp Semiconductor package substrate with protective metal layer on pads formed thereon and method for fabricating the same
EP1624464A1 (en) * 2004-08-05 2006-02-08 STMicroelectronics S.r.l. Built-in self diagnosis device for a random access memory and method of diagnosing a random access memory
US7176781B2 (en) * 2004-09-29 2007-02-13 Agere Systems Inc Structure and method for adjusting integrated circuit resistor value
US7517798B2 (en) * 2005-09-01 2009-04-14 Micron Technology, Inc. Methods for forming through-wafer interconnects and structures resulting therefrom
TWI297941B (en) * 2005-10-13 2008-06-11 Phoenix Prec Technology Corp Semiconductor device with electroless plating metal connecting layer and method for fabricating the same
KR100679270B1 (ko) * 2006-01-27 2007-02-06 삼성전자주식회사 상변화 메모리 소자 및 그 제조방법
JP5452064B2 (ja) * 2009-04-16 2014-03-26 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US8482114B2 (en) * 2009-09-10 2013-07-09 Nxp B.V. Impedance optimized chip system
CN104216678B (zh) * 2014-09-18 2017-11-07 中国科学技术大学 一种无偏真随机数发生器及随机数生成方法
CN106935517B (zh) * 2015-12-31 2019-07-09 深圳市中兴微电子技术有限公司 集成无源器件的框架封装结构及其制备方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101010876A (zh) * 2004-06-30 2007-08-01 露崎典平 随机脉冲产生源及使用该源产生随机数和/或概率的半导体器件、方法和程序
US20160028544A1 (en) * 2012-11-15 2016-01-28 Elwha Llc Random number generator functions in memory
CN109165007A (zh) * 2018-05-25 2019-01-08 武汉华芯纳磁科技有限公司 基于自旋轨道耦合效应和热扰动的真随机数发生器

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