TW201409647A - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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Abstract
一種半導體裝置,包括:一凹口,於兩個相鄰的金屬線之間的一聚合物層中,且凹口位於鈍化保護層上;或者抗電子遷移層於重分佈金屬線之上以提高對電子遷移的阻抗。
Description
本發明係有關於一種半導體裝置及其製造方法。
隨著半導體裝置之最小特徵尺寸的縮小與相鄰的金屬線之間距縮小,可靠度的問題變得更嚴重,例如不合格的高加速溫濕試驗(Highly Accelerated Temperature/Humidity Stress Test,HAST)、電子遷移與應力遷移的增加等問題。裝置尺寸的縮小及金屬的間距與寬度之微縮(scale down)導致電阻與電流密度的增高。較高的電流密度會增加金屬枝晶(dendrites)的生長率而使相鄰的金屬線之間距縮小,最終產生短路。
加大金屬之間距是防止這種短路所產生的內連線失靈的一種方法。而因為裝置會不斷的縮小,加大金屬之間距係不實際的。另一種選擇,可進行不同的表面處理以減少金屬橋接短路,例如,經發現將金屬層暴露於氨(NH3)可減少其界面(interface)上的金屬擴散(diffusion)。加入摻質至金屬層中亦可侷限金屬擴散。遺憾地,這些降低金屬擴散率的技術會大幅地提高金屬層的電阻。
因此,需要一種包含金屬內連線的新結構或製造半導體裝置的改良製程,以減少金屬橋接。
本發明提供一種半導體裝置,包括:一基板;多個層間介電層,於基板上方;多個金屬層,於基板上方;一第一聚合物層,於層間介電層與金屬層上方;其中第一聚合物層具有一第一表面、一第二表面於第一表面的同側、及一第三表面於第一表面之相反側,且第一表面與第二表面之一深度差等於或大於約1 um;多個金屬線,於該第一表面與該第一聚合物層上;以及一第二聚合物層,於金屬線與第一聚合物層上。
本發明又提供一種半導體裝置,包括:一基板;多個層間介電層,於基板上方;多個金屬層,於基板上方;一第一聚合物層,於層間介電層與金屬層上方;多個金屬線,於第一聚合物層之一第一表面上;一第二聚合物層,該些金屬線上;以及一抗電子遷移層,於金屬線之側壁與第二聚合物層之間。
本發明亦提供一種半導體裝置的製造方法,包括:提供一基板;形成多個層間介電層於基板上方;形成多個金屬層於基板上方;形成一第一聚合物層於層間介電層與金屬層上方;形成多個金屬線於第一聚合物層上;形成一凹口於兩個相鄰的金屬線之間的第一聚合物層中,凹口之深度等於或大於約1 um;以及形成一第二聚合物層於該些金屬線上。
100‧‧‧半導體晶粒
158‧‧‧基板
160‧‧‧電子電路
162、168‧‧‧層間介電層
164、170‧‧‧插塞
166、172‧‧‧金屬層
174‧‧‧鈍化保護層
176‧‧‧開口
178‧‧‧第一聚合物層
180‧‧‧重分佈金屬線
182‧‧‧第二聚合物層
184、188‧‧‧導電墊
186‧‧‧導電材料
120、220、320、420、520‧‧‧凹口
310、410、510‧‧‧抗電子遷移層
第1~1-1圖係根據本發明不同實施例繪示出半導體裝置的剖面示意圖。
第2~2-4圖係根據本發明不同實施例繪示出半導體裝置的
剖面示意圖。
第3~3-5圖係根據本發明不同實施例繪示出半導體裝置的剖面示意圖。
第4~4-5圖係根據本發明不同實施例繪示出半導體裝置的剖面示意圖。
第5~5-5圖係根據本發明不同實施例繪示出半導體裝置的剖面示意圖。
第6圖係根據本發明不同實施例繪示出在半導體晶粒中形成凹口與抗電子遷移層之方法的流程圖。
以下說明本發明實施例之製作與使用。然而,可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明,並非用以侷限本發明的範圍。
要瞭解的是本說明書以下的揭露內容提供許多不同的實施例或範例,以實施本發明的不同特徵。而本說明書以下的揭露內容是敘述各個構件及其排列方式的特定範例,以求簡化發明的說明。當然,這些特定的範例並非用以限定本發明。另外,本發明的說明中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的,並非用以限定各個實施例及/或所述外觀結構之間的關係。再者,若是本說明書以下的揭露內容敘述了將一第一特徵形成於一第二特徵之上或上方,即表示其包含了所形成的上述第一特徵與上述第二特徵是直接接觸的實施例,亦包含了尚可將附加
的特徵形成於上述第一特徵與上述第二特徵之間,而使上述第一特徵與上述第二特徵可能未直接接觸的實施例。
在空間上的相關用語,例如”下”、”上”、”水平”、”垂直”、”上方”、”下方”、”向上”、”向下”、”頂部”、”底部”等等及其衍生詞(例如,”水平地”、”向下地”、”向上地”等等)係用以容易表達出本說明書中的特徵與額外特徵的關係。這些空間上的相關用語涵蓋了具有特些特徵的裝置的不同方位。
金屬互連線(interconnection lines)中的應力遷移(stress migration)或電子遷移(electromigration)的特點為被高電流密度誘導的離子移動(movement)。隨著半導體裝置的特徵尺寸縮小,電流密度的增加因而增加了電子遷移所誘導的金屬化的失靈。半導體裝置的特點為高電流密度與在兩個相鄰的重分佈(redistribution)線之間生長金屬枝晶。本發明不同實施例可抑制金屬橋接與增加對電子遷移的電阻。具體地說,在聚合物層中形成凹口或在重分佈線上形成抗電子遷移(anti-electromigration)層。
第1圖係根據本發明一實施例繪示出半導體晶粒結構之剖面示意圖。請參照第1圖,半導體晶粒100包括基板158。一些實施例中,半導體晶粒為矩形或正方形。基板158可為一矽基板。一些實施例中,基板158可為矽覆絕緣體(silicon-on-insulator)、碳化矽、III-V族材料、或藍寶石(sapphire)。基板158可更包括各種電子電路160。形成於基板158上的電子電路160可為任何適合於特定應用的電路。在特定的
實施例中,電子電路160可包括由高介電常數材料製得的各種n型金屬氧化物半導體(NMOS)及/或p型金屬氧化物半導體(PMOS)裝置,高介電常數材料包括矽酸鉿、矽酸鋯、二氧化鉿及二氧化鋯。電子電路160亦可包括其他電晶體,例如鰭式場效電晶體(fin field-effect transistor,FinFET)及其他平面(planar)電晶體、電容器、電阻器、二極體、光二極體(photo-diode)、熔絲(fuse)等。電子電路160可互連以呈現一或多種功能。功能包括記憶(memory)結構、處理(processing)結構、感測器、擴大器(amplifier)、電源分配器、或輸入/輸出電路等。
在電子電路160上形成層間介電層162。層間介電層162可由低介電常數材料所組成,例如摻氟氧化矽,其介電常數為約2.0~4.5。在一些實施例中,低介電常數材料為摻碳氧化矽,其介電常數為約3.0。另一些實施例中,低介電常數材料為多孔摻碳氧化矽,其介電常數為約2.5。又一些實施例中,低介電常數材料為市售SILKTM商標的介電材料或多孔介電材料,其介電常數小於約2.6。在一些實施例中,低介電常數材料亦可為多孔氧化矽,其介電常數小於約2.0。
請參照第1圖,在層間介電層162中形成插塞164,插塞164連接至電子電路160。插塞係由金屬組成,其可為鈦、氮化鈦、鎢、鋁、鉭、銅、或上述之組合。插塞164連接至底金屬層166,底金屬層166係由銅、鋁、鉭、鈦、氮化鈦、鎢、或上述之組合所組成,且底金屬層166係置於層間介電層162中。在金屬層166上設置另一層間介電層168,層間介電層168
係由相似於層間介電層162的低介電常數材料所組成。在層間介電層168中設置頂插塞170,插塞170電性連接至底金屬層166。頂插塞170係由金屬所組成,其可為鎢、銅、氮化鈦、鉭、或上述之合金所組成。頂插塞170連接至頂金屬層172,頂金屬層172係由鋁、銅、鈦、氮化鈦、鎢、或上述之合金所組成。而雖第1圖顯示底金屬層166與頂金屬層172,此技藝具有通常知識者將理解可在底金屬層166與頂金屬層172之間形成一或多個層間介電層(未顯示)與相關的插塞及金屬層(未顯示)。
在頂金屬層172上沉積鈍化保護(passivation)層174。在一些實施例中,鈍化保護層174包括無機材料,例如,未摻雜的矽玻璃、氮化矽、氧化矽、氮氧化矽、摻硼氧化矽、摻磷氧化矽等。在鈍化保護層174中形成開口176以提供外部電性連接。開口176係由微影(photolithography)與蝕刻所形成。在鈍化保護層174上沉積第一聚合物層178。第一聚合物層178係由聚合物材料所製作,例如聚亞醯胺(polyimide)、聚苯噁唑(polybenzoxazole,PBO)、矽氧樹脂(silicone)、苯並環丁烯(benzocyclobutene,BCB)、環氧聚合物(epoxy)、塑形(molding)化合物(例如環氧樹脂)、塑模底膠(molded underfill)(例如樹脂)等。可由習知的任何合適方法製作第一聚合物層178,例如,旋轉塗佈(spin coating)及視需要地進行硬化(curing)步驟。藉由微影(photolithography)與蝕刻製程在第一聚合物層178中形成對應到開口176的開口。在第一聚合物層178上形成重分佈金屬線180,且重分佈金屬線180填入開口176中。重分佈金屬線180可由金屬製成,例如,鈦、氮化鈦、鋁、鉭、銅、或上述之組
合。重分佈金屬線180可由習知的任何合適方法製作,例如濺鍍(sputter)、化學氣相沉積(chemical vapor deposition,CVD)、或電鍍(electroplating)。重分佈金屬線180提供頂金屬層174與半導體晶粒100之上表面之間的導電路徑。取決於沉積的方法,可由微影與蝕刻作圖案化或可選擇性(selectively)地沉積形成重分佈金屬線180。
在重分佈金屬線180與聚合物層178上形成第二聚合物層182。第二聚合物層182係由聚合物材料所形成,例如聚亞醯胺(polyimide)、聚苯噁唑(polybenzoxazole,PBO)、矽氧樹脂(silicone)、苯並環丁烯(benzocyclobutene,BCB)、環氧聚合物(epoxy)、塑形(molding)化合物(例如環氧樹脂)、塑模底膠(molded underfill)(例如樹脂)等。可由習知的任何合適方法製作第二聚合物層182,例如,旋轉塗佈(spin coating)或貼合(lamination)及視需要地進行硬化(curing)步驟。圖案化第二聚合物層182以形成多個開口而暴露出底導電墊188與部份的重分佈金屬線180。在第二聚合物層182中形成頂導電墊184且部分頂導電墊184形成於第二聚合物層182之上,頂導電墊184並連接至底導電墊188。由無電(electro-less,E-less)電鍍形成頂導電墊184。頂導電墊184可具有單層結構或複合層結構,複合結構包括由不同材料形成的多個次層(sub-layer),且可包一或多材料為鈦、銅、鎳、鈀、金、鉭、或上述之組合。一些實施例中,頂導電墊184係由無電鍍鎳鈀化金(Electro-less Nickel Electro-less Palladium Immersion Gold,ENEPIG)所組成,其包括鎳層、位於鎳層上的鈀層、與位於鈀層上的金層。可使用浸
鍍(immersion plating)形成金層。另一些實施例中,可使用其他材料與方法形成頂導電墊184,包括,但不限於,無電鍍鎳化金(Electro-less Nickel Immersion Gold,ENIG)、無電電鍍鎳/電鍍鈀(electro-less nickel electro-less palladium,ENEP)、直接浸金(Direct Immersion Gold,DIG)等。
在導電墊184上提供導電材料186。導電材料186係由焊球(solder ball)、焊料(solder)、微凸塊(micro bump)、銅柱(pillar)、金屬柱、銅柱釘(stud)、金柱釘、或上述之組合所組成。一些實施例中,可使用常用的方法形成焊球,例如,球轉移(transfer)或植球(ball placement)。另一些實施例中,導電材料186係由微凸塊所組成,例如銅、錫、鎳、鈦、鉭、焊料、或上述之組合,且可由微影與電鍍(electroplating)或無電電鍍(plating)形成微凸塊。又一些實施例中,導電材料186係由金屬柱所組成,例如鈦、錫、焊料、銅、鉭、鎳、或上述之組合,且可由微影與電鍍(electroplating)或其他電鍍形成微凸塊。
第1-1圖為第1圖中的區域A之詳細圖。在第一聚合物層178中的兩個相鄰的重分佈金屬線180之間形成凹口120。在兩個相鄰的重分佈金屬線180之間的凹口120之深度D1等於或大於約1 um,凹口120可防止半導體裝置運作時產生金屬橋接。亦可在重分佈金屬線180上形成抗電子遷移(anti-electromigration)層以增加對電子遷移的阻抗。
第2圖顯示在第1圖中一位置的結構,其相同於第1-1圖中的位置。相同或相似於對應第1圖從基板158到鈍化保護層174的說明將被省略。請參照第2圖,在第一聚合物層178
中的兩個相鄰的重分佈金屬線180之間形成凹口,凹口之深度D1等於或大於約1 um。形成第2圖的局部結構的各種製程將搭配第2-1圖~第2-4圖作詳述。
請參照第2-1圖,在鈍化保護層(第1圖之層174,在此未顯示)上形成第一聚合物層178。第一聚合物層178是由聚合物材料所形成,例如聚亞醯胺(polyimide)、聚苯噁唑(polybenzoxazole,PBO)、矽氧樹脂(silicone)、苯並環丁烯(benzocyclobutene,BCB)、環氧聚合物(epoxy)、塑形(molding)化合物(例如環氧樹脂)、塑模底膠(molded underfill)(例如樹脂)等。可由習知的任何合適方法製作第一聚合物層178,例如,在200~400℃下進行旋轉塗佈(spin coating)及視需要地進行硬化(curing)步驟。
請參照第2-2圖,以微影步驟、金屬沉積、與蝕刻(視情況而定)在第一聚合物層178上形成重分佈金屬線180。重分佈金屬線180可由金屬製作,例如,鈦、氮化鈦、鋁、鉭、銅、或上述之組合。重分佈金屬線180可由習知的任何合適方法製作,例如,物理氣相沉積(physical vapor deposition,PVD)、濺鍍(sputter)、化學氣相沉積(chemical vapor deposition,CVD)、或電鍍(electroplating)。相鄰的兩個重分佈金屬線180之間隔小於約20 um。在一些實施例中,相鄰的兩個重分佈金屬線180之間隔小於約10 um。一些實施例中,使用清洗(cleaning)步驟以移除在微影步驟中所使用的光阻(photoresist)。
請參照第2-3圖,在未被重分佈金屬線180遮蓋的部分第一聚合物層178上形成凹口220。凹口220之深度D2等於或
大於約1 um。可為以重分佈金屬線180為蝕刻遮罩(mask),並使用帶有氣體的電漿蝕刻形成凹口220,氣體可為,例如,氮氣、氧氣、氧化氮、氧基(oxygen based)氣體、氧基(oxygen based)氣體混合物、氦氣、氬氣等。在一些實施例中,凹口220的形成方法可為帶有氣體的離子撞擊(bombardment),氣體可為,例如氮氣、氬氣、氮基(nitrogen based)氣體等。之後,可進行清洗步驟以移除電漿蝕刻的副產物。
請參照第2-4圖,第二聚合物層182形成並圍繞於重分佈金屬線180與第一聚合物層178上。第二聚合物層182是由聚合物材料所形成,例如聚亞醯胺(polyimide)、聚苯噁唑(polybenzoxazole,PBO)、矽氧樹脂(silicone)、苯並環丁烯(benzocyclobutene,BCB)、環氧聚合物(epoxy)、塑形(molding)化合物(例如環氧樹脂)、塑模底膠(molded underfill)(例如樹脂)等。可由習知的任何合適方法製作第二聚合物層182,例如,在200~400℃下進行旋轉塗佈(spin coating)及視需要地進行硬化(curing)步驟。
第3圖顯示在第1圖中一位置的結構,其相同於第1-1圖中的位置。相同或相似於對應第1圖從基板158到鈍化保護層174的說明將被省略。請參照第3圖,在第一聚合物層178中的兩個相鄰的重分佈金屬線180之間形成凹口,凹口之深度D3等於或大於約1 um。在重分佈金屬線180上沉積抗電子遷移層310以增加對電子遷移的電阻。形成第3圖的局部結構的各種製程將搭配第3-1圖~第3-5圖作詳述。
請參照第3-1圖,在鈍化保護層(第1圖之層174,在
此未顯示)上形成第一聚合物層178。第一聚合物層178是由聚合物材料所形成,例如聚亞醯胺(polyimide)、聚苯噁唑(polybenzoxazole,PBO)、矽氧樹脂(silicone)、苯並環丁烯(benzocyclobutene,BCB)、環氧聚合物(epoxy)、塑形(molding)化合物(例如環氧樹脂)、塑模底膠(molded underfill)(例如樹脂)等。可由習知的任何合適方法製作第一聚合物層178,例如,在200~400℃下進行旋轉塗佈(spin coating)及視需要地進行硬化(curing)步驟。
請參照第3-2圖,以微影步驟、金屬沉積、與蝕刻(視情況而定)在第一聚合物層178上形成重分佈金屬線180。重分佈金屬線180可由金屬製作,例如,鈦、氮化鈦、鋁、鉭、銅、或上述之組合。重分佈金屬線180可由習知的任何合適方法製作,例如,物理氣相沉積(physical vapor deposition,PVD)、濺鍍(sputter)、化學氣相沉積(chemical vapor deposition,CVD)、或電鍍(electroplating)。相鄰的兩個重分佈金屬線180之間隔小於約20 um。在一些實施例中,相鄰的兩個重分佈金屬線180之間隔小於約10 um。一些實施例中,使用清洗(cleaning)步驟以移除在微影步驟中所使用的光阻(photoresist)。
請參照第3-3圖,在重分佈金屬線180上沉積抗電子遷移層310。抗電子遷移層310之厚度為約100~10000埃。抗電子遷移層310可包括金、銀、鈀、銦、鎳、鍺、鉑、鎳鈀金合金、鎳金合金、其他貴金屬、或上述之組合。一些實施例中,抗電子遷移層310為多層(multi-layer)結構,包括鉑、鈀、鍺、銦、鋁、銀、鎳、鈀合金、鋁合金、銀合金、鎳合金、鍺合金、
銦合金、與鉑合金上述至少一者。可藉由任何適合的習知方法製作抗電子遷移層,例如物裡氣相沉積(PVD)、濺鍍、化學氣相沉積(CVD)、或電鍍(electroplating)。
請參照第3-4圖,在未被重分佈金屬線180遮蓋的部分第一聚合物層178上視需要地形成凹口320。凹口320之深度D3等於或大於約1 um。可為以重分佈金屬線180與抗電子遷移層310為蝕刻遮罩(mask),並使用帶有氣體的電漿蝕刻形成凹口320,氣體可為,例如,氮氣、氧氣、氧化氮、氧基(oxygen based)氣體、氧基(oxygen based)氣體混合物、氦氣、氬氣等。在一些實施例中,凹口320的形成方法可為帶有氣體的離子撞擊(bombardment),氣體可為,例如氮氣、氬氣、氮基(nitrogen based)氣體等。之後,可進行清洗步驟以移除電漿蝕刻的副產物。
請參照第3-5圖,第二聚合物層182形成並圍繞於重分佈金屬線180與第一聚合物層178上。第二聚合物層182是由聚合物材料所形成,例如聚亞醯胺(polyimide)、聚苯噁唑(polybenzoxazole,PBO)、矽氧樹脂(silicone)、苯並環丁烯(benzocyclobutene,BCB)、環氧聚合物(epoxy)、塑形(molding)化合物(例如環氧樹脂)、塑模底膠(molded underfill)(例如樹脂)等。可由習知的任何合適方法製作第二聚合物層182,例如,在200~400℃下進行旋轉塗佈(spin coating)及視需要地進行硬化(curing)步驟。
第4圖顯示在第1圖中一位置的結構,其相同於第1-1圖中的位置。相同或相似於對應第1圖從基板158到鈍化保
護層174的說明將被省略。請參照第3圖,在第一聚合物層178中的兩個相鄰的重分佈金屬線180之間形成凹口,凹口之深度D4等於或大於約1 um。在重分佈金屬線180上沉積抗電子遷移層410以增加對電子遷移的電阻。形成第4圖的局部結構的各種製程將搭配第4-1圖~第4-5圖作詳述。
請參照第4-1圖,在鈍化保護層(第1圖之層174,在此未顯示)上形成第一聚合物層178。第一聚合物層178是由聚合物材料所形成,例如聚亞醯胺(polyimide)、聚苯噁唑(polybenzoxazole,PBO)、矽氧樹脂(silicone)、苯並環丁烯(benzocyclobutene,BCB)、環氧聚合物(epoxy)、塑形(molding)化合物(例如環氧樹脂)、塑模底膠(molded underfill)(例如樹脂)等。可由習知的任何合適方法製作第一聚合物層178,例如,在200~400℃下進行旋轉塗佈(spin coating)及視需要地進行硬化(curing)步驟。
請參照第4-2圖,以微影步驟、金屬沉積、與蝕刻(視情況而定)在第一聚合物層178上形成重分佈金屬線180。重分佈金屬線180可由金屬製作,例如,鈦、氮化鈦、鋁、鉭、銅、或上述之組合。重分佈金屬線180可由習知的任何合適方法製作,例如,物理氣相沉積(physical vapor deposition,PVD)、濺鍍(sputter)、化學氣相沉積(chemical vapor deposition,CVD)、或電鍍(electroplating)。相鄰的兩個重分佈金屬線180之間隔小於約20 um。在一些實施例中,相鄰的兩個重分佈金屬線180之間隔小於約10 um。一些實施例中,使用清洗(cleaning)步驟以移除在微影步驟中所使用的光阻(photoresist)。
請參照第4-3圖,在未被重分佈金屬線180遮蓋的部分第一聚合物層178上形成凹口420。凹口420之深度D4等於或大於約1 um。可為以重分佈金屬線180與抗電子遷移層410為蝕刻遮罩(mask),並使用帶有氣體的電漿蝕刻形成凹口420,氣體可為,例如,氮氣、氧氣、氧化氮、氧基(oxygen based)氣體、氧基(oxygen based)氣體混合物、氦氣、氬氣等。在一些實施例中,凹口420的形成方法可為帶有氣體的離子撞擊(bombardment),氣體可為,例如氮氣、氬氣、氮基(nitrogen based)氣體等。之後,可進行清洗步驟以移除電漿蝕刻的副產物。
請參照第4-4圖,在重分佈金屬線180上沉積抗電子遷移層410,且抗電子遷移層410之厚度為約100~10000埃。抗電子遷移層410為非金屬材料層,例如,介電材料層、聚合物材料層、或上述之組合。抗電子遷移層410可為單層或多層結構。在一些實施例中,抗電子遷移層410為介電材料層,其是由氮化矽、氧化矽、氮氧化矽、碳化矽、氮化碳矽(silicon carbon nitride)、重複氧化矽與氮化矽的層、或上述之組合等材料,並藉由不同的沉積技術所形成,沉積技術可包括熱氧化、低壓化學氣相沉積(low-pressure chemical vapor deposition,LPVCD)、大氣壓力化學氣相沉積(atmospheric-pressure chemical vapor deposition,APCVD)、電漿增強化學氣相沉積(plasma-enhaced chemical vapor depostion,PEVDE)、熱絲化學氣相沉積(hot wire chemical vapor deposition,HWCVD)、與未來發展的沉積製程。一些實施例中,抗電子遷移層410為聚合物材料層,例如,環氧聚合物(epoxy)、聚亞醯胺(polyimide)、
苯並環丁烯(benzocyclobutene,BCB)、聚苯噁唑(polybenzoxazole,PBO)等,然而,也可使用其他相對較軟的介電材料,通常為有機物。
在形成抗電子遷移層410後可視情況而定地進行蝕刻製程,以移除位於重分佈金屬線180與第一聚合物層178上的部分抗電子遷移層410。蝕刻製程包括乾蝕刻,例如電漿蝕刻或活性(reactive)離子蝕刻。
請參照第4-5圖,第二聚合物層182形成並圍繞於重分佈金屬線180與第一聚合物層178上。第二聚合物層182是由聚合物材料所形成,例如聚亞醯胺(polyimide)、聚苯噁唑(polybenzoxazole,PBO)、矽氧樹脂(silicone)、苯並環丁烯(benzocyclobutene,BCB)、環氧聚合物(epoxy)、塑形(molding)化合物(例如環氧樹脂)、塑模底膠(molded underfill)(例如樹脂)等。可由習知的任何合適方法製作第二聚合物層182,例如,在200~400℃下進行旋轉塗佈(spin coating)及視需要地進行硬化(curing)步驟。
第5圖顯示在第1圖中一位置的結構,其相同於第1-1圖中的位置。相同或相似於對應第1圖從基板158到鈍化保護層174的說明將被省略。請參照第5圖,在第一聚合物層178中的兩個相鄰的重分佈金屬線180之間形成凹口,凹口之深度D5等於或大於約1 um。在重分佈金屬線180上沉積抗電子遷移層510以增加對電子遷移的電阻。形成第3圖的局部結構的各種製程將搭配第5-1圖~第5-5圖作詳述。
請參照第5-1圖,在鈍化保護層(第1圖之層174,在
此未顯示)上形成第一聚合物層178。第一聚合物層178是由聚合物材料所形成,例如聚亞醯胺(polyimide)、聚苯噁唑(polybenzoxazole,PBO)、矽氧樹脂(silicone)、苯並環丁烯(benzocyclobutene,BCB)、環氧聚合物(epoxy)、塑形(molding)化合物(例如環氧樹脂)、塑模底膠(molded underfill)(例如樹脂)等。可由習知的任何合適方法製作第一聚合物層178,例如,在200~400℃下進行旋轉塗佈(spin coating)及視需要地進行硬化(curing)步驟。
請參照第5-2圖,以微影步驟、金屬沉積、與蝕刻(視情況而定)在第一聚合物層178上形成重分佈金屬線180。重分佈金屬線180可由金屬製作,例如,鈦、氮化鈦、鋁、鉭、銅、或上述之組合。重分佈金屬線180可由習知的任何合適方法製作,例如,物理氣相沉積(physical vapor deposition,PVD)、濺鍍(sputter)、化學氣相沉積(chemical vapor deposition,CVD)、或電鍍(electroplating)。相鄰的兩個重分佈金屬線180之間隔小於約20 um。在一些實施例中,相鄰的兩個重分佈金屬線180之間隔小於約10 um。一些實施例中,使用清洗(cleaning)步驟以移除在微影步驟中所使用的光阻(photoresist)。
請參照第5-3圖,在重分佈金屬線180上沉積抗電子遷移層510。抗電子遷移層510之厚度為約100~10000埃。抗電子遷移層510為非金屬材料層,例如,介電材料層、聚合物材料層、或上述之組合。抗電子遷移層510可為單層或多層結構。在一些實施例中,抗電子遷移層510為介電材料層,其是由氮化矽、氧化矽、氮氧化矽、碳化矽、氮化碳矽(silicon carbon
nitride)、重複氧化矽與氮化矽的層、或上述之組合等材料並藉由不同的沉積技術所形成,沉積技術可包括熱氧化、低壓化學氣相沉積(low-pressure chemical vapor deposition,LPVCD)、大氣壓力化學氣相沉積(atmospheric-pressure chemical vapor deposition,APCVD)、電漿增強化學氣相沉積(plasma-enhaced chemical vapor depostion,PEVDE)、熱絲化學氣相沉積(hot wire chemical vapor deposition,HWCVD)、與未來發展的沉積製程。一些實施例中,抗電子遷移層510為聚合物材料層,例如,環氧聚合物(epoxy)、聚亞醯胺(polyimide)、苯並環丁烯(benzocyclobutene,BCB)、聚苯噁唑(polybenzoxazole,PBO)等,然而,也可使用其他相對較軟的介電材料,通常為有機物。
請參照第5-4圖,在未被重分佈金屬線180遮蓋的部分第一聚合物層178上形成凹口520。凹口520之深度D5等於或大於約1 um。可為以重分佈金屬線180與抗電子遷移層510為蝕刻遮罩(mask),並使用帶有氣體的電漿蝕刻形成凹口520,氣體可為,例如,氮氣、氧氣、氧化氮、氧基(oxygen based)氣體、氧基(oxygen based)氣體混合物、氦氣、氬氣等。在一些實施例中,凹口520的形成方法可為帶有氣體的離子撞擊(bombardment),氣體可為,例如氮氣、氬氣、氮基(nitrogen based)氣體等。之後,可進行清洗步驟以移除電漿蝕刻的副產物。
請參照第5-5圖,第二聚合物層182形成並圍繞於重分佈金屬線180與第一聚合物層178上。第二聚合物層182是由聚合物材料所形成,例如聚亞醯胺(polyimide)、聚苯噁唑(polybenzoxazole,PBO)、矽氧樹脂(silicone)、苯並環丁烯
(benzocyclobutene,BCB)、環氧聚合物(epoxy)、塑形(molding)化合物(例如環氧樹脂)、塑模底膠(molded underfill)(例如樹脂)等。可由習知的任何合適方法製作第二聚合物層182,例如,在200~400℃下進行旋轉塗佈(spin coating)及視需要地進行硬化(curing)步驟。
第6圖為對應到第2圖~第5-5圖的方法600之流程圖。方法從步驟601開始,在基板上形成多個介電層。基板可包括多個裝置形成於其上。在步驟603中,在基板上的該些介電層中形成多個金屬層。本領域中具有通常知識者將理解可重複步驟601與603以形成多個金屬層在對應的多個介電層中。在步驟605中,對應到第2-1圖、第3-1圖、第4-1圖、與第5-1圖,在該些介電層與該些金屬層上方形成第一聚合物層。在步驟607,對應到第2-2圖、第3-2圖、第4-2圖、與第5-2圖,在第一聚合物層上形成多個金屬線。在步驟609中,在兩個相鄰的金屬線之間的第一聚合物層中形成凹口,凹口之深度等於或大於約1 um。步驟609對應到第2-3圖、第3-4圖、第4-3圖、與第5-4圖。在可選的(optional)步驟611(視情況而選擇)中,在該些金屬層之側壁與第一聚合物層之間形成抗電子遷移層。步驟611對應到第3-3圖、第4-4圖、與第5-3圖。一些實施例中,步驟611接在步驟609之後(對應到第4圖、第4-1圖~第4-5圖及其相關的文字敘述)。一些實施例中,步驟611接在步驟607之後(對應到第5圖、第5-1圖~第5-5圖及其相關的文字敘述)。一些實施例中,步驟609接在步驟611之後(對應到第3圖、第3-1圖~第3-5圖及其相關的文字敘述)。在步驟613中,在該些金屬線與第一
聚合物層上方形成第二聚合物層。
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作更動、替代與潤飾。舉例來說,任何所屬技術領域中具有通常知識者可輕易理解此處所述的許多特徵、功能、製程及材料可在本發明的範圍內作更動。
再者,本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟,任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟,只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此,本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外,每一申請專利範圍構成個別的實施例,且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
100‧‧‧半導體晶粒
158‧‧‧基板
160‧‧‧電子電路
162、168‧‧‧層間介電層
164、170‧‧‧插塞
166、172‧‧‧金屬層
174‧‧‧鈍化保護層
176‧‧‧開口
178‧‧‧第一聚合物層
180‧‧‧重分佈金屬線
182‧‧‧第二聚合物層
184、188‧‧‧導電墊
186‧‧‧導電材料
120‧‧‧凹口
Claims (10)
- 一種半導體裝置,包括:一基板;多個層間介電層,於該基板上方;多個金屬層,於該基板上方;一第一聚合物層,於該些層間介電層與該些金屬層上方;其中該第一聚合物層具有一第一表面、一第二表面於該第一表面的同側、及一第三表面於該第一表面之相反側,且該第一表面與該第二表面之一深度差等於或大於約1 um;多個金屬線,於該第一表面與該第一聚合物層上;以及一第二聚合物層,於該些金屬線與該第一聚合物層上。
- 如申請專利範圍第1項所述之半導體裝置,更包括一非金屬材料層,於該些金屬線之側壁與該第二聚合物層之間,且其中該非金屬材料層包括氮化矽、氧化矽、氮氧化矽、碳化矽、氮化碳矽(silicon carbon nitride)、或上述之組合。
- 如申請專利範圍第1項所述之半導體裝置,其中該第一聚合物層包括聚亞醯胺(polyimide)、聚苯噁唑(polybenzoxazole,PBO)、矽氧樹脂(silicone)、苯並環丁烯(benzocyclobutene,BCB)、環氧聚合物(epoxy)、樹脂(resin)等,且其中該第二聚合物層包括聚亞醯胺(polyimide)、聚苯噁唑(polybenzoxazole,PBO)、矽氧樹脂(silicone)、苯並環丁烯(benzocyclobutene,BCB)、環氧聚合物(epoxy)、樹脂(resin)等。
- 如申請專利範圍第1項所述之半導體裝置,其中該些金屬線 中相鄰的兩個金屬線的間隔小於約20 um。
- 一種半導體裝置,包括:一基板;多個層間介電層,於該基板上方;多個金屬層,於該基板上方;一第一聚合物層,於該些層間介電層與該些金屬層上方;多個金屬線,於該第一聚合物層之一第一表面上;一第二聚合物層,於該些金屬線上;以及一抗電子遷移層,於該些金屬線之側壁與該第二聚合物層之間。
- 如申請專利範圍第5項所述之半導體裝置,其中該第一聚合物層具有一第二表面於該第一表面的同側、及一第三表面於該第一表面之相反側,且該第一表面與該第二表面之一深度差等於或大於約1 um。
- 如申請專利範圍第5項所述之半導體裝置,其中該抗電子遷移層為金、鎳、鉑、錫、鉭、鈀、氮化鈦、鎢、銀、鍺、銦、或上述之組合。
- 一種半導體裝置的製造方法,包括:提供一基板;形成多個層間介電層於該基板上方;形成多個金屬層於該基板上方;形成一第一聚合物層於該些層間介電層與該些金屬層上方;形成多個金屬線於該第一聚合物層上; 形成一凹口於兩個相鄰的金屬線之間的該第一聚合物層中,該凹口之深度等於或大於約1 um;以及形成一第二聚合物層於該些金屬線上。
- 如申請專利範圍第8項所述之半導體裝置的製造方法,其中該第一聚合物層包括聚亞醯胺(polyimide)、聚苯噁唑(polybenzoxazole,PBO)、矽氧樹脂(silicone)、苯並環丁烯(benzocyclobutene,BCB)、環氧聚合物(epoxy)、樹脂(resin)等,且其中該第二聚合物層包括聚亞醯胺(polyimide)、聚苯噁唑(polybenzoxazole,PBO)、矽氧樹脂(silicone)、苯並環丁烯(benzocyclobutene,BCB)、環氧聚合物(epoxy)、樹脂(resin)等。
- 如申請專利範圍第8項所述之半導體裝置的製造方法,更包括:形成一抗電子遷移層於該些金屬線之側壁與該第二聚合物層之間。
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