TWI557820B - 元件封裝及其形成方法 - Google Patents

元件封裝及其形成方法 Download PDF

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Publication number
TWI557820B
TWI557820B TW104139735A TW104139735A TWI557820B TW I557820 B TWI557820 B TW I557820B TW 104139735 A TW104139735 A TW 104139735A TW 104139735 A TW104139735 A TW 104139735A TW I557820 B TWI557820 B TW I557820B
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Taiwan
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layer
under
metal layer
conductive
opening
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TW104139735A
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English (en)
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TW201701378A (zh
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陳威宇
陳憲偉
蘇安治
謝正賢
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台灣積體電路製造股份有限公司
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Publication of TW201701378A publication Critical patent/TW201701378A/zh

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Description

元件封裝及其形成方法
本揭露是關於一種元件封裝及其形成方法，特別是關於一種球下金屬層封裝及其形成方法。
在傳統的封裝技術上，舉例來說，可於晶粒上方形成晶圓級封裝(wafer level packaging,WLP)、重新分配層(redistribution layer,RDL)，並將其電性連接至晶粒上以活化元件。外部輸入/輸出墊(I/O pads)，舉例來說，位於球下金屬層上的焊球可接著形成，並透過重新分配層電性連接至晶粒。這項封裝技術的一種有利特徵是形成扇出封裝(fan-out package)的可能性。因此，位於晶粒上方的輸入/輸出墊的面積可被重新分配成較晶粒面積還大，於是晶粒表面上封裝的輸入/輸出墊數量可增加。
在這樣的封裝技術中，可於晶粒四周形成成型料件來提供表面區域以支撐扇出內連接結構(fan-out interconnect structures)。舉例來說，重新分配層典型上包含一或多層形成於晶粒與成型料件上方的高分子層。於高分子層中形成導電性的特徵(例如，導電線及/或通道)將晶粒上的輸入 /輸出墊電性連接至位於重新分配層上方之外部的輸入/輸出墊。外部的輸入/輸出墊可設置於晶粒與成型料件上方。
依據本揭露之多個實施方式，一種元件封裝包含晶粒、扇出重新分配層與球下金屬層。扇出重新分配層位於晶粒上方。球下金屬層位於扇出重新分配層上方。球下金屬層包含導電墊部位與溝槽。溝槽環繞導電墊部位。元件封裝包含還包含連接器。連接器設置於球下金屬層的導電墊部位上，其中扇出重新分配層將連接器與球下金屬層電性連接至晶粒。
依據本揭露之多個實施方式，一種元件封裝包含元件晶粒、導電線、高分子層與球下金屬層。導電線位於元件晶粒上方且電性連接至元件晶粒。高分子層延伸至導電線的上表面上方。球下金屬層形成於導電線之上表面上，其中球下金屬層被位於高分子層中的開口至少部分曝露而出。球下金屬層包含導電墊部位與維持牆部位。維持牆部位形成環狀結構圍繞導電墊部位。維持牆部位被溝槽從導電墊部位分開。焊球位於球下金屬層的導電墊部位上。
依據本揭露之多個實施方式，一種元件封裝的方法包含下列步驟：於晶粒上方形成晶種層。於晶種層上形成導電線。於導電線與晶種層上方形成第一遮罩層。於第一遮罩層中圖案化開口。開口包含第一開口與第二開口。第一開口用以形成球下金屬層之導電墊部位。第二開口用以形成球下金屬層之維持牆部位。第二開口形成環狀結構圍繞第一開口，且第一 遮罩層的一部分仍設置於第一開口與第二開口間。元件封裝的方法還包含下列步驟：於第一開口與第二開口中形成球下金屬層。移除第一遮罩層。於球下金屬層的導電墊部位固定焊球。
100、200、300‧‧‧封裝
102‧‧‧晶粒
104‧‧‧成型料件
106‧‧‧重新分配層
108、126‧‧‧高分子層
110‧‧‧接觸墊
112‧‧‧保護層
114‧‧‧導電柱
116‧‧‧介電層
118‧‧‧晶粒貼附膜
120‧‧‧載體
122‧‧‧導電特徵
122A‧‧‧導電線
122B‧‧‧導電通道
124‧‧‧導電線
126‧‧‧高分子層
128‧‧‧球下金屬層
128’‧‧‧導電墊部位
128”‧‧‧維持牆部位
130‧‧‧溝槽
132‧‧‧連接器
134‧‧‧晶種層
136、138‧‧‧遮罩層
140‧‧‧開口
140A‧‧‧第一開口
140B‧‧‧第二開口
第1A圖至第1C圖繪示依據本揭露一些實施方式之元件封裝的剖面圖。
第2圖至第9圖繪示依據本揭露一些實施方式之製造元件封裝之中間步驟的剖面圖。
第10A圖與第10B圖繪示依據本揭露一些其他實施方式之元件封裝的的剖面圖。
第11A圖與第11B圖繪示依據本揭露一些其他實施方式之元件封裝的的剖面圖。
第12圖繪示依據本揭露一些實施方式之形成元件封裝的流程圖。
以下的說明將提供許多不同的實施方式或實施例來實施本揭露的主題。元件或排列的具體範例將在以下討論以簡化本揭露。當然，這些描述僅為部分範例且本揭露並不以此為限。例如，將第一特徵形成在第二特徵上或上方，此一敘述不但包含第一特徵和第二特徵直接接觸的實施方式，也包含其他特徵形成在第一特徵與第二特徵之間，且在此情形下第一特 徵和第二特徵不會直接接觸的實施方式。此外，本揭露可能會在不同的範例中重複標號或文字。重複的目的是為了簡化及明確敘述，而非界定所討論之不同實施方式及配置間的關係。
此外，空間相對用語如「下面」、「下方」、「低於」、「上面」、「上方」及其他類似的用語，在此是為了方便描述圖中的一個元件或特徵和另一個元件或特徵的關係。空間相對用語除了涵蓋圖中所描繪的方位外，該用語更涵蓋裝置在使用或操作時的其他方位。也就是說，當該裝置的方位與圖式不同(旋轉90度或在其他方位)時，在本文中所使用的空間相對用語同樣可相應地進行解釋。
於多種實施方式中，包含形成於半導體元件晶粒上方且具有扇出重新分配層(redistribution layers,RDLs)的封裝。球下金屬層(under bump metallurgy,UBM)形成於重新分配層最上面的導電線的上方，並且溝槽圖案化於球下金屬層中。舉例來說，球下金屬層可包含導電墊部位與圍繞導電墊部位的維持牆部位，其中溝槽實體上分隔了導電墊部位與維持牆部位。外部的連接器(例如：焊球)固定於球下金屬層的導電墊部位上，且可進行回流製程(reflow process)以將連接器黏合至球下金屬層。在回流的過程中，導電性材料(例如：助焊劑(solder flux))可能從連接器下面流出。藉由包含溝槽與環繞導電墊的維持牆，助焊劑可維持於球下金屬層中，且助焊劑不會向外流出而損傷元件封裝的其他特徵。舉例來說，可預防助焊劑破壞介於導電性特徵與重新分配層之高分子層的介面。因此，可降低因回流製程造成的層別分離問題，從而改善 製造良率。甚至，可藉由使用單一晶種層形成球下金屬層與導電線，其有利地降低了製造成本。
第1A圖繪示依據本揭露多個實施方式之一種扇出元件(fan-out device)封裝100的剖面圖。封裝100包含晶粒102與設置以圍繞晶粒102的成型料件104，且重新分配層106(例如：具有導電特徵122)形成於晶粒102與成型料件104上方。晶粒102可為半導體晶粒和任何形式的積體電路，例如處理器、邏輯電路(logic circuitry)、記憶體、類比電路、數位電路、混和信號(mixed signal)電路或其他類似電路。
晶粒102可包含基板、主動元件與內連接結構(未單獨繪示)。舉例來說，基板可包含塊狀矽(bulk silicon)基板、摻雜或未摻雜的基板、或絕緣層覆矽(semiconductor-on-insulator,SOI)基板的主動層。一般來說，絕緣層覆矽基板包含形成於絕緣層上的一層半導體材料，例如矽。舉例來說，絕緣層可包含氧化埋層(buried oxide(BOX)layer)或矽氧化層(silicon oxide layer)。絕緣層，例如矽或玻璃基板，提供於基板上。可替代地，基板可包含其他基本半導體、化合物半導體、合金半導體或其組合。基本半導體例如鍺。化合物半導體包含碳化矽(silicon carbide)、砷化鎵(gallium arsenic)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)及/或銻化銦(indium antimonide)。合金半導體包含矽鍺(SiGe)、磷化砷鎵(GaAsP)、砷化銦鋁(AlInAs)、砷化鎵鋁(AlGaAs)、砷化銦鎵(GaInAs)、磷化銦鎵(GaInP)及/或砷磷化鎵銦 (GaInAsP)。其他基板，舉例來說，多層結構或帶有梯度的基板亦可使用。
主動元件，例如電晶體、電容、電阻、二極體、光二極體、熔斷器與其他類似物，可形於基板的上表面成。內連接結構可形成於主動元件與基板上方。內連接結構可包含使用任何適合方法形成之含有導電特徵(例如：含有銅、鋁、鎢、其組合物或其他類似物的導電線與導孔)的層間介電質(inter-layer dielectric,ILD)層及/或金屬間介電質(inter-metal dielectric,IMD)層。層間介電質與金屬間介電質可包含低介電常數值(low-k)的介電材料，其具有的介電常數值，舉例來說，低於約4或甚至約2。含有低介電常數值介電材料的層間介電質與金屬間介電質設置於如此的導電特徵之間。在一些實施方式中，層間介電質與金屬間介電質的材質可為，舉例來說，磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼矽酸鹽玻璃(borophosphosilicate glass,BSG)、氟矽玻璃(fluorosilicate glass,FSG)、含氧碳化矽(SiOxCy)、旋塗玻璃(Spin-On-Glass)、旋塗高分子(Spin-On-Polymers)、碳化矽(silicon carbon)材料、前述之化合物、前述之合成物、前述之組合物或其他類似物。層間介電質與金屬間介電質可藉由任何適合方法形成，舉例來說，旋轉塗佈(spinning)、化學氣相沉積(chemical vapor deposition,CVD)與電漿輔助化學氣相沉積(plasma-enhanced chemical vapor deposition,PECVD)。內連接結構電性連接至各種不同的主動元件，以在晶粒102中形成功能性電路。這樣的電路所提供的功能可包含 記憶體結構、處理器結構、感應器、放大器、電力分配、輸入/輸出電路或其他類似結構。於本技術領域具有通常知識之人應能理解，提供上述例子的目的僅為進一步解釋本揭露，並非以任何方法限制本揭露。當為了滿足某些應用時，可使用其他的電路。
輸入/輸出(I/O)與保護的特徵可形成於內連接結構上方。舉例來說，接觸墊110可形成於內連接結構上方，並可藉由各種位於內連接結構中之不同的導電性特徵，電性連接至主動元件。接觸墊110可包含導電材料，舉例來說，鋁、銅或其他類似物。並且，可於內連接結構與保護墊110上方形成保護層112。在一些實施方式中，可以使用非有機質材料(non-organic materials)，舉例來說，氧化矽(silicon oxide)、未摻雜的矽酸鹽玻璃(un-doped silicate glass)、氮化氧矽(silicon oxynitride)或其他類似物來形成保護層112。也可以使用其他適合的保護層材料。保護層112的一些部位可覆蓋住接觸墊110的邊緣部位。
額外的內連接特徵，例如，額外的保護層、導電柱及/或球下金屬層(under bump metallurgy,UBM)，亦可選擇形成於接觸墊110上。舉例來說，如第1A圖所繪示，導電柱114可形成於接觸墊110上並電性連接至接觸墊110，並且介電層116可進一步形成以圍繞導電柱114。晶粒102的各種特徵可藉由任何適合的方法而形成，並且於此不再進一步詳述。並且，上述晶粒102的一般特徵與配置為例示性的實施方式，並且晶粒102可包含上述特徵或其他特徵之數量上的任意組合。
雖然前面所描述的始終為晶粒102，本技術領域中具有通常知識者應理解，當晶粒102為較大之基板，例如晶圓，的一部分時，可對晶粒102進行一些處理。形成之後，可於晶圓中的其他結構(例如：其他晶粒)獨立出晶粒102，並且將其貼附至載體120(例如：使用晶粒貼附膜(die attach film,DAF)118)以作進一步的處理。載體120可為玻璃或陶瓷載體，且在封裝100的各種特徵形成過程中，載體120可提供暫時性的結構支撐。
成型料件104係設置以圍繞晶粒102。舉例來說，於成型料件104/晶粒102的一個由上而下的視圖中(未繪示)，成型料件104可圍繞晶粒102。成型料件104可提供適合的表面，以形成扇出重新分配層，例如重新分配層106。成型料件104的材質可包含任何適合的材料，舉例來說，環氧樹酯(epoxy resin)、成型底部填充劑(molding underfill)及其他類似物。形成成型料件104的適合方法可包含壓力成型(compressive molding)、傳遞成型(transfer molding)、液態密封劑成型(liquid encapsulant molding)及其他類似方法。舉例來說，成型料件104可以液態形式圍繞晶粒102。接下來，進行固化製程以固化成型料件104。填充成型料件104時可能溢出晶粒102，使得成型料件104覆蓋住晶粒102的上表面。可使用機械研磨(mechanical grinding)、化學機械研磨拋光(chemical mechanical polish,CMP)或其他回蝕技術以移除成型料件104多餘的部分，並曝露出晶粒102的連接器(例如： 導電柱114)。經過平坦化製程後，成型料件104與晶粒102的上表面本質上可在同一水平面。
可於晶粒102與成型料件104上方形成一或多層重新分配層106。重新分配層106可側向延伸過晶粒102的邊緣，以提供扇出內連接結構。重新分配層106可包含一或多個形成於晶粒102與成型料件104上方的高分子層108。在一些實施方式中，高分子層108可包含聚醯亞氨(polyimide,PI)、聚苯撐苯并二噁唑(PBO)、苯并環丁烯(benzocyclobuten,BCB)、環氧樹酯(epoxy)、矽氧樹酯(silicone)、丙烯酸酯(acrylates)、奈米填充苯氧樹酯(nano-filled pheno resin)、矽氧烷(siloxane)、氟化高分子(fluorinated polymer)、降冰片烯(polynorbornene)及其他使用任何適合方法，例如旋轉塗佈(spin-on)技術而形成的類似物。
導電特徵122(例如：導電線122A與導電通道122B)形成於高分子層108間。導電線122A形成於高分子層108上方，且導電通道122B可延伸過高分子層108，並電性連接至晶粒102的接觸墊110。雖然清楚地繪示出三層高分子層108，重新分配層106更可視封裝設計而包含任何層數的高分子層108，且高分子層108具有導電特徵設置於其中。
重新分配層106可進一步包含最上面的高分子層126，其係設置於封裝100的外表面。高分子層126可包含最上面的導電線124，其藉由導電特徵122電性連接至位於下方的晶粒102。最上面的導電線124可為重新分配線，以作為電性配線及形成輸入/輸出特徵的平台。在一些實施方式中，最上 面的導電線124亦可被稱為無球下金屬層(under bump metallurgy-less,UBML)墊124。
額外的封裝特徵，舉例來說，球下金屬層128與外部的連接器132形成於重新分配層106的最上面的導電線124之上方。第1B圖繪示依據本揭露多個實施方式之封裝100中具有如此特徵的詳細剖面圖。第1C圖繪示依據本揭露多個實施方式之球下金屬層128、外部的連接器132與導電線124對應的由上而下的視圖。連接器132可為焊球，例如，球柵陣列封裝(ball grid array,BGA)球、倒裝晶片連接(controlled collapse chip connector(C4)bumps)、微凸塊(microbumps)或其他類似物。連接器132可藉由重新分配層106中的導電特徵122電性連接至晶粒102。連接器132可將封裝100電性連接至其他封裝元件，舉例來說，其他元件晶粒、內插器、封裝基板、印刷電路板(printed circuit board,PCB)、主機版(mother board)或其他類似物。
在各種不同實施方式中，連接器132設置於球下金屬層128上，連接器132可形成於導電線124上方。雖然為了簡單的目的而僅繪示單一個連接器132與單一個球下金屬層128，封裝100可包含任何數量的球下金屬層128/連接器132。可在高分子層126中圖案化出開口以曝露出球下金屬層128，且高分子層126可覆蓋住球下金屬層128的邊緣部位。
在一些實施方式中，可直接於導電線124上形成球下金屬層128。如同在接下來的段落中將更詳盡地說明，單獨使用晶種層來形成球下金屬層128與導電線124，其有利地 降低生產成本。在球下金屬層128中圖案化出溝槽130。舉例來說，溝槽130實體上從球下金屬層128中分隔出維持牆部位128”與導電墊部位128’。溝槽130可圍繞連接器132(例如參照第1C圖)以維持助焊劑流量，使助焊劑免於在回流時從連接器132流出。舉例來說，當連接器132固定在球下金屬層128上時，可使用回流製程黏合連接器132與球下金屬層128。在回流的過程中，助焊劑可能從連接器132向外流出並且損害不同封裝材料間的介面(例如，高分子層126與導電線124間的介面)，從而可能會導致層別分離及/或其他缺陷。這些缺陷在測試製程中，例如對封裝100所進行的熱循環測試(thermal cycle test)，可能會進一步惡化。藉由形成環繞連接器132的溝槽130，助焊劑可被維持在溝槽130中而不流向封裝100的其他區域，從而降低了封裝缺陷(例如，高分子層和導電特徵間的層別分離)。
在第1B圖與第1C圖中，側向尺寸W1對應於連接器132中心至距離連接器132中心的導電線124的最近邊緣間之距離。側向尺寸W2對應於連接器132中心至距離連接器132中心的球下金屬層128的最遠邊緣128C間之距離。側向尺寸W3對應於連接器132中心至距離連接器132中心的高分子層126的最近側牆126A間之距離。側向尺寸W4對應於連接器132中心至距離連接器132中心的溝槽130的最遠側牆128B間之距離。側向尺寸W5對應於連接器132中心至距離連接器132中心的溝槽130的最近側牆128A間之距離。在封裝100中，前述側向尺寸W1至W5的大小關係為W1>W2>W3>W4> W5。並且，溝槽130的側向尺寸(例如，W4減去W5)可為約10微米至約20微米。並且，維持牆部位128”的側向尺寸(例如，W2減去W4)亦可為約10微米至約20微米。
第2圖至第9圖繪示依據本揭露一些實施方式之形成最上面的導電線124、球下金屬層128以及連接器132的各中間階段的剖面圖。在第2圖中，提供封裝100(高分子層108具有導電特徵122)的一部位的剖面圖。高分子層108可為部分的重新分配層106，且如前面所述(見第1A圖繪示)，可於元件晶粒102與成型料件104上方形成高分子層108。舉例來說，同樣繪示於第2圖中的為含銅的導電性晶種層134。晶種層134電性連接至位於其下的導電特徵122。舉例來說，在一些實施方式中，形成晶種層134包含在高分子層108中形成開口，並使用例如光微影及/或蝕刻製程來曝露出導電特徵122。接著，可於高分子層108上方與開口中，藉由使用原子層沉積(atomic layer deposition)、化學氣相沉積(chemical vapor deposition,CVD)或其他共型的沉積方式來形成晶種層134。
接著參考第3圖，於晶種層134上形成導電線124。使用圖案化的遮罩層136來定義導電線124的形狀。舉例來說，於一些實施方式中，遮罩層136為沉積於晶種層134上方的光阻地毯(photoresist blanket)，並接著使用光微影術來進行圖案化。舉例來說，光微影術可包含，在紫外光(ultraviolet light)下透過蝕刻罩幕而曝露出遮罩層136的一些部位。接著，對遮罩層136之曝露的或未曝露的部位進行顯影，並依據使用的光阻為正型光阻(positive resist)或負型光 組(negative resisit)來決定是否要移除光阻。如此，可於遮罩層136中形成曝露出晶種層134的開口。在其他實施方式中，遮罩層136可為硬式罩幕(例如，包含氮化矽(silicon nitride)及其他類似物)。於這樣的實施方式中，舉例來說，可於遮罩層136上方形成並圖案化光阻(未繪示)，且藉由使用適合的蝕刻製程，光阻的圖案可接著被轉移至遮罩層136。
於圖案化遮罩層136後，使用適合的製程，例如無電鍍(electroless plating)、電化學鍍(electro-chemical plating)或其他方法，於開口中形成導電線124。在電鍍過程中，晶種層134提供了成核點，以使導電線124由下而上地成長並具有良好的均勻性。電鍍製程的結果，導電線124可併入其下的晶種層134，且在一例示性的實施方式中，導電線124的總厚度T1(包含晶種層134)可為約5微米至約8微米。可在其他實施方式中使用其他尺寸的導電線124。於形成導電線124後，可使用適合的製程來移除遮罩層136。舉例來說，當遮罩層136為光阻時，可使用電漿灰化(plasma ashing)或濕式剝離製程來移除遮罩層136。在電漿灰化製程完後，可以選擇性地以硫酸(H2SO4)溶液浸濕封裝100，並且移除殘餘的光阻材料。在其他實施方式中，當遮罩層136為硬式罩幕，可使用選擇性蝕刻製程以移除遮罩層136。
接著，在第4圖與第5圖中，球下金屬層128形成於晶種層134與導電線124上方。在第4圖中，遮罩層138沉積於晶種層134與導電線124上方。遮罩層138類似遮罩層136，且遮罩層138可於使用上述適合的製程來圖案化出帶有開口 140(標記為140A與140b)的圖案。開口140曝露出下方的導電線124，且遮罩層138可用於定義每一個球下金屬層128的形狀。舉例來說，開口140可包含第一開口140A用以定義球下金屬層128的導電墊部位，且第二開口140B用以定義球下金屬層128的維持牆部位。在由上往下的視圖中(未繪示)，第二開口140B可圍繞第一開口140A。遮罩層138的一部分仍然可設置於第一開口140A與第二開口140B之間。
接下來，在第5圖中，使用適合的製程，例如無電鍍、電化學電鍍或其他類似方法，於開口140中形成球下金屬層128。舉例來說，球下金屬層128的厚度T2為約1.5微米至約5微米。球下金屬層128的其他種尺寸可用於其他實施方式中。球下金屬層128可直接形成於導電線124曝露出來的表面上，且導電線124的導電材料於形成球下金屬層128的過程中提供了成核點。如同前面所討論，圖案化導電線124以提供封裝100中電路的電性佈線。因此，在封裝100的一些區域中(例如，在導電線124未出現的區域中)，可於晶種層134上直接形成球下金屬層128(未明確繪示)。在這樣的區域中，晶種層134提供了成核點以形成球下金屬層128。因此，在例示性的實施方式中，可單獨使用晶種層134來形成導電線124與球下金屬層128，以節省生產成本。舉例來說，在球下金屬層128形成前晶種層134未被蝕刻。
接著，如上所述移除遮罩層138。所形成的結構如第6A圖與第6B圖所繪示。第6A圖繪示剖面圖，且第6B圖繪示球下金屬層128對應的由上而下的視圖。球下金屬層128包 含溝槽130，溝槽130圍繞球下金屬層128的導電墊部位128’(見第6B圖)。在接下來的製程步驟中，外部的連接器132(例如焊球)設置於球下金屬層128的導電墊部位128’上。如第6B圖所繪示，維持牆部位128”圍繞溝槽130與導電墊部位128’。舉例來說，維持牆部位128”實體上被導電墊以空間(溝槽130)分隔。舉例來說，溝槽130的寬度W6為約10微米至約20微米。寬度W6對應到球下金屬層128的維持牆部位128”與導電墊部位128’形成的空間。舉例來說，維持牆部位128”的寬度W7為約10微米至約20微米。因此，可於導電線124與晶種層134上方形成具有圖案化的溝槽130於其中的球下金屬層128。
在形成球下金屬層128後，舉例來說，使用結合光微影和蝕刻的方法以圖案化晶種層134。舉例來說，移除部分未被導電線124或球下金屬層128覆蓋到的晶種層134。形成的結構繪示於第7圖中。接下來，在第8圖中，於高分子層108、導電線124與球下金屬層128上方形成高分子層126。高分子層126可覆蓋住球下金屬層128的邊緣部位。在一些實施方式中，使用適合的製程，例如化學氣相沉積(CVD)或其他方法，先共型地沉積高分子層126。舉例來說，接著使用光微影及/或蝕刻製程來圖案化高分子層126，以至少部分曝露出球下金屬層128。在封裝100中，可設置高分子層126的側牆於球下金屬層128的維持牆部位128”的上表面。
接下來，在第9圖中，將連接器132固定至球下金屬層128上。連接器132設置於球下金屬層128的導電墊部位128’上。在一些實施方式中，藉由一開始將助焊劑(未繪示) 放置於球下金屬層128的導電墊部位128’上，以固定連接器132。舉例來說，助焊劑可用刷、噴覆、模板或其他方式來進行添加。助焊劑一般具有酸性物質的成分，酸性物質可移除氧化物阻障，且酸性物質具有在製程中可防止產生滑動的黏合品質。助焊劑可同時放置於封裝100的球下金屬層128上。亦可使用其他種材料，例如焊膠(solder paste)、黏合劑或其他類似物以幫助黏合連接器132與球下金屬層128。
一旦助焊劑放置到位後，儘管可選擇性地使用任何適合的放置方法，使用例如，取放操作(pick and place operation)的方式，將連接器132實體上放置到與助焊劑接觸的位置。一旦連接器132與助焊劑接觸後，進行回流製程以將連接器132的材料與助焊劑回流，直至實體上將連接器132黏合與連接器132下方的球下金屬層128黏合。回流製程會造成化學反應，化學反應將消秏部分的球下金屬層及/或球下金屬層128下方的導電線124。因此，在足夠的厚度下(例如，在前面所給的例示性厚度範圍下)形成球下金屬層128與導電線124，以容許如此的回流形成的化學反應不損傷到下方的封裝特徵。並且，在回流過程中，助焊劑或連接器132的材料可從連接器132的下方側向地散開。使用溝槽132與維持牆部位128”來保持住如此的材料流動。因此，導電材料可被保持住而免於攻擊其他的元件特徵，進而降低生產時發生缺陷(例如，層別分離)的風險。
第10A圖繪示依據其他實施方式之封裝200的剖面圖，而第10B圖繪示10A圖對應的由上而下的視圖。封裝200 可類似封裝100，相似的參考符號指相似的元件。在封裝200中，高分子層126的至少一部位可設置於溝槽130中。也就是說，高分子層126可完全地覆蓋住球下金屬層128的維持牆部位128”。在封裝200中，側向尺寸W1至W5的大小關係為W1>W2>W4>W3>W5。
第11A圖繪示依據其他實施方式之封裝300的剖面圖，而第11B圖繪示11A圖對應的由上而下的視圖。封裝300可類似封裝100，相似的參考符號指相似的元件。在封裝300中，可在高分子層126中藉由開口曝露出整個球下金屬層128。也就是說，高分子層126並未覆蓋住球下金屬層128的任何部位，且高分子層126圍繞著球下金屬層128。在封裝300中，側向尺寸W1至W5的大小關係為W1>W3>W2>W4>W5。
第12圖繪示並例示依據各種不同的形成元件封裝的實施方式之流程圖。在步驟402中，於晶粒(例如，晶例102)上方形成晶種層(例如，晶種層134)。可於晶粒上方的扇出重新分配層(例如，重新分配層106)上方形成晶種層。在步驟404中，於晶種層上方形成導電線(例如，導電線124)。舉例來說，使用遮罩層(例如，遮罩層136)以定義導電線的形狀，且使用電鍍製程並使用晶種層以提供成核點來形成導電線。然後移除遮罩層。
在步驟406中，於導電線與晶種層上方形成遮罩層(例如，遮罩層138)。遮罩層可不同於形成導電層使用的遮罩層。在步驟408中，於遮罩層中圖案化開口(例如，開口140)。 開口可包含第一開口(例如，第一開口140A)以形成球下金屬層的導電墊部位(例如，導電墊部位128’)。開口可包含第二開口(例如，第二開口140B)以形成球下金屬層的維持牆部位(例如，維持牆部位128’)。仍可設置一部分的遮罩層於第一與第二開口之間。在步驟410中，於遮罩層中的開口中形成球下金屬層(例如，球下金屬層128)。舉例來說，可藉由填充第一開口以形成球下金屬層的導電墊部位，以及填充第二開口以形成球下金屬層的維持牆部位。在形成球下金屬層的過程中，導電線及/或晶種層可提供電鍍製程的成核點。然後，在步驟412中，移除遮罩層。
在步驟414中，於導電線與球下金屬層上方形成高分子層(例如，高分子層126)。位於高分子層中圖案化開口以曝露出球下金屬層。在一實施方式中，高分子層可覆蓋住球下金屬層的邊緣部位(例如，球下金屬層的維持牆的邊緣部位)。在一實施方式中，高分子層可完全曝露出球下金屬層。在一實施方式中，高分子層可完全覆蓋住球下金屬層的維持牆部位。在步驟416中，於球下金屬層上固定連接器(例如，連接器132)。連接器可固定於球下金屬層的導電墊部位上。
因此，在各種不同的實施方式中，於重新分配層的最上方的導電線形成球下金屬層。球下金屬層可包含導電墊部位與圍繞導電墊部位的維持牆部位，其中溝槽實體上分開了導電墊部位與維持牆部位。外部的連接器(例如，焊球)固定於球下金屬層的導電墊部位上，並執行回流製程以將連接器黏合至球下金屬層。藉由包含溝槽與維繞導電墊的維持牆，助焊劑 可在回流過程中被保持在球下金屬層中。因此，可降低由回流製程產生的層別分離問題，進而改善生產良率。甚至，單獨使用晶種層來形成球下金屬層與導電線，其有利地將低了生產成本。
雖然本揭露已以實施方式揭露如上，然其並不用以限定本揭露，任何熟習此技藝者，在不脫離本揭露的精神和範圍內，當可作各種的更動與潤飾，因此本揭露的保護範圍當視後附的申請專利範圍所界定者為準。封裝200可類似封裝100，相似的參考符號指相似的元件。
100‧‧‧封裝
102‧‧‧晶粒
104‧‧‧成型料件
106‧‧‧重新分配層
108、126‧‧‧高分子層
110‧‧‧接觸墊
112‧‧‧保護層
114‧‧‧導電柱
116‧‧‧介電層
118‧‧‧晶粒貼附膜
120‧‧‧載體
122‧‧‧導電特徵
122A、124‧‧‧導電線
122B‧‧‧導電通道
128‧‧‧球下金屬層
130‧‧‧溝槽
132‧‧‧連接器

Claims (10)

  1. 一種元件封裝，包含：一晶粒；複數個扇出重新分配層(fan-out redistribution layer,RDL)，位於該晶粒上方；一球下金屬層(under bump metallurgy,UBM)，位於該些扇出重新分配層上方，其中該球下金屬層包含：一導電墊部位；以及一溝槽，圍繞該導電墊部位；以及一連接器，設置於該球下金屬層的該導電墊部位上，其中該些扇出重新分配層將該連接器與該球下金屬層電性連接至該晶粒。
  2. 如請求項1所述之元件封裝，其中該球下金屬層更包含一維持牆部位圍繞該溝槽。
  3. 如請求項2所述之元件封裝，其中該連接器未設置於該球下金屬層的該維持牆部位上。
  4. 如請求項1所述之元件封裝，其中該些扇出重新分配層包含一導電線，其中該球下金屬層形成於該導電線之一上表面上，且其中該溝槽曝露出該導電線的一部位。
  5. 如請求項4所述之元件封裝，其中該些扇出重新分配層包含一高分子層延伸於該導電線之一上表面上方。
  6. 一種元件封裝，包含：一元件晶粒；一導電線，位於該元件晶粒上方且電性連接至該元件晶粒；一高分子層，延伸至該導電線的一上表面上方；一球下金屬層(under bump metallurgy,UBM)，形成於該導電線之一上表面上，其中該球下金屬層至少部分由該高分子層中的一開口曝露而出，且其中該球下金屬層包含：一導電墊部位；以及一維持牆部位，形成一環狀結構圍繞該導電墊部位，其中該維持牆部位與該導電墊部位被一溝槽分開；以及一焊球，位於該球下金屬層的該導電墊部位上。
  7. 如請求項6所述之元件封裝，其中該溝槽圍繞該導電墊部位，且其中該溝槽至少部分曝露出該導電線的該上表面。
  8. 一種元件封裝的形成方法，包含：於一晶粒上方形成一晶種層；於該晶種層上形成一導電線； 於該導電線與該晶種層上方形成一第一遮罩層；於該第二遮罩層中圖案化開口，其中該些開口包含：一第一開口，提供給一球下金屬層(under bump metallurgy,UBM)之一導電墊部位；以及一第二開口，提供給該球下金屬層之一維持牆部位，其中該第二開口形成一環狀結構圍繞該第一開口，且其中該第一遮罩層的一部分仍設置於該第一開口與該第二開口之間；於該第一開口與該第二開口中形成該球下金屬層；移除該第一遮罩層；以及固定一焊球至該球下金屬層的該導電墊部位。
  9. 如請求項8所述之元件封裝的形成方法，其中形成該導電線包含：於形成該第一遮罩層前，於該晶種層上方形成一第二遮罩層；於該第一遮罩層中圖案化一第三開口，其中該第三開口曝露出該晶種層；以及以一導電材料填滿該第三開口，以形成該導電線。
  10. 如請求項8所述之元件封裝的形成方法，更包含：於該球下金屬層上方形成一高分子層；以及圖案化該高分子層以曝露出該球下金屬層的至少一部位。
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