TWI714657B - 介電緩衝層 - Google Patents

介電緩衝層 Download PDF

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TWI714657B
TWI714657B TW105135262A TW105135262A TWI714657B TW I714657 B TWI714657 B TW I714657B TW 105135262 A TW105135262 A TW 105135262A TW 105135262 A TW105135262 A TW 105135262A TW I714657 B TWI714657 B TW I714657B
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Taiwan
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layer
redistribution
passivation layer
dielectric material
patternable
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TW105135262A
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TW201731056A (zh
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阿德維特 特朗
約翰吉拉德 穆爾黑德
凱文Ｊ 李
斯里蘭 派塔比拉曼
詹姆斯 鄭
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美商英特爾公司
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Abstract

本文揭示之實施例係有關於用於在一矽晶圓上形成一LMI著陸墊之方法。該方法包括在一基體上形成一重新分布層(RDL)；在該RDL及該基體上形成覆蓋該基體及該RDL的一鈍化層；在該鈍化層上形成一可圖案化介電材料層；處理該可圖案化介電材料層而暴露覆蓋該RDL的該鈍化層的一部分；處理覆蓋該RDL的該鈍化層的該部分而暴露該RDL的一部分；及在該RDL的該暴露部分上形成一LMI著陸墊。所得晶圓可包括具有一頂部及一側壁部的一重新分布線；覆蓋該側壁部的一鈍化層；覆蓋該鈍化層的一介電層；及覆蓋該重新分布線之該頂部的一金屬介面。

Description

介電緩衝層
本文揭示之實施例係有關於半導體處理，及更特別係有關於使用旋塗上電介質增加作為邏輯記憶體介面的緩衝層而保護免於鍍穿鈍化層縫隙。
於重新分布層(RDL)鍍覆處理之後，鈍化層係沈積於邏輯記憶體介面(LMI)層作為電介質以防止RDL線至線漏電及短路。因RDL線的高地形故，此種鈍化層具有縫隙，其於LMI鍍覆期間開啟，及造成縫隙中鍍覆出，導致線至線短路。又復，於製造處理之後縫隙中的脆弱區造成熱循環期間縫隙中的銅擠壓，及將導致裝置的早期故障。圖1為包括從鈍化層縫隙鍍覆出金屬的矽晶圓之示意圖。
依據本發明之一實施例，係特地提出一種裝置，其包含：一基體；具有一頂部及一側壁部的一重新分布線；至少部分地覆蓋該側壁部的一鈍化層；至少部分地覆蓋該鈍化層的一介電層；以及覆蓋該重新分布線之該頂部及與該重新分布線作電氣接觸的一金屬介面。
200、240、250、260、270、280、290:矽晶圓
202:基體
204、604:金屬線
206、606、658:鈍化層
208、608:縫隙
209:頂部
210:溝槽
211:側壁
212:可圖案化介電材料
214:LMI開口
216:已固化的可圖案化介電材料
218:鈍化層中的開口
300:方法流程圖
302-316:方塊
400:中介件
402:第一基體
404:第二基體
406:球柵陣列(BGA)
408:金屬互連件
410:通孔
412:貫穿矽通孔(TSV)
414:嵌入式裝置
500:計算裝置
501:前側
502:積體電路晶粒
503、552:重新分布層(RDL)
504:CPU
506:晶粒上記憶體
508:通訊邏輯單元
510:依電性記憶體
512:非依電性記憶體
514:圖形處理單元(GPU)
516:數位信號處理器(DSP)
520:晶片組
522:天線
524:顯示器或觸控螢幕顯示器
526:觸控螢幕控制器
528:全球定位系統(GPS)裝置
530:電池
532:運動共處理器或感測器
534:揚聲器
536:影像攝錄器
538:用戶輸入裝置
540:大容量儲存裝置
550、601:背側
600:示意圖
602:矽裝置晶圓
603:裝置側
616:可圖案化介電材料層
620:邏輯與記憶體介面(LMI)著陸墊
652:暫時矽載體晶圓
656:前端及後端層(FE/BE層)
662:凸塊、貫穿矽通孔(TSV)
圖1為包括從鈍化層縫隙鍍覆出金屬的矽晶圓之示意圖。
圖2A為依據本文揭示之實施例包括重新分布層及鈍化層的一矽晶圓之剖面示意圖。
圖2B為依據本文揭示之實施例帶有可圖案化介電材料的一矽晶圓之剖面示意圖。
圖2C為依據本文揭示之實施例帶有已經處理的可圖案化介電材料的一矽晶圓之剖面示意圖。
圖2D為依據本文揭示之實施例帶有已固化且可圖案化介電材料的一矽晶圓之剖面示意圖。
圖2E為依據本文揭示之實施例帶有經處理的鈍化層及已曝光重新分布層的一矽晶圓之剖面示意圖。
圖2F為依據本文揭示之實施例已進行清理處理的一矽晶圓之剖面示意圖。
圖2G為依據本文揭示之實施例帶有可圖案化介電材料的一矽晶圓之剖面示意圖。
圖3為依據本文揭示之實施例使用可圖案化介電材料在矽晶圓上形成鈍化層縫隙阻擋層之方法流程圖。
圖4為實施本文揭示之實施例的一中介件的示意方塊圖。
圖5為依據本文揭示之實施例建立的計算 裝置之示意方塊圖。
圖6為附接到矽載體晶圓的矽晶圓背側之示意圖。
本文中描述者為在鈍化層上方形成防衛層以保護於例如邏輯與記憶體介面著陸墊的非電解沈積期間之縫隙攻擊及析出。
本文揭示描述於LMI鈍化層沈積之後製造可圖案化緩衝層。可圖案化緩衝層將防止LMI鍍覆液接觸LMI鈍化層縫隙，及因而保護縫隙免於LMI鍍覆化學溶液的攻擊。
圖2A為依據本文揭示之實施例包括重新分布層及鈍化層的一矽晶圓200之剖面示意圖。於若干實施例中，圖2A-2G例示矽晶圓前側；於若干實施例中，圖2A-2G例示矽晶圓背側。矽晶圓背側係以進一步細節描述於圖6。矽晶圓200包括一基體202。基體可以是矽、氧化矽、或其它材料。矽晶圓200顯示已進行金屬鍍覆製程而形成分開金屬線204。舉例言之，分開金屬線可以是使用於重新分布層(RDL)中的金屬線。分開金屬線可包括一頂部209及一側壁211(或二側壁211)。相鄰分開金屬線204係由界定溝槽210的間隙分開。在形成鈍化層206之前，分開金屬線204間之基體202係暴露在溝槽210底部。於若干實施例中，分開金屬線係使用金屬鍍覆製程形成。分開金屬線可包括銅、鋁、或其它傳導性金屬。
矽晶圓200也包括鈍化層206，其覆蓋頂部209、側壁211、及溝槽210內部的暴露基體202。鈍化層206可包括氮化矽、碳化矽、摻碳氮化矽、氧氮化矽、及摻碳氧氮化矽。鈍化層206可作用來保護銅或其它金屬免於將造成RDL中之線路漏電或短路的橫跨溝槽210之擴散。
鈍化層206可以已知方式生成。經常，因分開金屬線204的相對高地形故，縫隙208將生成於鈍化層表面間。縫隙208藉由暴露出分開金屬線於被導入以產生邏輯與記憶體介面(LMI)著陸墊的金屬之非電解沈積而使得RDL對橫跨金屬線204的短路脆弱易感。
為了解決縫隙脆弱易感而造成短路問題，可圖案化介電材料212可被導引到溝槽，其防止非電解鍍覆浴溶液攻擊縫隙及鍍穿縫隙。圖2B為依據本文揭示之實施例帶有可圖案化介電材料的一矽晶圓240之剖面示意圖。可圖案化介電材料212可以是可光界定的、可光成像的、或可光圖案化的介電材料或能夠使用光刻技術或其它已知技術製作圖案的其它電介質。於若干實施例中，可圖案化介電材料212可以是正型可光學成像的介電材料。於若干實施例中，可圖案化介電材料可以是旋轉曝光顯影(SED)可圖案化材料。於若干實施例中，可圖案化介電材料212可經處理而形成永久膜(例如，可圖案化介電材料212可經固化而形成永久膜)。
可光界定介電材料實例包括但非僅限於： 得自陶氏化學(Dow Chemical)的英特維TM(InterViaTM)8000系列可光界定介電材料；得自陶氏化學的賽克羅廷TM(ClycloteneTM)4000系列可光界定介電材料；得自麥可肯(Microchem)的SU-8可光界定環氧樹脂材料；得自陶氏化學的WL-5000系列可光界定介電材料；得自普美勒(Promerus)的阿凡崔®(Avatrel®)可光界定介電材料；得自新越微矽(ShinEtsuMicroSi)的SINR系列可光界定介電材料；得自住友貝克萊公司(Sumitomo Bakelite Co,Ltd.)的SUMIRESIN EXCEL® CRC-8600系列可光界定介電材料；得自富士軟片(FujiFilm)的可光界定聚醯亞胺及PBO材料；得自東麗(Toray)的光尼斯TM(PhotoneeceTM)系列可光界定聚醯亞胺材料；得自旭化成電子材料公司(Asahi Kasei E-materials Corp.)的皮姆TM(PimelTM)可光界定聚醯亞胺及PBO材料；得自HD微系統(HD Microsystems)的可光界定聚醯亞胺材料；得自JSR微公司(JSR Micro,Inc.)的WPR系列可光界定介電材料；及得自杜邦(Dupont)的PerMXTM 3000系列光介電乾膜黏著劑。
可圖案化介電材料212可藉旋塗、乾膜積層、擠塗、或藉其它已知技術而導引到矽晶圓240。可圖案化介電材料212於鈍化層206上方，涵括於溝槽210中的鈍化層206，形成可圖案化介電材料。更明確言之，可圖案化介電材料212覆蓋由溝槽中的鈍化層所形成的縫隙208及其它位置208。可圖案化介電材料212可對抗被非電 解鍍覆液中的化學品降解，用以保護鈍化層縫隙208免受非電解鍍覆液之害。
可圖案化介電材料可包括下列特性中之一或多者：可圖案化介電材料與鍍覆液可相容，及允許鍍覆而不影響鍍膜的組成。
可圖案化介電材料防止LMI鍍覆液接觸LMI鈍化層縫隙，因而縫隙被保護免受LMI鍍覆化學溶液攻擊。
施加的可圖案化介電材料可製作圖案且與現有工具組可相容。
固化處理用於可圖案化介電材料，其係在針對貫穿矽通孔製程步驟要求的低溫進行。
可圖案化介電材料不與鍍覆液反應，且不變更鍍膜的鍍覆化學或組成。
可圖案化介電材料具有低應力，其防止製程期間晶圓的過度彎曲及防止在線路端點晶圓的額外應力。
可圖案化介電材料具有良好介電性質，本身作為介電阻擋層防止線路至線路短路。
可圖案化介電材料能夠倖存通過下游組裝製程。
圖2C為依據本文揭示之實施例帶有經處理的可圖案化介電材料的一矽晶圓250之剖面示意圖。於 圖2C中，可圖案化介電材料212可經處理而於鈍化層206上形成圖案。用於包括正光可成像或光可圖案化介電材料的可圖案化介電材料212，如業界眾所周知，遮蔽可被使用來將在分開金屬線204頂上的及鈍化層206頂上的，但非在期望LMI開口214位置的溝槽201上方的該等區域曝光於UV光；及在此等已曝光區域中的正光可成像或光可圖案化介電材料的可圖案化介電材料係於顯影製程中被去除。此種鈍化層206之已曝光部分係於圖2C中顯示為於可圖案化電介質製作圖案期間產生的LMI開口214。值得注意者為可圖案化介電材料被顯影之後，可圖案化介電材料212仍然覆蓋縫隙208。
圖2D為依據本文揭示之實施例帶有已固化的及可圖案化的介電材料的一矽晶圓260之剖面示意圖。於若干實施例中，矽晶圓260可經加熱而固化可圖案化介電材料212來形成永久膜(於圖2D中顯示為已固化可圖案化介電材料216)。已固化可圖案化介電材料216可耐受用來移除鈍化層206的蝕刻技術，使得縫隙208仍然由已固化可圖案化介電材料216所覆蓋。固化的溫度及時間係取決於使用的可圖案化介電材料之類型。
圖2E為依據本文揭示之實施例帶有經處理的鈍化層及已曝光重新分布層的一矽晶圓270之剖面示意圖。組成RDL的分開金屬線204係經曝光使得金屬可沈積到分開金屬線204上而形成電氣接點(亦即LMI著陸墊)。從可圖案化介電材料212顯影暴露出的鈍化層206可 使用已知技術蝕刻，諸如乾或濕蝕刻技術。蝕刻的結果是鈍化層中的開口218，其暴露分開金屬線204(例如，分開金屬線的頂部)而不暴露溝槽210，或更特別地，縫隙208。
圖2F為依據本文揭示之實施例已進行鈍化層後蝕刻清理處理的一矽晶圓280之剖面示意圖。於清理處理期間，蝕刻聚合物或其它污染物係自晶圓表面移除。
圖2G為依據本文揭示之實施例帶有可圖案化介電材料的一矽晶圓290之剖面示意圖。邏輯與記憶體介面(LMI)著陸墊能透過非電解鍍覆(無電鍍覆)而沈積到已暴露的分開金屬線204上。於圖2G中，著陸墊係顯示為非電解鍍覆表面精加工220。非電解鍍覆表面精加工220包括金屬，其於沈積後係與已暴露的分開金屬線204作電氣接觸。合宜的非電解鍍覆表面精加工包括但非僅限於：非電解CoP/浸沒Au、非電解CoWP/浸沒Au、非電解NiP/浸沒Au、非電解NiP/非電解Pd/浸沒Au、非電解Sn、非電解NiP/非電解Sn、非電解CoP/浸沒Au、非電解CoWP/非電解Sn、非電解Cu/非電解CoP/浸沒Au、非電解Cu/非電解CoWP/浸沒Au、非電解Cu/非電解NiP/浸沒Au、非電解Cu/非電解NiP/非電解Pd/浸沒Au、非電解Cu/非電解Sn、非電解Cu/非電解NiP/非電解Sn、非電解Cu/非電解CoP/浸沒Au、非電解Cu/非電解CoWP/非電解Sn。取決於採用的晶片對晶片焊接材料及/或晶片對晶片附接方法，其它表面精加工也可能適宜。鈍化層206及已固化可圖案化介電材料216防止非電解鍍覆液接觸溝槽210內部的分開金屬 線204(亦即藉由鍍穿縫隙208)。如此，已固化可圖案化介電材料將非電解金屬沈積隔離至各個分開金屬線204之頂暴露部。換言之，各個分開金屬線204包括LMI著陸墊且與其它分開金屬線204電氣絕緣。
於替代實施例中，C4或覆晶凸塊製作於著陸墊開口頂上而非進行表面精加工。C4或覆晶凸塊係使用業界已知技術製造，及可包括材料，諸如PbSn、Sn、SnAg、Cu、In、SnAgCu、SnCu、Au等。
圖3為依據本文揭示之實施例使用可圖案化介電材料在矽晶圓上形成鈍化層縫隙阻擋層之方法流程圖300。於若干實施例中，鈍化層縫隙阻擋層可形成於矽前側上；及於若干實施例中，鈍化層縫隙阻擋層可形成於矽背側上。於矽晶圓上，能形成重新分布層(302)。重新分布層可包括藉鍍覆，諸如電解或非電解沈積或其它已知技術形成的多個分開的(例如，彼此絕緣的)金屬線。分開金屬線可以是銅、鋁、或其它金屬。
鈍化層可形成於RDL上方(304)。鈍化層可覆蓋側壁及各個分開金屬線頂上及各金屬線間的已暴露矽基體。鈍化層可在接頭形成縫隙，或從沈積程序(例如，化學氣相沈積技術)鈍化層彼此會合位置形成縫隙。舉例言之，於分開金屬線間之溝槽內形成縫隙。所形成的縫隙對使用來形成邏輯與記憶體介面著陸墊的非電解沈積程序中的化學品攻擊脆弱易感。此種攻擊的結果可能導致非電解沈積溶液接觸分開金屬線的金屬及造成非電解鍍穿縫隙。 金屬過溝槽中的縫隙鍍覆出可造成相鄰分開金屬線間短路。
可圖案化介電材料層可形成於鈍化層上方(306)。特別，可形成可圖案化介電材料層來覆蓋鈍化層包括縫隙。可圖案化介電材料層可藉旋塗、乾膜積層、擠塗、或藉其它已知技術形成。可圖案化介電材料層可包括可圖案化介電材料，諸如正型可光學成像或可光圖案化介電材料，或旋轉曝光顯影(SED)可圖案化電介質。
可圖案化介電材料可經處理而暴露鈍化層頂部(308)。可圖案化介電材料可藉光刻術處理來去除覆蓋鈍化層的可圖案化介電材料之部分(例如，分開金屬線之頂部上的鈍化層)。可圖案化電介質的處理不應去除覆蓋鈍化層縫隙的可圖案化介電材料。作為可圖案化介電材料之處理的部分，可圖案化介電材料可經固化(310)。固化可圖案化介電材料可形成永久膜，該膜可耐受鈍化層的蝕刻，基體及其它層的清理，及LMI著陸墊的非電解鍍覆。
覆蓋分開金屬線的鈍化層可經處理而暴露分開金屬線之部分(312)。鈍化層可經蝕刻，諸如藉乾蝕刻、濕蝕刻、或藉其它已知技術蝕刻。蝕刻處理不應影響可圖案化介電材料。
清理處理能被使用來去除蝕刻聚合物或其它污染物，或以其它方式準備已暴露的金屬表面用於隨後處理。
LMI著陸墊可形成於已暴露的分開金屬線 上(316)。LMI著陸墊能使用非電解沈積形成。非電解沈積可沈積金屬至金屬線上，諸如前述金屬。非電解沈積化學品被阻止不攻擊縫隙，原因在於縫隙係由已固化的可圖案化介電材料覆蓋。藉由防止非電解沈積化學品攻擊縫隙，非電解沈積化學品。
於本文描述中，具體實施例的各種面向將使用熟諳技藝人士常用的術語描述來傳遞其工作實質給其它熟諳技藝人士。然而，熟諳技藝人士顯然易知可只以所描述面向中之部分而實施本文揭示。為了解說目的，闡明特定數目、材料、及組態以供徹底瞭解具體實施例。然而，熟諳技藝人士顯然易知可以無特定細節實施本文揭示。於其它情況下，眾所周知之特徵經刪除或簡化以免遮掩了具體實施例。
轉而，以最有助於瞭解本文揭示之方式描述各項操作呈多個分開操作，然而，描述的排序不應解譯為暗示此等操作必然為順序相依性。特別，此等操作無需以呈現的順序進行。
如於本文中使用，術語「於其上方」、「於其下方」、「於其間」、及「於其上」係指一個材料層或組件相對於其它層或組件的相對位置。舉例言之，設置於另一層上方或下方的一層可以直接接觸另一層，或可有一或多個中介層。再者，設置於兩層間的一層可以直接接觸該等二層，或可有一或多個中介層。相反地，第一層於第二層「上」係與第二層直接接觸。同理，除非另行明白陳 述，否則設置於兩個特徵間的一特徵可以直接接觸該等相鄰特徵，或可有一或多個中介層。
本文揭示之實施例可於基體諸如半導體基體上形成或進行。於一個實施例中，半導體基體可以是使用大塊矽或絕緣體上矽子結構形成的結晶性基體。於其它實施例中，半導體基體可使用其它材料其可以或可不組合矽製成，其包括但非僅限於鍺、銻化銦、碲化鉛、砷化銦、磷化銦、砷化鎵、砷化銦鎵、銻化鎵、或III-V族或IV族材料的其它組合。雖然本文描述可自其形成基體的數個材料實例，但可作為基礎在其上建立半導體裝置的任何材料皆係落入於本文揭示之精髓與範圍內。
多個電晶體諸如金氧半場效電晶體(MOSFET或簡稱MOS電晶體)可製作於基體上。於本文揭示之各種實施例中，MOS電晶體可以是平面電晶體、非平面電晶體、或兩者的組合。非平面電晶體包括鰭式FinFET電晶體諸如雙閘電晶體及三閘電晶體，及包裹或全包裹閘電晶體諸如奈米帶或奈米線電晶體。雖然本文描述的實施例可僅例示平面電晶體，但須注意本文揭示也可使用非平面電晶體進行。
各個MOS電晶體包括由至少兩層形成的閘堆疊，一閘介電層及一閘電極層。閘介電層可包括一層或一層堆疊。一或多層可包括氧化矽、二氧化矽(SiO2)及/或高k介電材料。高k介電材料可包括元素諸如鉿、矽、氧、鈦、鉭、鑭、鋁、鋯、鋇、鍶、釔、鉛、鈧、鈮、及鋅。 可使用於閘介電層的高k材料之實例包括，但非限制性，氧化鉿、氧化鉿矽、氧化鑭、氧化鑭鋁、氧化鋯、氧化鋯矽、氧化鉭、氧化鈦、氧化鋇鍶鈦、氧化鋇鈦、氧化鍶鈦、氧化釔、氧化鋁、氧化鉛鈧鉭、及鈮酸鉛鋅。於若干實施例中，當使用高k材料時，退火處理可於閘介電層上進行以改良其品質。
閘電極層係形成於閘介電層上，及取決於電晶體是否為PMOS或NMOS電晶體，可由至少一個P型功函數金屬或N型功函數金屬組成。於若干實施例中，閘電極層可由一堆疊之二或多金屬層組成，於該處一或多個金屬層為功函數金屬層，及至少一個金屬層為填充金屬層。可包括用於其它目的的進一步金屬層，諸如障壁層。
至於PMOS電晶體，可用於閘電極的金屬包括，但非限制性，釕、鈀、鉑、鈷、鎳、及傳導性金屬氧化物，例如氧化釕。P型金屬層將使其能形成具有約4.9eV至約5.2eV間之功函數的PMOS閘電極。至於NMOS電晶體，可用於閘電極的金屬包括，但非限制性，鉿、鋯、鈦、鉭、鋁、此等金屬的合金、及此等金屬之碳化物諸如碳化鉿、碳化鋯、碳化鈦、碳化鉭、碳化鋁。N型金屬層將使其能形成具有約3.9eV至約4.2eV間之功函數的NMOS閘電極。
於若干實施例中，當沿源極-通道-汲極方向觀看為電晶體的剖面時，閘電極可由「U」字形結構組成，其包括實質上平行基體表面的底部及實質上垂直基體 頂面的二側壁部。於另一個實施例中，形成閘電極的該等金屬層中之至少一者可單純為實質上平行基體頂面而不包括實質上垂直基體頂面的側壁部的平面層。於本文揭示之進一步實施例中，閘電極可由U字形結構與平面非U字形結構的組合組成。舉例言之，閘電極可由一或多個U字形金屬層形成於一或多個平面非U字形層頂上組成。
於本文揭示之若干實施例中，一對側壁隔件可形成於閘堆疊的相對兩側上而括住該閘堆疊。側壁隔件可自諸如氮化矽、氧化矽、碳化矽、摻碳氮化矽、及氧氮化矽的材料製成。側壁隔件之形成方法為業界眾所周知及大致包括沈積及蝕刻處理步驟。於替代實施例中，可使用多對隔件，例如二對、三對、或四對側壁隔件可形成於閘堆疊的相對兩側上。
如業界眾所周知，源及汲區係形成於基體內部相鄰各個MOS電晶體的閘堆疊。源及汲區通常係使用植入/擴散法或蝕刻/沈積法製成。於前一方法中，摻雜劑諸如硼、鋁、銻、磷、或砷可離子植入基體內而形成源及汲區。活化摻雜劑及造成摻雜劑進一步擴散入基體內的退火處理典型地接續在離子植入處理之後。在後者處理中，基體可先經蝕刻而在源及汲區的位置形成凹部。然後，可進行磊晶沈積處理而以用來製造源及汲區的材料填補凹部。於若干實施例中，源及汲區可使用矽合金諸如矽鍺或碳化矽製造。於若干實施例中，磊晶沈積矽合金可以摻雜劑諸如硼、砷、或磷原位摻雜。於進一步實施例中，源及 汲區可使用一或多個替代半導體材料諸如鍺或III-V族金屬或合金製成。及於進一步實施例中，一或多層金屬及/或合金可使用來形成源及汲區。
一或多個層間電介質(ILD)係沈積於MOS電晶體上方。ILD層可使用已知其可應用於積體電路結構的介電材料製成，諸如低k介電材料。有用的介電材料之實例包括，但非限制性，二氧化矽(SiO2)、摻碳氧化物(CDO)、氮化矽、有機聚合物諸如全氟環丁烷或聚四氟乙烯、氟矽酸鹽玻璃(FSG)、及有機矽酸鹽諸如倍半矽氧烷、矽氧烷、或有機矽酸鹽玻璃。ILD層可包括孔口或氣隙來進一步減低其介電常數。
圖4為依據本文揭示之實施例一中介件1000的示意方塊圖。中介件400為用來橋接第一基體402至第二基體404的中介基體。第一基體402可以是例如積體電路晶粒。第二基體404可以是例如記憶體模組、電腦主機板、或其它積體電路晶粒。一般而言，中介件400之目的係用以展開連結至更寬的間距或用以重新安排一連結的路徑到一不同的連結。舉例言之，中介件400可耦合積體電路晶粒到球柵陣列(BGA)406，其隨後可耦合至第二基體404。於若干實施例中，第一及第二基體402/404係附接到中介件400的對側。於其它實施例中，第一及第二基體402/404係附接到中介件400的同側。及於進一步實施例中，三或多個基體係藉由中介件400互連。
中介件400可由環氧樹脂、玻璃纖維加強 環氧樹脂、陶瓷材料、或聚合物材料諸如聚醯亞胺製成。於進一步實施例中，中介件可由其它剛性或撓性材料製成，其可包括前述用於半導體基體的相同材料，諸如矽、鍺、及其它III-V族及IV族材料。
中介件可包括金屬互連件408及通孔410，包括但非僅限於貫穿矽通孔(TSV)412。中介件400可進一步包括嵌入式裝置414，包括被動及主動裝置二者。此等裝置包括，但非限制性，電容器、解耦電容器、電阻器、電感器、熔絲、二極體、變壓器、感測器、及靜電放電(ESD)裝置。更複雜裝置諸如射頻(RF)裝置、功率放大器、天線、陣列、感測器及MEMS裝置也可形成於中介件400上。
依據本文揭示之實施例，本文中描述的設備或方法可使用於中介件400的製造。
圖5為依據本文揭示之實施例的計算裝置500。計算裝置500可包括前側501及背側550。計算裝置500具有多個組件，其中部分駐在前側501上。於一個實施例中，此等組件係附接至一或多個主機板。於替代實施例中，此等組件中之部分或全部係製作到單一單晶片系統(SoC)晶粒上。計算裝置500中的組件包括，但非限制性，積體電路晶粒502及至少一個通訊邏輯單元508。於若干實施例中，通訊邏輯單元508係製作在積體電路晶粒502內部，而於其它實施例中，通訊邏輯單元508係製作於分開的積體電路晶片中，該晶片可連結到與積體電路晶粒502 分享的或電子耦合的基體或主機板。積體電路晶粒502可包括CPU 504以及晶粒上記憶體506，其常被使用作為快取記憶體，其可藉諸如嵌入式DRAM(eDRAM)或旋轉轉移矩記憶體(STTM或STT-MRAM)技術提供。
計算裝置500可包括其它組件，其可以或可不實體上及電氣上耦合至主機板，或製作於SoC晶粒內部。此等其它組件包括，但非限制性，依電性記憶體510(例如，DRAM)、非依電性記憶體512(例如，ROM或快閃記憶體)、圖形處理單元514(GPU)、數位信號處理器516、密碼處理器542(於硬體內部執行密碼演算法的特化處理器)、晶片組520、天線522、顯示器或觸控螢幕顯示器524、觸控螢幕控制器526、電池530或其它電源、功率放大器(未顯示於圖中)、電壓調節器(未顯示於圖中)、全球定位系統(GPS)裝置528、運動共處理器或感測器532(其可包括加速度計、迴轉儀、及羅盤)、揚聲器534、影像攝錄器536、用戶輸入裝置538(諸如鍵盤、滑鼠、觸控筆、觸控板)、及大容量儲存裝置540(諸如硬碟驅動裝置、光碟(CD)、數位影音碟(DVD)及依此類推)。
通訊邏輯單元508使其能無線通訊用於將資料移轉至及自計算裝置500。術語「無線」及其衍生詞可使用來描述電路、裝置、系統、方法、技術、通訊通道等，其可透過使用經調變的電磁輻射通過非固體媒體而通訊資料。該術語並非暗示相關聯的裝置不含任何導線，但於若干實施例中可能不含。通訊邏輯單元508可實施眾多 無線標準或協定中之任一者，包括但非僅限於Wi-Fi(IEEE 802.11家族)、WiMAX(IEEE 802.16家族)、IEEE 802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍牙、其衍生物、以及標示為3G、4G、5G、及其後的任何其它無線協定。計算裝置500可包括多個通訊邏輯單元508。例如第一通訊邏輯單元508可專用於短程無線通訊諸如Wi-Fi及藍牙，及第二通訊邏輯單元508可專用於長程無線通訊諸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO、及其它。
計算裝置500的處理器504包括依據本文揭示之實施例形成的一或多個裝置，諸如電晶體或金屬互連件。術語「處理器」可指處理得自暫存器及/或記憶體的電子資料以將該電子資料變換成可儲存於暫存器及/或記憶體的其它電子資料之任何裝置或裝置部分。
通訊邏輯單元508也可包括依據本文揭示之實施例形成的一或多個裝置，諸如電晶體或金屬互連件。
於進一步實施例中，罩在計算裝置500殼體內部的另一個組件可含有依據本文揭示之實施例形成的一或多個裝置，諸如電晶體或金屬互連件。
於各種實施例中，計算裝置500可以是膝上型電腦、小筆電、筆記型電腦、超筆電、智慧型電話、平板、個人數位助理器(PDA)、超行動PC、行動電話、桌上型電腦、伺服器、列印器、掃描器、監視器、機上盒、 娛樂控制單元、數位影像攝錄器、可攜式音樂播放器、或數位視訊紀錄器。於進一步實施例中，計算裝置500可以是處理資料的任何其它電子裝置。
背側550可包括重新分布層(RDL)552。前文引述之組件中之一或多者可使用形成RDL 552的金屬線互連。依據本文揭示之實施例，各個金屬線可透過形成於計算裝置背側550上的通孔或邏輯與記憶體介面著陸墊存取。舉例言之，背側550可包括具有頂部及側壁部的重新分布層金屬線；至少部分地覆蓋側壁部的鈍化層；至少部分地覆蓋鈍化層的介電層；及覆蓋重新分布線路頂部且與其電氣接觸的金屬介面。於若干實施例中，前側501也可包括依據本文揭示之實施例的RDL 503及鈍化層縫隙緩衝。
圖6為附接到矽載體晶圓的矽裝置晶圓背側之示意圖600。圖6顯示如於圖2A-2G中顯示的相似組件。依據本文揭示之實施例，矽裝置晶圓602包括具有特徵的背側601，諸如分開金屬線604、鈍化層606(其可以是氮化矽層)、保護鈍化層606中之縫隙608的可圖案化介電材料層616、及邏輯與記憶體介面(LMI)著陸墊620。
矽裝置晶圓602也包括裝置側603。背側601上的特徵可藉貫穿矽通孔(TSV)662而電氣鏈接到裝置側上的特徵。在裝置側上，矽裝置晶圓602可包括前端及後端層(FE/BE層)656、硬鈍化層658、及一或多個凸塊662。凸塊662係電氣連結到矽裝置晶圓602之裝置側603 上的後端金屬布線層656。背側601處理結束之後，已減薄的矽裝置晶圓602係從暫時矽載體晶圓652脫離，及已減薄的矽裝置晶圓602被切割成個別晶片。然後在各個個別晶片上的凸塊662例如藉由焊接處理而電氣連結到晶片封裝件。
示意圖600顯示矽晶圓602如何能被攜載於矽載體晶圓652上。矽裝置晶圓602可藉一層膠或其它黏著劑654而固定至矽載體晶圓。
以下段落提出本文描述的實施例中之各者的實例。
實例1為一種裝置其包括一基體；具有一頂部及一側壁部的一重新分布線；至少部分地覆蓋該側壁部的一鈍化層；至少部分地覆蓋該鈍化層的一介電層；及覆蓋該重新分布線之該頂部及與其作電氣接觸的一金屬介面。
實例2可包括實例1的主旨，其中該鈍化層包含氮化矽、碳化矽、摻碳氮化矽、氧氮化矽、或摻碳氧氮化矽中之一者或一組合。
實例3可包括實例1的主旨，其中該介電層包含一可圖案化介電材料。
實例4可包括實例1或2或3中之任一者的主旨，其中該介電層包含一旋轉曝光顯影電介質。
實例5可包括實例1或2或3或4中之任一者的主旨，其中該介電層包含一永久膜。
實例6可包括實例1或2或3或4或5中之任一者的主旨，其中該金屬介面包含一邏輯與記憶體介面(LMI)。
實例7可包括實例1或2或3或4或5或6中之任一者的主旨，其中該重新分布線包含銅或鋁。
實例8可包括實例1或2或3或4或5或6或7中之任一者的主旨，其中該重新分布線、該鈍化層、該介電層、及該金屬介面位在一矽晶圓背側上。
實例9為一種用於在一矽晶圓之一背側上形成一邏輯與記憶體介面(LMI)著陸墊之方法，該方法包括在一基體上形成一重新分布層；在該重新分布層及該基體上形成覆蓋該基體及該重新分布層的一鈍化層；在該鈍化層上形成一可圖案化介電材料層；處理該可圖案化介電材料層而暴露覆蓋該重新分布層的該鈍化層之一部分；處理覆蓋該重新分布層的該鈍化層之該部分而暴露該重新分布層的一部分；及在該重新分布層之該暴露部分上，形成與該重新分布層作電氣接觸的一LMI著陸墊。
實例10可包括實例9的主旨，其中形成該可圖案化介電材料層包含在該可圖案化介電材料層上旋轉。
實例11可包括實例9或10中之任一者的主旨，其中該可圖案化介電材料層包含一正型可光學成像介電材料。
實例12可包括實例9或10或11中之任一者 的主旨，其中該可圖案化介電材料層包含一旋轉曝光顯影(SED)材料。
實例13可包括實例9或10或11或12中之任一者的主旨，其中處理該可圖案化介電材料層包括遮蔽該可圖案化介電材料層的一第一部分；將該可圖案化電介質之一第二部分曝光至一光源以自該鈍化層移除該第二部分而暴露該鈍化層的該部分。
實例14可包括實例9或10或11或12或13中之任一者的主旨，其中處理該可圖案化介電材料層進一步包含固化該可圖案化介電材料層而形成一永久膜。
實例15可包括實例9或10或11或12或13或14中之任一者的主旨，其中形成該重新分布層包含銅之電解或非電解鍍覆。
實例16可包括實例9或10或11或12或13或14或15中之任一者的主旨，其中形成該LMI著陸墊包含藉非電解沈積而沈積該LMI著陸墊。
實例17可包括實例9或10或11或12或13或14或15或16中之任一者的主旨，其中處理該鈍化層之該部分包含蝕刻該鈍化層之該部分。
實例18可包括實例9或10或11或12或13或14或15或16或17中之任一者的主旨，其中在該鈍化層上形成該可圖案化介電材料層包含覆蓋形成於該鈍化層中之一或多個縫隙；及其中處理覆蓋該重新分布層的該鈍化層之該部分包含維持該可圖案化介電材料層覆蓋形成於該鈍 化層中之一或多個縫隙。
實例19為一種計算裝置其包括包含一裝置側及一背側的一基體。該裝置側可包括一處理器；於該處理器內部的一通訊邏輯單元；於該處理器內部的一記憶體；於該計算裝置內部的一圖形處理單元；於該計算裝置內部的一天線；於該處理器內部的一功率放大器；及於該處理器內部的一電壓調節器。該背側可包括具有一頂部及一側壁部的一重新分布線；至少部分地覆蓋該側壁部的一鈍化層；至少部分地覆蓋該鈍化層的一介電層；及覆蓋該重新分布線之該頂部及與其作電氣接觸的一金屬介面。
實例20可包括實例19的主旨，其中該鈍化層包含氮化矽。
實例21可包括實例19或20中之任一者的主旨，其中該介電層包含一可圖案化介電材料。
實例22可包括實例19或20或21中之任一者的主旨，其中該介電層包含一永久膜。
實例23可包括實例19或20或21或22中之任一者的主旨，其中該金屬介面包含一邏輯與記憶體介面(LMI)。
實例24可包括實例9或10或11或12或13或14或15或16或17或18中之任一者的主旨，其中該LMI著陸墊係形成於一矽晶圓背側上。
如上本文揭示之例示性實施例的描述，包括於發明摘要部分中描述者，並非意圖為竭盡的或限制本 文揭示於所揭露的精準形式。雖然舉出其特定實施例及其實例，但本文揭示係本文中描述用於例示性目的，如熟諳技藝人士將瞭解於本文揭示之範圍內部的各種相當修改皆屬可能。
202:基體
204:已鍍覆的金屬線
206:鈍化層
208:鈍化層形成後存在的縫隙
216:已硬化的可圖案化介電材料
220:非電解鍍覆表面精加工
290:矽晶圓

Claims (23)

  1. 一種矽基裝置，其包含：一基體；包含一第一重新分布線和一第二重新分布線的至少兩個重新分布線，該等重新分布線各具有一頂部及一側壁部；至少部分覆蓋該等第一和第二重新分布線之該等側壁部的一鈍化層；一介電層，其至少部分覆蓋該鈍化層、且實質填滿在該等第一和第二重新分布線間之未受該鈍化層佔據的空間；以及包含一第一金屬介面和一第二金屬介面的至少兩個金屬介面，該第一金屬介面覆蓋該第一重新分布線之該頂部且電氣式接觸該第一重新分布線，該第二金屬介面覆蓋該第二重新分布線之該頂部且電氣式接觸該第二重新分布線。
  2. 如請求項1之裝置，其中，該鈍化層包含氮化矽、碳化矽、摻碳氮化矽、氧氮化矽、或摻碳氧氮化矽其中一者或一組合。
  3. 如請求項1之裝置，其中，該介電層包含一可圖案化介電材料。
  4. 如請求項1之裝置，其中，該介電層包含一旋轉曝光顯影(SED)電介質。
  5. 如請求項1之裝置，其中，該介電層包含 一永久膜。
  6. 如請求項1之裝置，其中，該金屬介面包含一邏輯與記憶體介面(LMI)。
  7. 如請求項1之裝置，其中，該等重新分布線包含銅或鋁。
  8. 如請求項1之裝置，其中，該等重新分布線、該鈍化層、該介電層、及該金屬介面係位在一矽晶圓背側上。
  9. 一種用於在矽晶圓之背側上形成邏輯與記憶體介面(LMI)著陸墊的方法，該方法包含下列步驟：在一基體上形成一重新分布層，該重新分布層包含一第一重新分布線和一第二重新分布線，該等第一和第二重新分布線被一間隙隔開，該間隙界定出一溝槽；在該重新分布層及該基體上形成覆蓋該基體及該重新分布層的一鈍化層；在該鈍化層上形成實質填滿該溝槽的一可圖案化介電材料層；處理該可圖案化介電材料層，以暴露出覆蓋該重新分布層的該鈍化層的一部分；處理覆蓋該重新分布層的該鈍化層的該部分，以暴露出該重新分布層的一部分；以及在該重新分布層之受暴露的該部分上形成電氣式接觸該第一重新分布線的一第一LMI著陸墊和電氣式接觸該第二重新分布線的一第二LMI著陸墊。
  10. 如請求項9之方法，其中，形成該可圖案化介電材料層的步驟包含：在該可圖案化介電材料層上進行旋轉作業。
  11. 如請求項9或10之方法，其中，該可圖案化介電材料層包含一正型可光學成像介電材料。
  12. 如請求項9之方法，其中，該可圖案化介電材料層包含一旋轉曝光顯影(SED)材料。
  13. 如請求項9之方法，其中，處理該可圖案化介電材料層的步驟包含：遮蔽該可圖案化介電材料層的一第一部分；向一光源暴露該可圖案化介電材料層的一第二部分，以將該第二部分自該鈍化層移除，而暴露出該鈍化層之該部分。
  14. 如請求項9之方法，其中，處理該可圖案化介電材料層的步驟進一步包含：固化該可圖案化介電材料層以形成一永久膜。
  15. 如請求項9之方法，其中，形成該重新分布層的步驟包含：進行銅的電解或非電解鍍覆。
  16. 如請求項9之方法，其中，形成該等第一和第二LMI著陸墊的步驟包含；藉由非電解沈積而沈積該等第一和第二LMI著陸墊。
  17. 如請求項9之方法，其中，處理該鈍化層之該部分的步驟包含：蝕刻該鈍化層之該部分。
  18. 如請求項9之方法，其中： 在該鈍化層上形成該可圖案化介電材料層的步驟包含：覆蓋形成於該鈍化層中的一或多個縫隙；並且處理覆蓋該重新分布層的該鈍化層的該部分之步驟包含：使該可圖案化介電材料層持續覆蓋形成於該鈍化層中的該一或多個縫隙。
  19. 一種計算裝置，其包含：一基體，其具有一裝置側及一背側；位在該裝置側上的數個裝置，該等裝置包含：一處理器；在該處理器內的一通訊邏輯單元；在該處理器內的一記憶體；在該計算裝置內的一圖形處理單元；在該計算裝置內的一天線；在該處理器內的一功率放大器；及在該處理器內的一電壓調節器；以及位在該背側上的數個特徵件，該等特徵件包含：包含一第一重新分布線和一第二重新分布線的至少兩個重新分布線，該等重新分布線各具有一頂部及一側壁部；至少部分覆蓋該等第一和第二重新分布線之該等側壁部的一鈍化層；一介電層，其至少部分覆蓋該鈍化層、且實質填滿在該等第一和第二重新分布線間之未受該鈍化層佔據的空間；及 包含一第一金屬介面和一第二金屬介面的至少兩個金屬介面，該第一金屬介面覆蓋該第一重新分布線之該頂部且電氣式接觸該第一重新分布線，該第二金屬介面覆蓋該第二重新分布線之該頂部且電氣式接觸該第二重新分布線。
  20. 如請求項19之裝置，其中，該鈍化層包含氮化矽。
  21. 如請求項19之裝置，其中，該介電層包含一可圖案化介電材料。
  22. 如請求項19之裝置，其中，該介電層包含一永久膜。
  23. 如請求項19之裝置，其中，該金屬介面包含一邏輯與記憶體介面(LMI)。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW393753B (en) * 1997-09-29 2000-06-11 Siemens Ag Improved multi-level conductive structure and method therefor
US20060108609A1 (en) * 2004-11-22 2006-05-25 International Business Machines Corporation Barrier Dielectric Stack for Seam Protection
TWI443798B (zh) * 2011-01-25 2014-07-01 Taiwan Semiconductor Mfg 積體電路與其形成方法
US20140252292A1 (en) * 2013-03-06 2014-09-11 Brian Clarke Balcony blockout insert
US20150187608A1 (en) * 2013-12-26 2015-07-02 Sanka Ganesan Die package architecture with embedded die and simplified redistribution layer

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10346460A1 (de) * 2003-10-02 2005-05-19 Infineon Technologies Ag Anordnung und Verfahren zum Schutz von Fuses/Anti-Fuses
US10204876B2 (en) * 2013-03-07 2019-02-12 Maxim Integrated Products, Inc. Pad defined contact for wafer level package
US9245795B2 (en) * 2013-05-28 2016-01-26 Intel Corporation Methods of forming substrate microvias with anchor structures

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW393753B (en) * 1997-09-29 2000-06-11 Siemens Ag Improved multi-level conductive structure and method therefor
US20060108609A1 (en) * 2004-11-22 2006-05-25 International Business Machines Corporation Barrier Dielectric Stack for Seam Protection
TWI443798B (zh) * 2011-01-25 2014-07-01 Taiwan Semiconductor Mfg 積體電路與其形成方法
US20140252292A1 (en) * 2013-03-06 2014-09-11 Brian Clarke Balcony blockout insert
US20150187608A1 (en) * 2013-12-26 2015-07-02 Sanka Ganesan Die package architecture with embedded die and simplified redistribution layer

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