Classifications

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  • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
  • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
  • H01L23/49894—Materials of the insulating layers or coatings
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  • H01L23/5329—Insulating materials
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  • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L23/5385—Assembly of a plurality of insulating substrates
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  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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Definitions

• the silicon wafer 200 also includes a passivation layer 206 that covers the top portion 209, the sidewalls 211, and the exposed substrate 202 within the trench 210.
• the passivation layer 206 can include silicon nitride, silicon carbide, carbon doped silicon nitride, silicon oxynitride, and carbon-doped silicon oxynitride.
• the passivation layer 206 can act to protect copper or other metals from diffusion across the trench 210 that would cause line leakage or short circuit in the RDL.
• Implementations of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate.
• the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure.
• the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present disclosure.
• FIG. 4 is a schematic block diagram of an interposer 1000 in accordance with embodiments of the present disclosure.
• the interposer 400 is an intervening substrate used to bridge a first substrate 402 to a second substrate 404.
• the first substrate 402 may be, for instance, an integrated circuit die.
• the second substrate 404 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die.
• the purpose of an interposer 400 is to spread a connection to a wider pitch or to reroute a connection to a different connection.
• the interposer 400 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide.
• the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
• the interposer may include metal interconnects 408 and vias 410, including but not limited to through-silicon vias (TSVs) 412.
• the interposer 400 may further include embedded devices 414, including both passive and active devices.
• Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices.
• More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 400.
• RF radio-frequency
• the communications logic unit 508 enables wireless communications for the transfer of data to and from the computing device 500.
• wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
• the computing device 500 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
• the computing device 500 may be any other electronic device that processes data.
• FIG. 6 is a schematic diagram 600 of a silicon device wafer backside attached to a silicon carrier wafer.
• FIG. 6 shows similar components as shown in FIGS. 2A-2G.
• the silicon device wafer 602 includes a backside 601 that has features, such as the discrete metal lines 604, the passivation layer 606 (which can be a silicon nitride layer), the patternable dielectric material layer 616 that protects the seams 608 in the passivation layer 606, and the logic/memory interface (LMI) landing pads 620, in accordance with embodiments of the present disclosure.
• the discrete metal lines 604 which can be a silicon nitride layer
• the patternable dielectric material layer 616 that protects the seams 608 in the passivation layer 606, and the logic/memory interface (LMI) landing pads 620, in accordance with embodiments of the present disclosure.
• LMI logic/memory interface
• Example 1 is a device that includes a substrate, a redistribution line having a top portion and a sidewall portion, a passivation layer at least partially covering the sidewall portion, a dielectric layer at least partially covering the passivation layer; and a metal interface covering the top portion of and in electrical contact with the redistribution line.
• Example 9 is a method for forming a logic/memory interface (LMI) landing pad on a silicon wafer, the method including forming, on a substrate, a redistribution layer; forming, on the redistribution layer and the substrate, a passivation layer covering the substrate and the redistribution layer; forming, on the passivation layer, a pattemable dielectric material layer; processing the pattemable dielectric material layer to expose a portion of the passivation layer covering the redistribution layer; processing the portion of the passivation layer covering the redistribution layer to expose a portion of the redistribution layer; and forming, on the exposed portion of the redistribution layer, an LMI landing pad in electrical contact with the redistribution layer.
• LMI logic/memory interface
• Example 13 may include the subject matter of any of examples 9 or 10 or 11 or 12, wherein processing the pattemable dielectric material layer includes masking a first portion of the pattemable dielectric material layer and exposing a second portion of the patternable dielectric to a light source to remove the second portion from the passivation layer to expose the portion of the passivation layer.
• Example 16 may include the subject matter of any of examples 9 or 10 or 11 or 12 or 13 or 14 or 15, wherein forming the LMI landing pad comprises depositing the LMI landing pad by electroless deposition.
• Example 17 may include the subject matter of any of examples 9 or 10 or 11 or 12 or 13 or 14 or 15 or 16, wherein processing the portion of the passivation layer comprises etching the portion of the passivation layer.
• Example 18 may include the subject matter of any of examples 9 or 10 or 11 or 12 or 13 or 14 or 15 or 16 or 17, wherein forming the patternable dielectric material layer on the passivation layer comprises covering one or more seams formed in the passivation layer with the patternable dielectric material layer; and wherein processing the portion of the passivation layer covering the redistribution layer comprises maintaining the patternable dielectric material layer covering one or more seams formed in the passivation layer.
• Example 22 may include the subject matter of any of examples 19 or 20 or 21, wherein the dielectric layer comprises a permanent film.

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  • 2015-12-09 WO PCT/US2015/064620 patent/WO2017099736A1/en active Application Filing
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