CN1512579A - 半导体模块 - Google Patents
半导体模块 Download PDFInfo
- Publication number
- CN1512579A CN1512579A CNA2003101243341A CN200310124334A CN1512579A CN 1512579 A CN1512579 A CN 1512579A CN A2003101243341 A CNA2003101243341 A CN A2003101243341A CN 200310124334 A CN200310124334 A CN 200310124334A CN 1512579 A CN1512579 A CN 1512579A
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- Prior art keywords
- semiconductor chip
- module
- semiconductor
- support
- module board
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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Abstract
本发明在其上以层叠方式安装有二个半导体芯片的半导体模块中,实现了上部半导体芯片的下表面接地电极的接地增强和小型化。下部半导体芯片被固定到形成在模块板上表面中的凹陷底部,且上部半导体芯片被固定到由形成在凹陷周围模块板上表面上的导体制成的支持体的上表面。外部电极端子和散热焊点被形成在模块板的下表面上。连接到散热焊点的多个通道被形成在凹陷底部中。支持体被形成在连接到散热焊点的通道上。散热焊点假设为接地电位。诸如芯片电阻器、芯片电容器、以及芯片固定线圈的类芯片电子部件,被安装在模块板的上表面上。半导体芯片被导电金属丝连接到模块板的布线。上部半导体芯片的下表面接地电极经由通道被连接到假设为接地电位的散热焊点。
Description
技术领域
本发明涉及到半导体模块,更确切地说是涉及到能够以垂直层叠的方式安排多个半导体芯片,同时防止它们彼此形成接触,且同时能够增强上部半导体芯片的接地的半导体模块。
背景技术
作为将其中组合有诸如晶体管之类的有源元件的半导体芯片以及其中组合有诸如电阻器、电容器之类的无源元件的芯片部件分别安装在印刷电路板上的半导体模块(半导体器件)的例子,已知有混合模块(例如见专利文献1)。
而且,已知有一种将多个半导体芯片组合在封装件中的产品(例如见专利文献2)。
[专利文献1]
日本未经审查的专利公开2000-58741(p.5和6,图1)
[专利文献2]
日本未经审查的专利公开2001-110986(p.7左列)
大量电子部件被组合到移动通信的终端设备(移动电话等)中。组合到移动电话的传输系统中的高频放大器件(功率放大器模块PA)的急剧小型化和功能复杂化已经在进行中。作为一种通信方法,已知GSM(全球移动通信系统)方法。虽然这种GSM方法的功率放大器模块目前的外形尺寸被设定为纵向10mm和横向8mm,但作为下一代模块的主流,外形尺寸有望会被设定为纵向6mm和横向5mm。
而且,同样在CDMA(码分多址)领域中,虽然功率放大器模块的目前外形尺寸被设定为纵向6mm和横向6mm,但有望会要求纵向5mm和横向5mm的外形尺寸,因此,纵向4mm和横向4mm的外形尺寸相继会被要求。
在这种超小型化的功率放大器模块中,仅仅利用在具有印刷电路板构造的模块板的表面上二维安装各个部件,无法安装包括其中组合有诸如晶体管之类的有源元件的半导体芯片以及由电阻器(芯片电阻器)、电容器(芯片电容器)等组成的无源元件的各个芯片部件,因此,需要三维安装。
另一方面,如日本未经审查的专利公开2001-110986所示,对于平行排列半导体芯片的结构,产品的小型化受到阻碍。而且,在将其它半导体芯片安装在半导体芯片上表面上的叠层安装结构中,存在着难以增强上侧半导体芯片背面上参考电位电极(接地电极)的缺点。
发明内容
因此,本发明的目的是增强半导体模块中上侧半导体芯片下表面接地电极的接地,此半导体模块的构造中以重叠的方式层叠和安装了多个半导体芯片。
本发明的另一目的是将半导体模块小型化成组合有多个半导体芯片和无源部件等。
从本说明书和附图的描述中,本发明的上述目的、其它目的、以及新颖特点将变得明显。
本说明书公开的典型的本发明的概述简要解释如下。
根据本发明的半导体模块包括:
由印刷电路板构成的模块板,它具有用来在其上表面上安装第一半导体芯片(下部半导体芯片)的凹陷,并具有用来在其凹陷周围的上表面上安装第二半导体芯片(上部半导体芯片)的支持体;
第一半导体芯片,它以形成在其主表面上的电极被排列在上侧的状态被固定到凹陷底部上的芯片安装层;
第二半导体芯片,它以形成在其主表面上的电极被排列在上侧的状态被固定到支持体的上表面,此第二半导体芯片大于第一半导体芯片;
导电金属丝,它连接第一半导体芯片的电极和模块板的布线;
导电金属丝,它连接第二半导体芯片的电极和模块板的布线;
电子部件,例如安装在模块板上表面上的电阻器、电容器等;
密封部分,它覆盖模块板的上表面,同时覆盖第一和第二半导体芯片、金属丝、电子部件等,此密封部分具有固定的厚度且由绝缘树脂制成;
外部电极端子,它被提供在模块板的下表面,并由导电层组成;
散热焊点,它被提供在模块板的下表面,并由构成参考电位电极(接地电极)的导电层组成;以及
通道,它包括模块板的凹陷部分,并由导体组成,贯穿在模块板的上表面和下表面之间,其中
支持体由形成在通道上并支持第二半导体芯片的导电球组成,
第二半导体芯片以非接触的状态被重叠到第一半导体芯片的上侧,
第二半导体芯片的下表面被设定为高于连接到第一半导体芯片的金属丝的回路高度,且
形成在凹陷底部上的通道和连接到支持体的通道二者都被连接到散热焊点。
半导体模块包括根据级联连接方法将多个晶体管连接在多个级中的高频功率放大器件、高频功率放大器件的第一级晶体管被包括在第二半导体芯片中,且高频功率放大器件的末级晶体管被包括在第一半导体芯片中。半导体模块被安装在移动电话上。而且,假设模块板的外形尺寸和密封部分的外形尺寸相同。
这种半导体模块能够提供将第二半导体芯片(上部半导体芯片)安置在第一半导体芯片(下部半导体芯片)上的三维安装结构,因此,与将第一和第二半导体芯片平行安装在一个平面上的结构相比,有可能使半导体模块小型化。同时,由于此半导体模块采用了将下部半导体芯片固定到形成在模块板上表面中的凹陷底部的结构,故有可能减小半导体模块的厚度,减小量相当于凹陷的深度。
在这种半导体模块中,下部半导体芯片的下表面经由通道被电连接到模块板下表面的散热焊点,此散热焊点被设定为参考电位(地),同时,上部半导体芯片经由导电球和通道被电连接到散热焊点,因此,增强了上部半导体芯片的接地,更不用说下部半导体芯片了。
这种半导体模块构成了高频功率放大器件,其中,虽然高频功率放大器件的第一级晶体管被组合到上部半导体芯片中,且呈现比第一级晶体管更高的热值的末级晶体管被组合到下部半导体芯片中,但这些晶体管呈现出有利的散热性质,且二种晶体管的接地都被增强,因此,其中组合有此半导体模块的移动电话以稳定的方式工作。
附图说明
图1是根据本发明一个实施方案(实施方案1)的半导体模块的示意剖面图;
图2是实施方案1的半导体模块的平面图;
图3是实施方案1的半导体模块的仰视图;
图4是实施方案1的半导体模块的局部放大剖面图;
图5是处于密封部分被清除状态中的实施方案1的半导体模块的示意平面图;
图6是示意剖面图,示出了实施方案1的半导体模块被安装在安装板上的状态;
图7是示意剖面图,示出了实施方案1的半导体模块制造中的各个步骤;
图8是可应用于实施方案1的半导体模块的高频功率放大器件的电路图;
图9是示意剖面图,示出了构成本发明另一实施方案(实施方案2)的半导体模块;
图10是实施方案2的半导体模块的局部放大剖面图;
图11是处于密封部分被清除的实施方案2的半导体模块的示意平面图;
图12是示意剖面图,示出了本发明另一实施方案(实施方案3)的半导体模块;而
图13是实施方案3的半导体模块的等效电路图。
具体实施方式
结合附图来详细地解释本发明的优选实施方案。此处,在所有用来解释本发明各个实施方案的附图中,具有相同功能的各个部件被赋予相同的符号,其重复的解释从略。
(实施方案1)
图1-7涉及到构成本发明一个实施方案(实施方案1)的半导体模块。图1-5涉及到半导体模块的结构。图1是其剖面图,图2是其平面图,图3是其仰视图,图4是其局部放大剖面图,而图5是其处于密封部分被清除状态的示意平面图。
如图1-3所示,本实施方案1的半导体模块(半导体器件)1包括外形为四边形的模块板2、以重叠方式形成在模块板2的上表面上的密封部分(封装件)3、以及形成在模块板2的下表面上的多个外部电极端子4和散热焊点5。
在半导体模块1的制造中,如稍后所述,包括半导体芯片的各个电子部件被安装在模块基板的上表面上,然后,具有固定高度的树脂密封层被形成在模块基板的上表面上,使树脂密封层覆盖各个电子部件等,随后,沿纵向和横向切割包括重叠到模块基板的树脂密封层的模块基板,于是同时制造了多个半导体模块1。因此,有可能提供模块板2的侧面和密封部分3的侧面彼此对准,且密封部分3的端部不处于模块基板2端部外面的结构。结果,能够制造小型尺寸的半导体模块1。
模块板2由印刷电路板(PCB)构成。PCB采用了这样一种结构,其中,多个介质层(绝缘膜)被彼此层叠且包括由其上下表面上和内部的给定布线图形组成的导电层,且这些上下导电层通过垂直延伸的导体被彼此电连接。在实施方案1中,虽然不受特别的限制,但各个介质层被提供在5个层中。布线22由导电层和导体组成。
外部电极端子4和散热焊点5由形成在模块板2下表面上的导电层组成。金属丝连接焊点23和电极连接焊点24由形成在模块板2上表面上的导电层组成。
外部电极端子4和散热焊点5由形成在模块板2下表面上的导电层组成。金属丝连接焊点23和电极连接焊点24由形成在模块板2上表面上的导电层组成。
而且,在实施方案1中,凹陷10被形成在模块板2的上表面中。而且,垂直贯穿模块板2的通孔被形成在凹陷10的底部中,且导体被同时填充在各个通孔中,从而形成通道8。通道8被连接到散热焊点5。散热焊点5的面积大于外部电极端子4的面积。
而且,通道孔被形成在凹陷周围的模块板2中,且同时,导体被填充在通道孔中,从而形成通道7。通道7的下端也被连接到散热焊点5。
导电层和导体由金属组成。例如,虽然图中未示出,但形成在模块板2上下表面上的导电层由Ti(下层)/TiN层以及形成在Ti(下层)/TiN层上的Ti(下层)/Al-Cu-Si层组成。而且,在其上连接有粘合剂和金属丝的导电层的表面上,为了方便连接,形成了镀层膜9。此镀层膜9例如被形成在金属丝连接焊点23和电极连接焊点24的表面以及通道7的上表面上。此镀层膜9由例如Ti(下层)/Ni制成。
如图3所示,外部电极端子4沿各个边以预定的间距被安置在半导体模块1的四边形底部表面上。然后,其面积比外部电极端子4的面积大得多的散热焊点5,被安置在底部表面的中央部位处。
凹陷(空腔)10被形成在模块板2的上表面大致中央。利用粘合材料17,半导体芯片(第一半导体芯片)15被安装在凹陷10的底部上。形成在凹陷10底部中的通道8用来迅速地将固定到凹陷10底部的半导体芯片15产生的热传输到散热焊点5。当半导体模块1被安装在模块板上时,散热焊点5越大,就越有可能有效地将热传输到安装板侧。
而且,虽然通道7也被形成在凹陷10周围模块板2的上表面部分(比凹陷底部高出一个台阶的表面)中,但由导体制成的支持体12被粘合和固定到通道7。
支持体12被提供在凹陷10周围,使支持体12环绕凹陷10。半导体芯片(第二半导体芯片)16被安装在支持体12上。例如采用了焊料球作为支持体12。镀层膜9被形成在支持体12被连接于其上的通道7的上表面上,以便容易与支持体12粘合。
在本实施方案1中,在半导体芯片15和半导体芯片16的图中未示出的半导体板,被电连接到相应的通道8和7。在本实施方案1中,假设半导体板为第一参考电位,亦即接地电位。因此,散热焊点5也假设为接地电位。
二个半导体芯片15和16以其间给定的距离被彼此垂直地重叠(非接触状态),因此,固定到凹陷10底部的半导体芯片15被称为下部半导体芯片,而固定到支持体12的半导体芯片16被称为上部半导体芯片。下部半导体芯片被安装在凹陷10的底部上,而上部半导体芯片被安装在提供于凹陷10周围的支持体12上,因此,比下部半导体芯片15更大的半导体芯片被用作上部半导体芯片16。
由于下部半导体芯片15被连接到形成于凹陷10底部中的多个通道8,故散热特性是良好的。因此,即使当下部半导体芯片的热值大于上部半导体芯片的热值时,也有可能使下部半导体芯片稳定地工作。在本实施方案1中,上部半导体芯片可以是组合具有热值小的控制系统的有源元件(例如晶体管)的类型,而下部半导体芯片可以是组合具有呈现热值比上部半导体芯片更大的驱动系统的晶体管的类型。
下部半导体芯片和上部半导体芯片二者以图中未示出的电极被形成在上表面上的状态被分别安装。而且,各个芯片的电极和模块板2的给定布线层部分,用导电金属丝18彼此电连接。
上部半导体芯片16下表面的高度被设定为高于连接到下部半导体芯片15的金属丝的回路高度,因此,有可能防止出现连接到下部半导体芯片15的金属丝18与上部半导体芯片16下表面形成接触时可能引起的短路缺陷。因此,实际上有可能将半导体芯片16安排在半导体芯片15上方,同时防止半导体芯片16与半导体芯片15形成接触。
如图4和图5所示,多个电子部件19被安装在模块板2的上表面上。电子部件19是诸如芯片电阻器、芯片电容器、以及芯片固定线圈之类的芯片部件。这些芯片部件分别构成其二端处的电极19a,且各个芯片部件被安装在模块板2上,使电极19a用焊料20与模块板2的布线层电连接。在实施方案1中,含铅量小的焊料(以下称为“无铅焊料”)被用作焊料20。在Sn、Ag、或Cu中含有Zn或Bi的焊料被用作无铅焊料。在图5中略去了焊料20。
此处,借助于选择形成在模块板2上表面上的布线层的图形,也有可能安装其中组合有有源元件的电子部件亦即半导体芯片或树脂封装的小型化晶体管等。
覆盖半导体芯片15和16、金属丝18、电子部件19等的密封部分3,被形成在模块板2的上表面上。密封部分3由绝缘树脂制成。例如,密封部分3由杨氏模量为1-200Mpa且热膨胀系数α为180×10-6-200×10-6/℃的硅酮树脂或杨氏模量为1000-10000Mpa的环氧树脂制成。利用这种密封部分3,有可能具有在相关侧处进行安装时的回流中,能够防止焊料在封装件内部的膨胀引起的焊料溢出的有利效果。亦即,当借助于执行采用诸如焊料之类的键合材料的回流而将半导体模块1安装在安装板上时,组合到半导体模块1密封部分3中的电子部件的键合部分处的焊料由于回流产生的热而膨胀,焊料从而通过模块板2与密封部分3之间的界面泄露到外面的现象(焊料溢出现象)容易发生。由于模块板2的热膨胀系数α约为7×10-6/℃,故借助于用具有上述杨氏模量和热膨胀系数的树脂来形成密封部分3,能够增强模块板2与密封部分3之间的粘合强度,从而能够抑制焊料溢出现象的产生。
基于硅单晶板来制作半导体芯片15和16,例如,其中用通常使用的外延生长或成为施主或受主的杂质的选择和扩散方法,在给定位置处制作一个或多个诸如由晶体管构成的有源元件之类的电子元件。当有需要时,各个电子元件的电极用金属丝连接,且给定的电极被引出半导体芯片的上表面作为电极端子。而且,半导体芯片15和16可以是构成诸如由化合物半导体制成的晶体管之类的有源元件的芯片。
例如,半导体模块1被构造成包括制作在其下表面上的外部电极端子4和散热焊点5的模块板2的厚度为0.75mm,而密封部分3的厚度为0.9mm。虽然半导体模块1采用了将半导体芯片层叠在二层中的结构,但有可能减小半导体模块1的厚度。
这种半导体模块1以图6所示的半导体模块1被安装在由PCB板构成的安装板30上的形式被采用。安装板30包括其上下表面上和内部的给定图形的布线层31,同时,这些布线层31通过填充在通道孔中的导体34被彼此电连接。安装板30中的布线层31由多个层组成。对于形成在安装板30的上下表面上的布线层,图中未示出的用来增强连接性质的镀层膜,被形成在其连接有电极的部位上。此镀层膜由例如Ni层(下层)/无铅焊料组成。而且,散热焊点35对应于半导体模块1的散热焊点5被制作在安装板30的上表面上。
如图6所示,借助于将制作在下表面上的外部电极端子4和散热焊点5重叠到制作在安装板30的上表面上的布线层31和散热焊点35,然后对预先形成在布线层31和散热焊点35上的焊料36进行回流,来安装半导体模块1。
接着,参照图7(a)-7(f)来解释本实施方案1的半导体模块1的制造方法。用下列步骤来制造半导体模块1:制备模块基板,将类芯片电子部件安装在模块基板的上表面上,将下部半导体芯片(第一半导体芯片)安装在凹陷底部上,在第一半导体芯片中进行金属丝键合,将支持体固定到凹陷周围的通道,将上部半导体芯片(第二半导体芯片)安装到支持体的上表面,在第二半导体芯片中进行金属丝键合,在模块板的上表面上形成树脂密封层,以及切割和分离模块基板。
如图7(a)所示,首先制备模块基板2a。模块基板2a由四边形PCB构成,将产品制作部分f沿纵向和横向排列在矩阵中(n行和m列矩阵安排)。在图7(a)中,由f确定的尺寸区域是产品制作部分。在图7(b)中,产品制作部分f的放大图被示为剖面图。产品制作部分f的结构是已经被解释为半导体模块1的模块板2的结构部分。产品制作部分f被构造成使凹陷10被形成在上表面的大致中央处,通道8和7被形成在凹陷10的底部和凹陷10周围模块板2的上表面中,布线层被形成在模块板2的上表面上,以及外部电极端子4和散热焊点5被形成在下表面上。
接着,如图7(c)所示,类芯片电子部件19被制作在模块板2的上表面上。虽然已经结合图4解释了安装结构,但提供在类芯片电子部件19二端处的电极19a被置于模块板2上表面上的电极连接焊点24上,预先用印刷等方法形成在电极连接焊点24上的焊料20由于加热(回流)而被暂时熔化,以便将电极19a固定到电极连接焊点24(见图4)。待要安装的类芯片电子部件19是例如诸如芯片电阻器、芯片电容器、芯片固定线圈之类的无源部件。
接着如图7(d)所示,由焊料球制成的支持体12被粘合在形成在凹陷10周围模块板2上的通道7上。而且,利用粘合材料17,半导体芯片15(第一半导体芯片,即下部半导体芯片)被安装在凹陷10的底部上。然后,用导电金属丝18,图中未示出的半导体芯片15的电极和形成在模块板2的上表面上的给定金属丝连接焊点23被彼此电连接。
接着,如图7(e)所示,用给定的粘合材料(从图中略去了),半导体芯片16(第二半导体芯片,即上部半导体芯片)被安装在排列于凹陷10周围模块板2的上表面上的支持体12上。而且,用导电金属丝18,图中未示出的上部半导体芯片16的电极和形成在模块板2的上表面上的给定金属丝连接焊点23被彼此电连接。
接着,如图7(f)所示,例如用转移注模方法,具有给定高度的树脂密封层3a被形成在模块基板2a的上表面上,以便覆盖安装在模块基板2a的上表面侧上的半导体芯片15和16、金属丝18、以及电子部件19。
接着,模块基板2a与重叠到模块基板2a的树脂密封层3a一起沿纵向和横向被切割和分离,以便制造图1-3所示的多个半导体模块1。由于这种切割,模块基板2a被形成为模块板2,且树脂密封层3a被形成为密封部分3。
图8是可应用于本实施方案1的半导体模块的高频功率放大器件的例子。此高频功率放大器件具有图8所示的电路构造。此高频功率放大器件被构造成放大二种通信系统,其中,放大各个通信系统的放大系统采用了基于三级级联连接的三级晶体管连接构造。
亦即,一种通信系统被构造成使起始级晶体管Q1、下一级晶体管Q2、以及彼此并联连接的末级晶体管(输出级放大器)Q3和Q4,被顺序连接在输入端子Pin1与输出端子Pout1之间。电源电压Vdd1被施加到各个晶体管的漏电极,且各个晶体管的栅电极被从控制端子Vapc输入的电压偏置。
而且,另一通信系统被构造成使起始级晶体管Q5、下一级晶体管Q6、以及并联连接的末级晶体管(输出级放大器)Q7和Q8,被顺序连接在输入端子Pin2与输出端子Pout2之间。电源电压Vdd2被施加到各个晶体管的漏电极,且各个晶体管的栅电极响应于从控制端子Vapc输入的控制电压被偏置。
控制端子Vapc被连接到开关SW1,其中,开关SW1响应于来自转换端子Vctl的转换信号而转换,且控制端子Vapc的控制电压被形成来执行开关SW1规定的通信系统的放大。
晶体管Q1、Q2、Q5、Q6以单片方式被制作在第一半导体芯片(芯片1)上,而输出级晶体管Q3、Q4、Q7、Q8以单片方式被制作在单个半导体芯片(芯片2)上。
在二种通信系统中,C所示的大量电容性元件(CP、CG、CB)、R所示的大量电阻元件(RP、RG)、以及L所示的大量固定线圈,被组合到二种通信系统中,从而构成匹配电路和偏置电路。
例如,在这样一种构造中,一种通信系统采用DCS(数字蜂窝系统1800)方法,它将频带设定为1710-1785MHz,而另一种通信系统采用GSM(全球移动通信系统)方法,它将频带设定为880-915MHz。
在实施方案1的构造中,其中组合大热值的输出级晶体管的芯片2被固定到凹陷10的底部,而其中组合呈现比输出级晶体管小得多的热值的起始级和下一级晶体管的芯片1,被安装在支持体12的上表面上。
利用实施方案1,能够得到下列有利效果。
(1)由于半导体模块1采用了三维安装结构,将第二半导体芯片(上部半导体芯片)16安置在第一半导体芯片(下部半导体芯片)15的上方,故与将第一和第二半导体芯片平行地安置在同一个平面上的结构相比,半导体模块1能够被小型化。
(2)由于半导体模块1采用了下部半导体芯片15被固定到形成于模块板2的上表面中的凹陷10的底部,故能够减小半导体模块的厚度,减小的量相当于凹陷的深度。
(3)下部半导体芯片15的下表面经由通道8与模块板2下表面的假设为参考电位(地)的散热焊点5电连接,而上部半导体芯片16经由焊料球组成的支持体12和通孔7与散热焊点5电连接,因此,也增强了上部半导体芯片16的接地,更不用说下部半导体芯片15了。
(4)关于从通道8到散热焊点5的路径的热阻以及从支持体12经由通孔7到散热焊点5的路径的热阻,由于支持体12、通道7和8由热阻小的导体(金属)制成,故上下半导体芯片15和16产生的热能够被迅速地传输到散热焊点5。亦即,当用诸如焊料的热阻小的键合材料(焊料36)将半导体模块1的散热焊点5粘合到安装板30的散热焊点35时,上下半导体芯片15和16产生的热能够被迅速地辐射到安装板30,从而保持半导体模块1的稳定工作。
例如,当移动电话的高频功率放大器件由本发明的半导体模块1构成时,在具有多级构造的放大阶段中,组成末级(输出级)晶体管的产生大热值的半导体芯片15和组成起始级晶体管和控制用晶体管的呈现小热值的半导体芯片16,被安装在支持体12的上表面上,因此,有可能提供被小型化的且呈现有利散热性质的高频功率放大器件。结果,其中组合有此半导体模块1的移动电话也稳定地工作。
(实施方案2)
图9-11涉及到根据本发明另一实施方案(实施方案2)的半导体模块。图9是示意剖面图,示出了半导体模块,图10是半导体模块的局部放大剖面图,而图11是处于密封部分被清除状态的半导体模块的示意平面图。
实施方案2的半导体模块1的特征在于,在实施方案1的半导体模块1中,支持上部半导体芯片16的支持体12和模块板2被整体制作。亦即,虽然在实施方案1中支持体12与模块板2分别制作,但在实施方案2中,支持体12在制造模块板2同时被制作。
虽然在实施方案1的半导体模块1中,介质层由5层组成,但在本实施方案2中,介质层由6层组成,且如图11所示,最上面的介质层由突起在四边形图形中的支持体12组成,并被排列在能够支持上部半导体芯片16的位置处。而且,垂直贯穿模块板2的通孔被制作在各个支持体12中,且导体被填充在各个通孔中,从而形成通道7。这些通道7还被连接到形成在模块板2的下表面上的散热焊点5。镀层膜9被形成在贯穿支持体12中央的通道7的上表面上,且利用粘合材料,半导体芯片16的下表面被电连接到镀层膜9部分。
本实施方案2的半导体模块1也呈现出与用实施方案1得到的有利效果基本上相同的有利效果。
图12是示意剖面图,示出了构成本发明另一实施方案(实施方案3)的半导体模块,而图13是半导体模块的等效电路图。
如图12所示,实施方案3的半导体模块1基本上具有与实施方案1相同的结构。但本实施方案不同于实施方案1的是有关安装在凹陷10底部上的半导体芯片15和组合到安装在支持体12上的半导体芯片16中的晶体管。图13对应于用来解释实施方案1的图8。
如图13所示,一种通信系统被构造成使起始级晶体管Q1、下一级晶体管Q2、以及末级(输出级)晶体管Q3和Q4,被顺序连接在输入端子Pin1与输出端子Pout1之间。而另一种通信系统被构造成使起始级晶体管Q5、下一级晶体管Q6、以及并联连接的末级晶体管(输出级放大器)Q7和Q8,被顺序连接在输入端子Pin2与输出端子Pout2之间。
在实施方案1的半导体模块1中,安装在凹陷10底部上的下部半导体芯片15将末级(输出级)晶体管Q3、Q4、Q7、Q8组合在其中,而安装在支持体12的上表面上的半导体芯片16将控制用IC、起始级晶体管Q1和Q5、以及下一级晶体管Q2和Q6组合在其中。
相反,在本实施方案3的半导体模块1中,安装在凹陷10底部上的半导体芯片15将控制用IC和起始级晶体管Q1和Q5组合在其中,而安装在支持体12的上表面上的半导体芯片16将下一级晶体管Q2和Q6以及末级(输出级)晶体管Q3、Q4、Q7、Q8组合在其中。
但由于电路尺寸不同,亦即,当末级(输出级)晶体管的热值不大时,有可能将末级(输出级)晶体管Q3、Q4、Q7、Q8组合到上部半导体芯片16中,而将控制用IC和起始级晶体管Q1和Q5组合到下部半导体芯片15中。但倘若由于热辐射效应将上部半导体芯片16产生的热经由支持体12和通道7传输到散热焊点5而能够实现这一点,则上部半导体芯片16能够稳定地有效工作。
虽然基于各个实施方案已经具体解释了本发明人提出的本发明,但不言自明,本发明不局限于上述各个实施方案,而是能够作出各种修正而不偏离本发明的主旨。虽然MOSFET(金属氧化物半导体场效应晶体管)被用作实施方案1中的放大元件(晶体管),但放大元件也可以由包含其它的硅或化合物半导体的双极基晶体管组成。
用本说明书中公开的本发明中的典型发明得到的有利效果简要地解释如下。
(1)借助于以垂直重叠的方式安置多个半导体芯片中的至少二个半导体芯片,提高了封装密度,半导体模块从而能够被小型化。
(2)半导体模块采用了这样一种结构,其中,凹陷被形成在模块板的上表面中,下部半导体芯片被安装在凹陷的底部上,而上部半导体芯片以分隔开的方式被安装在下部半导体芯片上方的支持体的上表面上,因此,能够减小半导体模块的厚度。
(3)借助于将具有大热值的半导体芯片安装在形成多个通道的凹陷底部上,能够提高通过通道的散热性质。而且,上部半导体芯片能够提高通过支持体或导体形成的通道的散热性质,能够实现半导体模块的稳定工作。
(4)利用支持体和通道,上部半导体芯片的下表面部分被电连接到形成在模块板下表面上的由导体组成的散热焊点。因此,能够增强安装在上部半导体芯片下表面上的接地电极的接地。而且,下部半导体芯片通过通道也被电连接到散热焊点,因此,能够增强安装在下部半导体芯片下表面上的接地电极的接地。结果,能够实现半导体模块的稳定工作。
(5)如上述有利效果(3)和(4)所述,此半导体模块能够提高散热性质,并能够增强接地,因此,将此半导体模块应用于移动电话的高频功率放大器件,有可能稳定地运行其中组合有此半导体模块的移动电话。
(6)由于多个半导体芯片、无源部件等能够以高集成度组合到模块板中,故半导体模块能够被小型化。
Claims (30)
1.一种半导体模块,它包含:
模块板,其上表面上具有支持体,且其下表面上具有外部电极端子;
第一半导体芯片,它以形成在主表面上的电极被形成于半导体芯片上侧上的状态被固定到模块板;
第二半导体芯片,其一部分平面重叠到第一半导体芯片上方,使第二半导体芯片不与第一半导体芯片形成接触,第二半导体芯片被支持体支持且固定到支持体;以及
导电金属丝,它对第一半导体芯片和模块板进行电连接。
2.根据权利要求1的半导体模块,其中,部分支持体由导体制成。
3.根据权利要求2的半导体模块,其中,由导体形成并贯穿在模块板上下表面之间的通道被形成在模块板中,且由导体形成的支持体被连接到通道。
4.根据权利要求1的半导体模块,其中,支持体处于参考电位。
5.根据权利要求2的半导体模块,其中,第一半导体芯片和第二半导体芯片通过支持体彼此电连接。
6.根据权利要求1的半导体模块,其中,支持体由与模块板一起同时形成的突起组成。
7.根据权利要求6的半导体模块,其中,由导体形成并贯穿在模块板上下表面之间的通道被形成在支持体内部。
8.根据权利要求1的半导体模块,其中,支持体构成相对于模块板分离的部分,并被固定到模块板。
9.根据权利要求8的半导体模块,其中,支持体由球组成。
10.根据权利要求9的半导体模块,其中,支持体由导体形成并与由导体组成的贯穿在模块板上下表面之间的通道电连接。
11.根据权利要求1的半导体模块,其中,由导体形成并贯穿在模块板上下表面之间的通道被形成在模块板中,由导电层组成的散热焊点被形成在模块板的下表面上,且通道被连接到散热焊点。
12.根据权利要求1的半导体模块,其中,第二半导体芯片的一边长于第一半导体芯片的一边。
13.根据权利要求1的半导体模块,其中,第一半导体芯片的热值大于第二半导体芯片的热值。
14.根据权利要求1的半导体模块,其中,由导体形成并贯穿在模块板上下表面之间的通道被形成在模块板中,且第一半导体芯片被连接到通道。
15.根据权利要求1的半导体模块,其中,第一半导体芯片和第二半导体芯片被连接到公共参考电位电极。
16.根据权利要求1的半导体模块,其中,凹陷被形成在模块板的上表面中,且第一半导体芯片被固定到凹陷的底部。
17.根据权利要求16的半导体模块,其中,由导体形成并贯穿在模块板上下表面之间的通道被形成在凹陷的底部中,由导电层组成的散热焊点被形成在模块板的下表面上方,且通道被连接到散热焊点。
18.根据权利要求1的半导体模块,其中,参考电位电极被形成在第二半导体芯片的下表面上。
19.根据权利要求1的半导体模块,其中,参考电位电极被形成在第一半导体芯片的下表面上。
20.根据权利要求1的半导体模块,其中,形成在第二半导体芯片上表面上的电极和形成在模块板上的布线,被导电金属丝彼此电连接。
21.根据权利要求1的半导体模块,其中,支持体的上表面被设定为高于连接到第一半导体芯片的金属丝的回路高度。
22.根据权利要求1的半导体模块,其中,凹陷被形成在模块板的上表面中,支持体被形成在凹陷周围的模块板上表面上,第一半导体芯片被固定到凹陷的底部,第二半导体芯片被固定到支持体,且支持体的上表面被设定为高于连接到第一半导体芯片的金属丝的回路高度。
23.根据权利要求1的半导体模块,其中,有源元件被分别制作在第一半导体芯片和第二半导体芯片上,且第一半导体芯片的有源元件和包括在第二半导体芯片中的另一个有源元件,基于第二半导体芯片的有源元件被控制。
24.根据权利要求23的半导体模块,其中,半导体模块包括其上基于多级的级联连接方法连接有多个晶体管的功率放大器件,且功率放大器件的第一级晶体管被包括在第二半导体芯片中,而功率放大器件的末级晶体管被包括在第一半导体芯片中。
25.一种半导体模块,其中,根据权利要求24的半导体模块是安装在移动电话上的半导体模块。
26.根据权利要求1的半导体模块,还包含无源部件。
27.根据权利要求1的半导体模块,其中,用由具有绝缘性质的树脂制成的密封部分来覆盖第一和第二半导体芯片、支持体、金属丝、以及各个电子部件。
28.根据权利要求27的半导体模块,其中,密封部分的端部不位于模块板端部的外面。
29.根据权利要求27的半导体模块,其中,形成密封部分的树脂是杨氏模量为1-200Mpa且热膨胀系数α为180×10-6-200×10-6/℃的硅酮树脂或杨氏模量为1000-10000Mpa的环氧树脂。
30.一种半导体模块,它包含:
模块板,其上表面上具有由导体制成的支持体,且其下表面上具有外部电极端子;
第一半导体芯片,它以形成在主表面上的电极被形成于第一半导体芯片上侧上的状态被固定到模块板;
第二半导体芯片,它被重叠到第一半导体芯片上方,其间有间隙,并被固定到支持体;
导电金属丝,它将第一半导体芯片和第二半导体芯片电连接到模块板;以及
电连接到模块板的电子部件,其中
晶体管被分别提供到第一半导体芯片和第二半导体芯片,高频功率放大器件用晶体管的多级级联连接方法来构成,高频功率放大器件的第一级晶体管被包括在第二半导体芯片中,且高频功率放大器件的末级晶体管被包括在第一半导体芯片中,且
其中,参考电位层被形成在第二半导体芯片的下表面上,且支持体被连接到参考电位层。
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Also Published As
Publication number | Publication date |
---|---|
TW200428639A (en) | 2004-12-16 |
US7301781B2 (en) | 2007-11-27 |
JP2004214249A (ja) | 2004-07-29 |
US20070035004A1 (en) | 2007-02-15 |
US7154760B2 (en) | 2006-12-26 |
US20040125578A1 (en) | 2004-07-01 |
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