CN1512578A - 半导体模块 - Google Patents
半导体模块 Download PDFInfo
- Publication number
- CN1512578A CN1512578A CNA2003101243271A CN200310124327A CN1512578A CN 1512578 A CN1512578 A CN 1512578A CN A2003101243271 A CNA2003101243271 A CN A2003101243271A CN 200310124327 A CN200310124327 A CN 200310124327A CN 1512578 A CN1512578 A CN 1512578A
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- semiconductor chip
- module
- semiconductor
- passive devices
- integrated passive
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Abstract
本发明实现了半导体模块的小型化。此半导体模块包括下表面上具有外部电极端子和散热焊点的模块板、其中组合高频功率放大器件的起始级晶体管的第一半导体芯片、其中组合下一级晶体管和末级晶体管的第二半导体芯片、以及构成匹配电路的集成无源器件。第一半导体芯片和第二半导体芯片中的至少一个以及集成无源器件,以重叠的方式被安装在模块板的上表面上。第二半导体芯片被安装在形成于模块板上表面中的凹陷底部上。连接到散热焊点的多个通道被形成在凹陷底部中。诸如第一半导体芯片、电阻器、电容器之类的分立部件,被安装在凹陷外面的模块板的上表面上。用形成在模块板上表面上的密封部分,将各个半导体芯片和各个部件密封。
Description
技术领域
本发明涉及到半导体模块,更确切地说是涉及到能够获得其小型化的半导体模块。
背景技术
作为将其中组合有诸如晶体管之类的有源元件的半导体芯片以及其中组合有诸如电阻器、电容器之类的无源元件的芯片部件分别安装在印刷电路板上的半导体模块(半导体器件)的例子,已知有混合集成电路器件。
混合集成电路器件构成例如组合在移动电话中的高频功率放大器件(高频功率模块,例如见专利文献1)。
而且,已知有一种制造具有电容器的小型IC(集成电路器件)的技术(例如见专利文献2)。
[专利文献1]
日本未经审查的专利公开No.Hei 9(1997)-116091(p.5-7,图1,图3)
[专利文献2]
日本未经审查的专利公开No.Hei 9(1997)-232504(p.2,图5)
大量电子部件被组合到移动通信的终端设备(移动电话等)中。组合在移动电话的传输系统中的高频放大器器件(功率放大器模块PA)的急剧小型化和复杂化已经在进行中。作为一种通信方法,已知GSM(全球移动通信系统)方法。虽然这种GSM方法的功率放大器模块目前的外形尺寸被设定为纵向10mm和横向8mm,但作为下一代模块的主流,外形尺寸有望会被设定为纵向6mm和横向5mm。
而且,同样在CDMA(码分多址)领域中,虽然功率放大器模块的外形尺寸目前被设定为纵向6mm和横向6mm,但外形尺寸有望会变得更小,成为纵向5mm和横向5mm,因此,纵向4mm和横向4mm的外形尺寸随后将会被要求。而且,对GSM产品也有这种要求。
在这种超小型化的功率放大器模块中,仅仅利用在具有印刷电路板构造的模块板的表面上二维安装各个部件,无法安装包括其中组合有诸如晶体管之类的有源元件的半导体芯片、电阻器(芯片电阻器)、电容器(芯片电容器)之类的各个芯片部件,因此,需要三维安装。
发明内容
因此,本发明的目的是获得半导体模块的小型化,此半导体模块中组合有多个半导体芯片和多个电子部件。
从本说明书和附图中,本发明的上述目的、其它目的、以及新颖特点将变得明显。
本说明书公开的典型的本发明的概述简要解释如下。
(1)本发明的半导体模块包括:模块板,其上表面上具有布线而其下表面上具有外部电极端子;包括有源元件的第一半导体芯片和第二半导体芯片;以及借助于集成多个无源元件而形成的集成无源器件,其中,至少第一半导体芯片和第二半导体芯片之一以及集成的无源器件,以重叠的方式被安装在模块板的上表面上。在模块板的上表面上形成凹陷,而由导体制成的散热焊点被形成在模块板的下表面上。垂直贯穿模块板的多个通道被形成在凹陷的底部,且这些通道被连接到散热焊点。第二半导体芯片被安装在凹陷的底部上。诸如第一半导体芯片、电阻器、电容器之类的电子部件(无源部件)被安装在凹陷外面的模块板上表面上。集成的无源器件被安装在第一半导体芯片的上表面上。形成在第一和第二半导体芯片上表面上的各个电极以及形成在模块板上表面上的集成无源器件和布线,被导电金属丝彼此电连接。这些第一和第二半导体芯片、集成无源器件、金属丝等,被形成在模块板上表面上的密封部分覆盖。密封部分和模块板具有相同的尺寸,且彼此以对准的方式重叠。第一半导体芯片和第二半导体芯片包括放大电路,同时,第一半导体芯片的输出被输入到第二半导体芯片,从而构成高频功率放大器件。被连接到第一半导体芯片的放大电路的输入匹配电路以及被连接在第一和第二半导体芯片的放大电路之间的级间匹配电路,被组合到集成的无源器件中。
(2)在上述的构造(1)中,输出匹配电路被连接到第二半导体芯片的放大电路的输出部分,且输出匹配电路被组合到安装在模块板上表面上的集成无源器件中。
用本说明书中公开的本发明中的典型发明得到的有利效果简要地解释如下。
(1)由于半导体模块采用了三维安装结构将集成无源器件和其它半导体芯片安装在安装于模块板上表面上的半导体芯片的上表面上,故有可能得到半导体模块的小型化和功能的复杂化。
(2)由于借助于集成多个无源元件而制作集成无源器件,故与将各个分立部件安装在模块板上的结构相比,半导体模块能够被小型化。而且,由于集成无源器件能够被安装在模块板上,使集成无源器件被重叠到半导体芯片,故有可能获得半导体模块的进一步小型化。
(3)由于半导体模块采用了产生大的热值的半导体芯片被固定到形成于模块板上表面上的凹陷的底部上的结构,故有可能经由通道迅速地将热传送到形成在模块板下表面上的散热焊点,因此有可能提供散热性能高的半导体模块。
附图说明
图1是根据本发明一个实施方案(实施方案1)的半导体模块的示意剖面图;
图2是半导体模块的平面图;
图3是半导体模块的仰视图;
图4是半导体模块的示意放大剖面图;
图5是示意平面图,示出了半导体模块中各个电子部件的安置状态;
图6是示意平面图,示出了组合在半导体模块中的集成无源部件的电路构造;
图7是示意剖面图,示出了一些集成无源部件;
图8是半导体模块的等效电路图;
图9是构成实施方案1的第一变形例的半导体模块的示意剖面图;
图10是构成实施方案1的第二变形例的半导体模块的示意剖面图;
图11是构成实施方案1的第三变形例的半导体模块的简化示意剖面图;
图12是简化示意剖面图,示出了根据本发明另一实施方案(实施方案2)的半导体模块;
图13是实施方案2的半导体模块的等效电路图;
图14是组合到实施方案2的半导体模块中的集成无源部件的剖面图;
图15是简化示意剖面图,示出了构成实施方案2的第一变形例的半导体模块;
图16是简化示意剖面图,示出了构成实施方案2的第二变形例的半导体模块;
图17是根据本发明另一实施方案(实施方案3)的半导体模块的简化示意剖面图;
图18是根据本发明另一实施方案(实施方案4)的半导体模块的简化示意剖面图;
图19是简化示意剖面图,示出了构成实施方案4的变形例的半导体模块;
图20是根据本发明另一实施方案(实施方案5)的半导体模块的简化示意剖面图;而
图21是根据本发明另一实施方案(实施方案6)的半导体模块的简化示意剖面图。
具体实施方式
结合附图来详细地解释本发明的优选实施方案。此处在所有用来解释本发明各个实施方案的附图中,具有相同功能的各个部件被赋予相同的符号,其重复的解释从略。
(实施方案1)
图1-8涉及到构成本发明一个实施方案(实施方案1)的半导体模块。图1-7涉及到半导体模块的结构。图1是半导体模块的示意剖面图,图2是其平面图,图3是其仰视图,图4是其示意放大剖面图,而图5示出了模块板上各个电子部件的布局。在图1中,在解释各个部件的符号中,示出了某些部件,同时在图4中示出了各个部件的细节。
本实施方案1的半导体模块(半导体器件)1包括外形为四边形的模块板2、以重叠方式形成在模块板2上表面上的密封部分(封装件)3、以及形成在模块板2下表面上的多个外部电极端子4和散热焊点5。
在半导体模块1的制造中,包括半导体芯片的各个电子部件被安装在模块板的上表面上,然后,具有固定高度的树脂密封层被形成在模块板的上表面上,使树脂密封层覆盖各个电子部件,随后,沿纵向和横向切割包括重叠到模块板的树脂密封层的模块板,于是同时制造了多个半导体模块1,从而有可能提供模块板2和密封部分3具有相同尺寸且彼此对准重叠的结构。因此,有可能提供模块板2的侧面和密封部分3的侧面彼此对准,且密封部分3的端部不处于模块板2端部外面的结构。利用这种制造方法,能够制造小型尺寸的半导体模块1。此处,由于上述的切割操作,模块板被制作成各个模块板,且密封层被形成为各个密封部分。
模块板2由印刷电路板(PCB)构成,其中,如图1所示,模块板2包括其上下表面和内部具有给定布线图形的导电层(未示出),且这些导电层经由填充在通孔(未示出)中的导体被彼此电连接。在模块板2的结构中,多个导电层(布线)被插入在多个介质层(绝缘膜)之间。在实施方案1中,虽然不受特别的限制,但各个介质层被提供在六层中。
布线9由形成在模块板2上下表面和内部上的导电层以及垂直延伸的导体组成。外部电极端子4和散热焊点5由形成在模块板2下表面上的导电层组成。芯片安装焊点6、电极连接焊点7、布线连接焊点8等,由形成在模块板2上表面上的导电层组成。
而且,在实施方案1中,凹陷10被形成在模块板2的上表面中。而且,垂直贯穿模块板的通孔被形成在凹陷10的底部处,且导体被同时填充在各个通孔中,从而形成通道11。而且,芯片安装焊点12也被形成在凹陷10的底部上。形成在凹陷10底部上的芯片安装焊点12和散热焊点5,经由多个通道11被彼此连接。散热焊点5的面积大于外部电极端子4的面积。
导电层和导体由金属组成。例如,虽然未示出,但形成在模块板2上下表面上的导电层由Ti(下层)/TiN层以及形成在Ti(下层)/TiN层上的Ti(下层)/Al-Cu-Si层组成。而且,在其上连接有粘合剂和布线的导电层的表面上,为了方便连接,形成了例如由Ti(下层)/Ni制成的镀层膜。而且,内部导电层由银导体组成,而填充在通孔或通道孔中的导体是银导体。
在本实施方案1中,用粘合剂16将第一半导体芯片15固定到芯片安装焊点6的上表面。在第一半导体芯片15中,虽然其结构未示出,但构成有源元件的多个放大电路被制作在硅衬底的上表面侧上,且预定数目的电极17被安置在覆盖硅衬底上表面的绝缘层上,致使预定数目的电极17被暴露。电极17沿四边形的第一半导体芯片15的各个边制作。形成在第一半导体芯片15周围模块板2上的第一半导体芯片15的电极17和布线连接焊点8,用导电金属丝18电连接。
而且,用粘合剂20将集成的无源器件21固定到第一半导体芯片15的中央。预定数目的电极22也被制作在集成无源器件21的上表面上。集成无源器件21的电极22和形成在集成无源器件21周围模块板2上的布线连接焊点8,用导电金属丝23彼此电连接。
用粘合剂26,第二半导体芯片25被固定到形成在凹陷10底部上的芯片安装焊点12。在第二半导体芯片25中,虽然其结构在图中未示出,但构成有源元件的多个放大电路被制作在硅衬底的上表面侧上,且预定数目的电极27被安置在覆盖硅衬底上表面的绝缘层上,致使预定数目的电极27被暴露。第二半导体芯片25的电极27和形成在凹陷10外围的布线连接焊点8,用导电金属丝28彼此电连接。而且,本实施方案采用了其中形成在凹陷10底部上的芯片安装焊点12和散热焊点5经由通道11彼此被电连接的结构。由于通道11由金属组成,故通道11表现出有利的导热性。因此,第二半导体芯片25产生的热被迅速地传输到散热焊点5。
在本实施方案1中,第二半导体芯片25的半导体衬底(未示出)被构造成使半导体衬底经由导电粘合剂26、芯片安装焊点12、以及通道11而与散热焊点5电连接。因此,借助于将第二半导体芯片25的半导体衬底设定为第一参考电位亦即接地电位,散热焊点5也被设定为接地电位。
预定数目的类芯片电子部件30被安装在模块板2的上表面上。类芯片电子部件30在其二端处构成电极31,且这些电极31部分用粘合剂32被电连接和固定到形成在模块板2上表面上的电极连接焊点7。类芯片电子部件30可以包括例如芯片电阻器、芯片电容器、以及芯片电感器。含铅量小的焊料(以下称为“无铅焊料”)被用作粘合剂32。在Sn、Ag、Cu中含有Zn或Bi的焊料被用作无铅焊料。
如图3所示,外部电极端子4沿半导体模块1的四边形底部表面各个边以预定的间距被安置。而且,具有比外部电极端子4大得多的面积的散热焊点5,被安置在底部表面的中央部位上。
覆盖第一半导体芯片15的密封部分3、第二半导体芯片25、集成无源器件21、类芯片电子部件30、布线18、23、28等,被形成在模块板2的上表面上。密封部分3由绝缘树脂制成。例如,密封部分3由杨氏模量为1-200Mpa且热膨胀系数α为180×10-6-200×10-6/℃的硅酮树脂或杨氏模量为1000-10000Mpa的环氧树脂制成。利用这种密封部分3,有可能具有在相关侧处进行安装时的回流中,能够防止焊料在封装件内部的膨胀引起的焊料溢出的有利效果。亦即,当借助于执行采用诸如焊料之类的键合材料的回流而将半导体模块1安装在安装衬底上时,组合在半导体模块1密封部分3内部的电子部件的键合部分处的焊料由于回流产生的热而膨胀,焊料从而通过模块板2与密封部分3之间的界面泄露到外面的现象(焊料溢出现象)容易发生。由于模块板2的热膨胀系数α约为7×10-6/℃,故借助于用具有上述杨氏模量和热膨胀系数的树脂来形成密封部分3,能够增强模块板2与密封部分3之间的粘合强度,从而能够抑制焊料溢出现象的产生。
本实施方案1的半导体模块1构成了高频功率放大器件。图8示出了此高频功率放大器件的电路构造。此高频功率放大器件采用放大二种通信系统的构造,其中,放大各个通信系统的放大系统采用相继将晶体管连接在3个级中的3级构造。例如,一种通信系统采用DCS(数字蜂窝系统1800)方法,其中的频带为1710-1785MHz,而另一种通信系统采用GSM(全球移动通信系统)方法,其中的频带为880-915MHz。
如图8所示,一种通信系统被构造成使起始级晶体管(起始级放大器即第一放大级)Q1、下一级晶体管(下一级放大器即第二放大级)Q2、以及彼此并联连接的末级晶体管(输出级放大器)Q3和Q4,被顺序连接在输入端子Pin1与输出端子Pout1之间。电源电压Vdd1被连接到各个晶体管的漏电极,且各个晶体管的栅电极被从控制端子Vapc输入的电压偏置。
而且,另一通信系统被构造成使起始级晶体管Q5、下一级晶体管Q6、以及并联连接的末级晶体管(输出级放大器)Q7和Q8,被顺序连接在输入端子Pin2与输出端子Pout2之间。电源电压Vdd2被施加到各个晶体管的漏电极,且各个晶体管的栅电极被从控制端子Vapc输入的控制电压偏置。
控制端子Vapc被连接到开关SW1,其中,开关SW1响应于来自转换端子Vctl的转换信号而转换,且控制端子Vapc的控制电压被形成来执行开关SW1规定的通信系统的放大。
晶体管Q1、Q2、Q5、Q6以单片方式被制作在第一半导体芯片15上,且输出级晶体管Q3、Q4、Q7、Q8以单片方式被制作在第二半导体芯片25上。
在二种通信系统中,C所示的大量电容器元件(CP、CG、CB)、R所示的大量电阻器元件(RP、RG)、以及L所示的大量电感器,被组合到二种通信系统中,构成匹配电路和偏置电路。
例如,在一种通信系统中,组合了CP1-CP7、CP9-CP12、和CB1、CB2所示的电容性元件,RP1-RP4、和RP6所示的电阻元件、L1所示的电感器元件,以及四边形所示的条形线条(微带线)。
而且,在另一种通信系统中,组合了CG1-CG7、CG9-CG12、和CB3、CB4所示的电容性元件,RG1-RG4和RG6所示的电阻元件、L2所示的电感器元件,以及四边形所示的条形线条(微带线)。
在集成无源器件21中,图8中四边形框所示的匹配电路被组合。图6是主要作为等效电路的示意平面图,示出了组合到集成无源器件21中的电容性元件。如图6所示,电极22沿集成无源器件21的二侧被提供在集成无源器件21的上表面上。四边形表示的电极22一侧处所示的G意味着接地端子。
在一种通信系统中,电容性元件CP1和CP2构成起始级晶体管Q1的输入匹配电路,电容性元件CP3和CP4构成起始级晶体管Q1与下一级晶体管Q2之间的级间匹配电路,而电容性元件CP5-CP7构成下一级晶体管Q2与末级(输出级)晶体管Q3和Q4之间的级间匹配电路。而且,在另一种通信系统中,电容性元件CG1和CG2构成起始级晶体管Q5的输入匹配电路,电容性元件CG3和CG4构成起始级晶体管Q5与下一级晶体管Q6之间的级间匹配电路,而电容性元件CG5-CG7构成下一级晶体管Q6与输出级晶体管Q7和Q8之间的级间匹配电路。如图6所示,这些匹配电路被组合到集成无源器件21中。
图7是示意剖面图,示出了集成无源器件21的一部分。在此剖面图中,示出了构成下一级晶体管Q2与末级(输出级)晶体管Q3和Q4之间的级间匹配电路的电容性元件CP5、CP6、CP7。电容性元件CP5的电极之一被连接到形成在集成无源器件21上表面上的电极22(图6中左侧电极),而电容性元件CP7的电极之一被连接到形成在集成无源器件21上表面上的电极22(图6中右侧电极)。如图4所示,这些电极22经由金属丝23被电连接到位于第一半导体芯片15周围的金属丝连接焊点8。
如图7所示,集成无源器件(以下也称为“IPD”)21被制作成在有玻璃片之类组成的板34主表面上,主表面上具有绝缘层35,导电层和绝缘层被重复地层叠在各给定位置处并成预定的形状。在制作集成无源器件21的中间阶段,介质层被形成在各个预定导电层之间,电容性元件(电容器)从而如图7所示被形成。而且,虽然图中未示出,但有可能借助于在各个预定导电层之间插入电阻材料来形成电阻元件,并能够借助于以涡旋形式安置导电层而形成电感元件(电感器)。
在图7中,参考号36a、36b、36c、36d表示导电层,参考号37表示介质层,而参考号38和39表示绝缘层。图6所示电极22被暴露于没有形成构成最上面保护膜的绝缘层39的区域处。电极22具有适合于金属丝键合的平坦结构(见图1和图6)。而且,电极22可以被制作成凸块电极,以便能够进行倒装芯片连接。图7示出了以这种方式形成的电容性元件CP5、CP6、CP7。
IPD由于大量无源元件能够以小型化的形式被组合而已经被普遍采用。作为IPD,已知有借助于在印刷电路板上相继形成由导体或介质组成的薄膜而形成各个无源部件的结构以及在半导体板主表面上形成预定图形的扩散区同时形成绝缘层、布线等以便形成各个无源部件的结构。
用于本实施方案1的电容器具有约为1-50pF的电容值,且每个电容器的介质层38的面积约为300平方微米,因此,如图6所示,其中组合了大约14个电容器的集成无源器件21具有纵向约为1mm和横向约为1mm的小型化尺寸,集成无源器件21从而能够被充分地安装在第一半导体芯片15上。这种集成无源器件21利用小型化能够大幅度减小安装面积,达到安装14个分立芯片电容器所需面积的大约30%。
图5是示意图,示出了被安装和排列在模块板2上表面上的第一半导体芯片15、第二半导体芯片25、电子部件30等。此处,图中略去了金属丝和焊料。
根据本实施方案1的半导体模块1,组合了其热值大的输出级晶体管的第二半导体芯片25,被固定到凹陷10的底部,因此,热辐射被有效地传导,而组合了其热值比输出级晶体管热值足够小的初始级和下一级晶体管的第一半导体芯片15,被安装在模块板2的上表面上。
而且,在第一实施方案1中,输入匹配电路、偏置匹配电路、以及输出级晶体管Q3、Q4、Q7、Q8的输出匹配电路,由具有小容差的分立部件构成。亦即,本实施方案不使用具有通常容差(10欧姆±5%)的分立部件,而使用小容差(10欧姆±1%)的分立部件。因此,有可能提高例如大约2%的特性(功率效率)。
而且,在半导体模块1的制造中,作为构成末级放大器的输出匹配电路的分立部件,分别制备了多个特性不同的分立部件,并在用来改善特性的最终调试中,选择了各个特性一致的分立部件,并安装在模块板2上,从而能够制造具有良好特性的半导体模块。
根据本实施方案1,有可能得到下列有利效果。
(1)由于本实施方案的半导体模块1采用了三维安装结构将集成无源器件21安装和排列在安装于模块板2上表面上的第一半导体芯片15的上表面上,故与将第一半导体芯片与集成无源器件平行安装在模块板2上表面上的结构相比,此半导体模块1能够被小型化。
(2)由于借助于集成多个电容器而制作集成无源器件21,故与将各个分立电容器(分立部件)安装在模块板2上的结构相比,此半导体模块1能够被小型化。而且,借助于将这种集成无源器件21安装在第一半导体芯片15上,有可能获得半导体模块1的进一步小型化。
(3)在集成无源器件21中,组合了起始级晶体管(放大器)Q1和Q5的输入匹配电路和输出匹配电路。而且,集成无源器件21被安装在其中组合起始级放大器Q1和Q5的第一半导体芯片15上,因此,起始级放大器Q1和Q5、输入匹配电路、以及输出匹配电路被安排成彼此靠近,从而能够减小RF(高频)损耗和阻抗起伏。
(4)由于输出级晶体管Q3、Q4、Q7、Q8的输入匹配电路、偏置匹配电路、以及输出匹配电路由容差小的分立部件构成,故有可能提高特性(功率效率)。例如,能够提高功率效率大约2%。
(5)由于半导体模块采用了热值大的第二半导体芯片25被固定到形成于模块板2上表面上的凹陷10的底部上的结构,故能够经由通道11迅速地将热传送到模块板2下表面上的散热焊点5,从而有可能提供散热性能高的半导体模块1(高频功率放大器件)。因此,其中组合了这种半导体模块1的移动电话由于半导体模块1的良好的散热性能而能够以稳定的方式工作。
此处,解释了实施方案1的一种变形例。在用来解释此变形例的附图中,给出了解释所需的符号,且略去了某些符号。
图9是构成第一变形例的半导体模块的示意剖面图。此变形例的半导体模块1的特征在于,在实施方案1中,用倒装芯片连接方法,集成无源器件21被安装在被安装于模块板2上表面上的第一半导体芯片15的上表面上。因此,如图9所示,集成无源器件21的电极被预先形成为焊料凸块电极40,且同时在对应于焊料凸块电极40的第一半导体芯片15的上表面上形成倒装芯片连接的电极41。然后在安装集成无源器件21时,各个焊料凸块电极40被重叠到各个电极41,并利用短暂的加热来软化焊料凸块电极40(回流),以便在焊料凸块电极40与电极41之间建立连接。
在根据第一变形例的半导体模块1中,用倒装芯片连接方法,集成无源器件21被安装在第一半导体芯片15的上表面上,因而不使用金属丝。因此,不存在归咎于金属丝的电感起伏,且因此有可能获得提高特性且同时能够简化调试的优点。
图10是构成第二变形例的半导体模块的简化示意剖面图。此变形例的半导体模块1的特征在于,在实施方案1中,用倒装芯片连接方法,第二半导体芯片25被安装在形成于模块板2上表面上的凹陷10的底部上,利用绝缘粘合剂45,第一半导体芯片15被安装在第二半导体芯片25的上表面上,且用导电金属丝18,第一半导体芯片15的电极17和形成在凹陷10周围的模块板2上表面上的金属丝连接焊点8被彼此电连接。而且,变形例2采用了其中集成无源器件21被安装在模块板2上表面上,且形成于集成无源器件21上表面上的电极22和形成在集成无源器件21外围周围的模块板2的上表面上的金属丝连接焊点8,用导电金属丝23彼此电连接的结构。
在此变形例中,第二半导体芯片25的的电极被预先形成为焊料凸块电极46,且同时在对应于焊料凸块电极46的凹陷10的底部上形成倒装芯片连接的电极(未示出)。然后在安装第二半导体芯片25时,各个焊料凸块电极46被重叠到形成在凹陷10底部上的各个电极,并利用短暂的加热来软化焊料凸块电极46(回流),以便在焊料凸块电极46与电极之间建立连接。
在此变形例中,下一级和末级放大器的接地能够被焊料凸块电极46加固。由于起始级放大器中的地电位的起伏小,故使用金属丝18来连接电极17与金属丝连接焊点8的构造能够充分地克服起伏。图11是构成第三变形例的半导体模块的简化示意剖面图。此变形例的半导体模块的特征在于,在实施方案1中,其中组合了起始级、下一级、以及末级放大器的半导体芯片50,被安装在凹陷10的底部上,半导体芯片50的电极(未示出)与形成在模块板2上表面上的金属丝连接焊点(未示出),用导电金属丝51彼此连接,且利用倒装芯片连接方法,用焊料凸块电极40,形成在半导体芯片50上表面上的集成无源器件21与形成在模块板2上表面上的电极(未示出)被电连接。而且,借助于组合容差小的各个分立部件,来形成输出匹配电路。
在此变形例中,不存在归咎于金属丝的特性起伏,因此有可能呈现稳定的特性。还有可能具有不需要用于金属丝键合的板焊点这一有利的效果,因而能够实现进一步的小型化。
在本实施方案1中,虽然对高频功率放大器件的起始级放大器被组合到第一半导体芯片15中的例子已经进行了解释,但也有可能将控制高频功率放大器件的控制电路组合到第一半导体芯片15中。例如,能够组合诸如APC(自动功率控制电路)、AGC(自动增益控制电路)之类的电路作为控制电路。
(实施方案2)
图12-14涉及到构成本发明另一实施方案(实施方案2)的半导体模块。本实施方案的特征在于,在实施方案1的半导体模块1中,输出匹配电路被组合到集成无源器件55中,集成无源器件55被安装在模块板2的上表面上,形成在集成无源器件55上表面上的电极(未示出)和形成在集成无源器件55周围的模块板2上表面上的金属丝连接焊点(未示出),用导电金属丝56彼此电连接。因此,构成输出匹配电路的分立部件不被安装在模块板2的上表面上。本实施方案2的其它构造相同于实施方案1的相应构造。
图13是本实施方案的半导体模块1的等效电路图。就等效电路而论,此等效电路相同于用于实施方案1的图8所示的等效电路。点划线框环绕的部分是组合到集成无源器件55中的部分。亦即,在集成无源器件55中,组合了提供在末级(输出级)晶体管Q3和Q4的漏端子与输出端子Pout1之间的电容性元件CP9-CP12和电感器L1,以及提供在末级(输出级)晶体管Q7和Q8的漏端子与输出端子Pout2之间的电容性元件CG9-CG13和电感器L1。
图14是组合到半导体模块中的集成无源部分的剖面图,且示出了形成电容性元件CP12和CP11以及电感器L1的部分。借助于以涡旋形式安排导电层来形成电感器L1。此处,参考号36e、36f、36g、36h表示导电层。
在本实施方案中,输出匹配电路被组合到集成无源器件55中,且集成无源器件55被安装在模块板2的上表面上。因此,与借助于将多个分立部件安装在模块板2的上表面上来构成输出匹配电路的结构相比,半导体模块1能够被进一步大幅度小型化。而且,当模块板2不被做小时,能够安装进一步更大数目的分立部件,因此能够获得功能的进一步复杂化。
图15是简化示意剖面图,示出了构成实施方案2的第一变形例的半导体模块。在此变形例中,实施方案2的集成无源器件的电极构成凸块电极58,且利用凸块电极58,集成无源器件55被倒装芯片安装在模块板2的主表面上。
在此变形例中,由于用倒装芯片连接方法将集成无源器件55安装在模块板2上,故不使用金属丝。因而有可能具有不存在归咎于金属丝的电感起伏的优点,因此提高了特性,且同时能够简化调试。
图16是简化示意剖面图,示出了构成实施方案2的第二变形例的半导体模块。此变形例2的特征在于,在实施方案1的半导体模块1中,输出匹配电路被组合到集成无源器件55中,集成无源器件55被安装在安装于凹陷10底部上的第二半导体芯片25的上表面上,形成在集成无源器件55上表面上的电极(未示出)和形成在凹陷10周围模块板2上表面上的金属丝连接焊点(未示出),用导电金属丝56彼此电连接。因此,构成输出匹配电路的分立部件不被安装在模块板2的上表面上。本变形例2的其它构造相同于实施方案1的相应构造。在本变形例中,由于其中组合输出匹配电路的集成无源器件55被安装在第二半导体芯片25上,故模块板能够被进一步小型化。或者,能够安装进一步更大数目的分立部件,因此,能够获得功能的进一步复杂化。
(实施方案3)
图17是简化示意剖面图,示出了构成本发明另一实施方案(实施方案3)的半导体模块。除了安装第一半导体芯片15和集成无源器件21的位置不同之外,本实施方案3的半导体模块1具有相同于实施方案1的半导体模块1的结构。
亦即,本实施方案采用了第一半导体芯片15用间隔60安装在安装于模块板2的凹陷10底部上的第二半导体芯片25上,且同时集成无源器件21被直接安装在模块板2上表面上的结构。
间隔60被粘合剂(未示出)固定到第二半导体芯片25的上表面上,而第一半导体芯片15利用粘合剂(未示出)被固定到间隔60。为了防止第一半导体芯片15与第二半导体芯片25经由间隔60被彼此电连接,整个间隔60由绝缘材料制成,或芯片的中间层或表面层由构成绝缘层的材料制成。当间隔60的电绝缘足够时,粘合剂可以由绝缘材料或导电材料制成。当电绝缘不足时,可以采用具有绝缘性质的粘合剂作为此粘合剂。而且,间隔60可以由在其二个表面上都具有粘合性的绝缘胶带等制成。
间隔60被做成小于第二半导体芯片25,使间隔60不与第二半导体芯片25上表面上的电极(未示出)接触,并被固定到第二半导体芯片25的中央。被固定到间隔60上表面上的第一半导体芯片15,被安装成使其上有电极(未示出)的一面构成上表面。第一半导体芯片15的电极和形成在凹陷10周围模块板2的上表面上的金属丝连接焊点(未示出)用导电金属丝18彼此电连接。
形成在安装于模块板2上的集成无源器件21上表面上的电极(未示出)以及形成在集成无源器件21周围模块板2的上表面上的金属丝连接焊点(未示出),用导电金属丝23彼此电连接。
组合到起始级放大器中的第一半导体芯片15呈现出比将输出级放大器组合在其中的第二半导体芯片25的热值更小的热值,因此,也有可能将第一半导体芯片15安装在第二半导体芯片25上。借助于用具有良好热导率的材料形成间隔60,有可能将第一半导体芯片15产生的热经由间隔60、第二半导体芯片25、以及通道11迅速地传送到散热焊点5。
根据实施方案3的半导体模块1,由于第一半导体芯片15被安装在第二半导体芯片25上而无须将第一半导体芯片15安装在模块板2的上表面上,故模块板2能够被小型化,其缩小量是第一半导体芯片15未被安装在模块板2上的面积。而且,当模块板2不被小型化时,利用未被小型化的模块板2的面积,有可能安装其它的分立部件等,因此,能够获得功能的复杂化。
(实施方案4)
图18是简化示意剖面图,示出了根据本发明另一实施方案(实施方案4)的半导体模块。除了第一半导体芯片15和集成无源器件21之间的安装关系相反以及集成无源器件21的尺寸被做得大于第一半导体芯片15的尺寸之外,本实施方案4的半导体模块1具有与实施方案1的半导体模块1相同的构造。
亦即,在本实施方案4中,第一半导体芯片15不直接安装在模块板2的上表面上,集成无源器件21以其电极被形成在其上表面上的姿态用粘合剂(未示出)安装在模块板2的上表面上,且第一半导体芯片用粘合剂(未示出)安装在集成无源器件21的上表面上。
集成无源器件21被制作得足够大,致使半导体芯片15不会与集成无源器件21的电极(未示出)形成接触,且第一半导体芯片15被固定到集成无源器件21的中央,致使第一半导体芯片15不会与集成无源器件21的电极(未示出)形成接触。
形成在集成无源器件21上表面上的电极(未示出)和形成在集成无源器件21周围模块板2上表面上的金属丝连接焊点(未示出),用导电金属丝彼此电连接。形成在集成无源器件21上的第一半导体芯片15上表面上的电极(未示出)和形成在集成无源器件21周围模块板2上表面上的金属丝连接焊点(未示出),用导电金属丝彼此电连接。
在大面积电感被组合到集成无源器件21中的情况下,集成无源器件的尺寸变得大于半导体芯片15。本实施方案4提供了能够在这种情况下对半导体模块进行小型化的结构。在此情况下,电感器的容量为1-20nH。
图19是简化示意剖面图,示出了构成本实施方案4的变形例的半导体模块。此变形例与实施方案4的半导体模块1的不同在于,将第一半导体芯片15安装在其上表面上的集成无源器件21,用倒装芯片连接方法被安装在模块板2的上表面上。
在此变形例中,实施方案4的集成无源器件21的电极构成凸块电极61,利用倒装芯片安装方法,集成无源器件21经由凸块电极61,被安装在模块板2的上表面上,且第一半导体芯片15以其电极被形成在上表面上的状态,被安装在集成无源器件21的上表面上。
在此变形例中,集成无源器件21的电极和模块板2的电极,不用金属丝彼此连接。亦即,这些电极用凸块电极彼此电连接,因此有可能具有消除归咎于金属丝的电感起伏从而提高特性且同时能够简化调试的有利效果。
(实施方案5)
图20是构成本发明另一实施方案(实施方案5)的半导体模块的简化示意剖面图。
本实施方案5的半导体模块1的特征在于,不同于安装在实施方案3的半导体模块1中模块板2的上表面上的集成无源器件21,此集成无源器件21被安装在利用间隔60,以重叠的方式安装于半导体芯片25上的第一半导体芯片15上。本实施方案的其它结构部件与实施方案3的半导体模块1的相应结构部件相同。
安装在第一半导体芯片15上表面上的集成无源器件21被做得小于第一半导体芯片15,致使集成无源器件21不会与形成在第一半导体芯片15上表面上的电极(未示出)形成接触,且同时,集成无源器件21被安装在第一半导体芯片15的中央位置上。
形成在集成无源器件21上表面上的电极(未示出)和形成在凹陷10周围模块板2上表面上的金属丝连接焊点(未示出),用导电金属丝23彼此电连接。
根据实施方案5的半导体模块1,由于集成无源器件21被安装在第二半导体芯片25上而不将集成无源器件21安装在模块板2的上表面上,故模块板2能够被小型化,缩小的量是不安装集成无源器件21的面积。而且,当模块板2不被小型化时,有可能利用不被小型化的模块板面积来安装其它的分立部件,因此能够得到功能的复杂化。
(实施方案6)
图21是本发明另一实施方案(实施方案6)的半导体模块的简化示意剖面图。
除了安装第一半导体芯片15和集成无源器件21的位置之外,本实施方案6的半导体模块1采用与实施方案1的半导体模块1相同的构造。
亦即,本实施方案6的半导体模块1采用了这样一种结构,其中,具有凸块电极58的集成无源器件21用倒装芯片连接方法被安装在安装于模块板2的凹陷10底部上的第二半导体芯片25上,第一半导体芯片15以电极被形成在上表面上的状态被安装在集成无源器件21的上表面上,且第一半导体芯片15的电极(未示出)和形成在凹陷10周围模块板2上表面上的金属丝连接焊点(未示出)用导电金属丝18彼此电连接。
虽然图中未示出,但集成无源器件21的各个凸块电极58被电连接到第一半导体芯片15的各个电极,并构成图8所示的部分等效电路。
本实施方案6的半导体模块1被构造成使第一半导体芯片15和集成无源器件21被安装在第二半导体芯片25上,而不将第一半导体芯片15和集成无源器件21安装在模块板2的上表面上,因此,模块板2能够被小型化,缩小的量是不安装第一半导体芯片15和集成无源器件21的面积。而且,当模块板2不被小型化时,有可能利用不被小型化的模块板面积来安装其它的分立部件,因此能够得到功能的复杂化。
虽然基于各个实施方案已经具体解释了本发明人提出的本发明,但不言自明,本发明不局限于上述各个实施方案,而是能够作出各种变形例而不偏离本发明的主旨。虽然MOSFET(金属氧化物半导体场效应晶体管)被用作放大器(晶体管),但放大器也可以由包含其它硅或化合物半导体的双极基晶体管组成。
Claims (38)
1.一种半导体模块,它包含:
模块板,其上表面上具有布线,且其下表面上具有外部电极端子;
形成在模块板上且包括有源元件的第一半导体芯片和第二半导体芯片;以及
集成无源器件,
其中,第一半导体芯片和第二半导体芯片之一以及集成无源器件,以重叠的方式被安装在模块板的上表面上。
2.根据权利要求1的半导体模块,其中,第一半导体芯片和第二半导体芯片包括放大电路,且第一半导体芯片的输出被输入到第二半导体芯片。
3.根据权利要求2的半导体模块,其中,级间匹配电路被提供在第一半导体芯片和第二半导体芯片之间,且级间匹配电路由集成无源器件组成。
4.根据权利要求3的半导体模块,其中,半导体模块包括连接到第一半导体芯片的输入部分的输入匹配电路以及连接到第二半导体芯片的输出部分的输出匹配电路,且输出匹配电路借助于连接分立部件而构成。
5.一种半导体模块,它包含:
模块板,其上表面上具有布线,且其下表面上具有外部电极端子;
形成在模块板上且包括有源元件的第一半导体芯片和第二半导体芯片;以及
集成无源器件,
其中,第一半导体芯片被安装在第二半导体芯片上。
6.根据权利要求5的半导体模块,其中,第二半导体芯片的热值大于第一半导体芯片的热值。
7.根据权利要求6的半导体模块,其中,分立部件被安装在模块板的上表面上。
8.根据权利要求6的半导体模块,其中,集成无源器件被安置在第一半导体芯片上。
9.根据权利要求6的半导体模块,其中,集成无源器件被安装在第一半导体芯片的上表面上,且第二半导体芯片被安装在集成无源器件上。
10.根据权利要求9的半导体模块,其中,分立部件被安装在模块板的上表面上。
11.根据权利要求6的半导体模块,其中,第一半导体芯片和第二半导体芯片包括放大电路,第一半导体芯片的输出被构造成输入到第二半导体芯片,且级间匹配电路被提供在第一半导体芯片和第二半导体芯片之间。
12.根据权利要求11的半导体模块,其中,半导体模块包括连接到第一半导体芯片的输入部分的输入匹配电路以及连接到第二半导体芯片的输出部分的输出匹配电路,且输出匹配电路借助于连接分立部件而构成。
13.一种半导体模块,它包含:
模块板,其上表面上具有布线,且其下表面上具有外部电极端子;
其上制作有源元件的第一半导体芯片和第二半导体芯片;以及
第一集成无源器件,
其中,第一半导体芯片和第二半导体芯片安置在模块板的上表面一侧,二者之间具有预定的距离。
14.根据权利要求13的半导体模块,其中,第一集成无源器件被排列在第一半导体芯片的上表面上。
15.根据权利要求14的半导体模块,其中,分立部件被安装在模块板的上表面上。
16.根据权利要求14的半导体模块,其中,第二集成无源器件被安装在模块板的上表面上,且包括有源元件的半导体芯片不存在于第二集成无源器件与模块板之间。
17.根据权利要求16的半导体模块,其中,分立部件被安装在模块板的上表面上。
18.根据权利要求14的半导体模块,其中,第二集成无源器件被安装在模块板的上表面上,且第二集成无源器件被安装在第二半导体芯片的上表面上。
19.根据权利要求13的半导体模块,其中,第一集成无源器件被安置在第一半导体芯片下方。
20.根据权利要求19的半导体模块,其中,用倒装芯片连接方法将第一集成无源器件安装在模块板的上表面上。
21.根据权利要求20的半导体模块,其中,分立部件被安装在模块板的上表面上。
22.根据权利要求19的半导体模块,其中,分立部件被安装在模块板的上表面上。
23.根据权利要求13的半导体模块,其中,第一半导体芯片和第二半导体芯片包括放大电路,第一半导体芯片的输出被构造成输入到第二半导体芯片,级间匹配电路被提供在第一半导体芯片和第二半导体芯片之间,且级间匹配电路由集成无源器件组成。
24.根据权利要求23的半导体模块,其中,半导体模块包括连接到第一半导体芯片的输入部分的输入匹配电路以及连接到第二半导体芯片的输出部分的输出匹配电路,且输出匹配电路借助于连接多个分立部件而构成。
25.一种半导体模块,它包含:
模块板,其上表面上具有布线,且其下表面上具有外部电极端子;以及
形成在模块板上且包括有源元件的第一半导体芯片和第二半导体芯片,
其中,第一半导体芯片和第二半导体芯片沿水平方向以其间预定的距离被安置在模块板的上表面一侧上,
其中,第一集成无源器件被安装在第一半导体芯片上,
其中,第一半导体芯片和第二半导体芯片包括放大电路,
其中,第一半导体芯片的输出被构造成输入到第二半导体芯片,
其中,级间匹配电路被提供在第一半导体芯片和第二半导体芯片之间,且
其中,级间匹配电路由第一集成无源器件组成。
26.根据权利要求25的半导体模块,其中,半导体模块包括连接到第一半导体芯片的输入部分的输入匹配电路以及连接到第二半导体芯片的输出部分的输出匹配电路,且输出匹配电路借助于连接分立部件而构成。
27.根据权利要求26的半导体模块,其中,第一半导体芯片和模块板被导电金属丝彼此电连接,且第一集成无源器件和模块板被导电金属丝彼此电连接。
28.根据权利要求26的半导体模块,其中,第二集成无源器件被安装在模块板的上表面上,且包括有源元件的半导体芯片不存在于第二集成无源器件与模块板之间。
29.根据权利要求28的半导体模块,其中,第二集成无源器件和模块板被导电金属丝彼此电连接。
30.一种半导体模块,它包含:
模块板,其上表面上具有布线,且其下表面上具有外部电极端子;以及
包括有源元件的第一半导体芯片和第二半导体芯片,
其中,第一半导体芯片和第二半导体芯片沿水平方向以其间预定的距离被安置在模块板的上表面一侧上,
其中,第一集成无源器件被安置在第一半导体芯片下方,
其中,第一半导体芯片和第二半导体芯片包括放大电路,
其中,第一半导体芯片的输出被构造成输入到第二半导体芯片,
其中,级间匹配电路被提供在第一半导体芯片和第二半导体芯片之间,且
其中,级间匹配电路由第一集成无源器件组成。
31.根据权利要求30的半导体模块,其中,半导体模块包括连接到第一半导体芯片的输入部分的输入匹配电路以及连接到第二半导体芯片的输出部分的输出匹配电路。
32.根据权利要求31的半导体模块,其中,第一集成无源器件用倒装芯片连接方法安装在模块板的上表面上。
33.一种半导体模块,它包含:
模块板,其上表面上具有布线,且其下表面上具有外部电极端子;以及
包括有源元件的半导体芯片;以及
安装在半导体芯片上表面上的集成无源器件,
其中,半导体芯片包括第一放大电路和第二放大电路,
其中,第一放大电路的输出被构造成输入到第二放大电路,
其中,级间匹配电路被提供在第一放大电路和第二放大电路之间,且
其中,级间匹配电路由集成无源器件组成。
34.根据权利要求33的半导体模块,其中,半导体模块包括连接到第二放大电路的输出部分的输出匹配电路,且输出匹配电路借助于连接多个分立部件而构成。
35.根据权利要求1的半导体模块,其中,半导体模块包括形成在模块板下表面上的散热焊点以及制作成垂直贯穿模块板且下部末端连接到散热焊点的多个通道,且第二半导体芯片被安置在多个通道上。
36.根据权利要求35的半导体模块,其中,凹陷被形成在模块板的上表面中,且多个通道被制作在凹陷底部中,第二半导体芯片被安装在凹陷的底部上方。
37.根据权利要求1的半导体模块,其中,第一半导体芯片、第二半导体芯片、以及集成无源器件,被绝缘树脂制作的密封部分覆盖。
38.根据权利要求37的半导体模块,其中,密封部分的端部不位于模块板端部的外面。
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JP2002379047A JP2004214258A (ja) | 2002-12-27 | 2002-12-27 | 半導体モジュール |
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Also Published As
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US7176579B2 (en) | 2007-02-13 |
TW200423379A (en) | 2004-11-01 |
US20040125579A1 (en) | 2004-07-01 |
JP2004214258A (ja) | 2004-07-29 |
US20060171130A1 (en) | 2006-08-03 |
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