CN1809925A - 优化的多用途组件 - Google Patents
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Abstract
本发明涉及一种微电子芯片组件ASY,其包括至少三个叠置到一起的微电子芯片ICH,TCH,BCH,芯片上形成集成器件。至少一个芯片,其称作中间芯片ICH,包括穿过所述芯片ICH的通孔VH,孔中充填有导电材料,该芯片在高电阻基片上形成,芯片上形成器件,可实现至少两个其他微电子芯片,称作上芯片TCH和下芯片BCH的功能。所述上和下芯片TCH,BCH通过倒装晶片接合分别连接到所述中间芯片ICH的上表面TF和下表面BF,所述通孔VH电连接所述上和下芯片TCH,BCH的焊点。
Description
技术领域
本发明涉及电子系统组装的领域,具体地,本发明涉及一种组件,其结合至少三个微电子芯片,芯片上形成集成器件,所述芯片叠置在一起,至少一个芯片包括穿过所述芯片的通孔,其中填充导电材料。本发明还涉及用于这种组件的微电子芯片,以及组装系统,其包括至少一个这样的组件。最后,本发明还涉及制造这种组件的方法。
背景技术
这种组件可从美国专利文献US 2001/0006257了解。在该文献中,介绍了实现至少三个微电子芯片的组件的方法,其中芯片形成有集成器件,所述芯片叠置到一起,至少一个芯片包括通孔,其穿过所述芯片并填充有导电材料。
在这份文献中,通过插入粘性层到两个芯片之间将一个芯片叠置到另一个芯片上。一旦芯片叠加后,孔穿过上芯片,并充填导电材料。这表示所述孔需要在芯片的特定部分实现,以便不损坏集成到芯片上的器件。这份文献提出的组件是类似有源芯片的组件。一旦三个芯片重叠和接触,与外部电路或无源元件的连接必须通过涂复到最高芯片的保护层来实现。
因此,该现有技术的文献提出的组件存在缺点和局限性,涉及到这种组件在复杂系统的实现和小型化的质量问题。
发明内容
本发明的目的是提出一种微型化和容易实现的适用于复杂系统的多个微电子芯片的组件。
通过一种前言部分提出的微电子芯片组件实现了本发明的目的,包括通孔的所述芯片,称为中间芯片,由高电阻基片形成,其上设置了可被至少两个其他微电子芯片使用的器件,这两个芯片称为上和下芯片,通过倒装晶片接合分别连接到所述中间芯片上和下表面的,所述通孔实现所述上和下芯片的焊点之间的电连接。
本组件使得可首先和独立地进行准备中间芯片的安装步骤。接下来,制造所述中间芯片期间,在集成器件和所述中间芯片的非专用于集成器件的表面之间形成通孔。从而实现非常好的小型化。
中间芯片用高电阻基片制造,其上设置了两个其他微电子芯片使用的特殊器件。由于高电阻特性,意味着半导体材料的一部分具有大于100欧姆的电阻,最好至少为1000欧姆。这些特殊器件可以是外围器件,如偏心片状线圈或去耦电容。没有这些器件,上和下芯片将不能正确工作。如果外围器件只是无源器件,屏蔽很简单而且中间芯片很便宜。
当上和下芯片通过倒装晶片接合进行连接时,使得组件避免使用引线,引线可引入寄生元件和限制性能,尤其是高频性能。具体地,本发明使得与集成到所述中间芯片的外围器件的连接短而可靠,并致力于实现上和下芯片的功能。
该组件的组装通过倒装晶片接合可以容易地连接所述中间芯片,使所述中间芯片连接到外连接机构,允许与外电路连接。因此,与外电路的连通很容易实现并具有良好的质量。所述连接机构最好是引线框型的组装件或然后进行组装的基片。在组件有多个中间芯片的情况下,只有一个中间芯片通过倒装晶片接合连接到连接机构。
本发明还可用于其上形成任何种类器件的芯片。但是,不同的集成器件之间非常靠近可能出现干涉,使得包括组件的整个系统的功能不是最优化。例如,以高频工作的器件对寄生元件非常敏感。此外,高功率器件可对非常紧凑的组件造成损坏,如本发明的组件。
在优选实施例中,对集成到下,中间和上芯片的器件进行选择,使所述器件相对所述连接机构以特定次序叠置,使得所述组件具有尽可能高的性能。特定次序可使得具有性能波动度高的器件集成在下芯片,而性能波动度低的器件集成到上芯片。
这使得性能易波动的器件的连接短,使得组件的不同器件的连接优化。高频信号路径和高能量信号路径要求非常低电阻、低感抗或低阻抗路径,以便分别得到高频性能和优化功率器件的功率产出。高频或高功率器件因此最好在非常接近连接机构的芯片实现,因此在下芯片实现。
在优选实施例中,所述连接机构包括热汇,专用来与所述下芯片接触。
这使得发热装置接触所述热汇。在这种情况下,发热器件集成到所述下芯片。由于形成的组件非常紧凑,本发明的组件将产生强热。热量是集成到下芯片的高频或高功率器件产生。
在特定实施例中,至少一个发热器件集成到所述下芯片,所述下芯片与所述热汇接触。
在特定的实施例中,至少一个高频器件集成到所述下芯片,所述下芯片与所述热汇接触。
优选实施例允许单独器件,如温度敏感器件远离发热器件,形成紧凑的以高频工作的器件。
在特定实施例中,器件集成到所述中间芯片的两侧。这样的特征可使更多的器件集成到所述中间芯片。例如,用于上芯片的器件集成到上侧,用于下芯片的器件集成到下侧。通孔用于实现两种类型器件之间的连接,用于直接连接上和下芯片。
本发明还涉及组装系统,其包括至少三个器件,分别集成到单独芯片,芯片设置在根据本发明的组件。在下面给出这种系统的示例。
本发明最后涉及一种制造微型化组装系统的方法,系统包括至少一个微电子组件。该方法包括步骤:用高电阻基片制造至少一个芯片,称为中间芯片,其包括位于至少一个表面的集成器件,和穿过所述芯片并充填有导电材料的通孔。然后,根据本发明的方法,进行连接步骤,所述中间芯片通过倒装晶片接合连接至少一个芯片,称为下芯片,其包括位于一个表面的集成器件,使所述通孔连接所述下芯片的端接点。然后,中间芯片通过倒装晶片接合连接到连接机构,使所述下芯片叠置到所述中间芯片和所述连接机构之间。其后进行连接步骤,所述中间芯片通过倒装晶片接合连接到第三芯片,第三芯片称为上芯片,其包括位于一个表面的集成器件,使通孔连接到上芯片的端接点。最后组件用模制部件进行模制。
这个方法允许通过其他技术,如单个芯片集成技术,实现非常紧凑的系统,具有与较大系统相同的功能。因此,这种方法避免了于同一芯片集成不同种类的器件。根据本发明,不同的芯片可独立有效地实现,然后进行组装。
附图说明
下面将参考附图详细介绍本发明,附图中:
图1显示了根据本发明的微电子芯片组件;
图2显示了本发明的系统的应用示例;
图3显示了根据本发明的实施例的微电子芯片组件;
图4显示了根据本发明的制造微型化的组装系统的方法的步骤。
具体实施方式
本文中使用“上”和“下”来表示相对微电子芯片组件的结构或连接机构的方向。应当知道,这些词用于组件本身或所述连接机构的参照系,不能用于普通的重力参照系。
术语“器件”是指任何可集成到微电子芯片上的元件,功能件,电路,应用件等。
术语“系统”是指任何电子功能件的组合,以实现完整的应用,不是指单个集成电路IC。
图1显示了根据本发明的微电子芯片组件ASY。该组件包括三个微电子芯片TCH,ICH,BCH,上面形成集成器件。集成器件使用半导体或半绝缘技术进行集成。
图中的粗线表示端接点PAD。这些端接点是涂复在芯片上的导电材料。所述端接点是芯片上形成的集成器件的一部分。
三个芯片叠置到一起。一个芯片称为中间芯片ICH,用高电阻基片形成,其包括穿过所述中间芯片ICH并充填有导电材料的通孔VH。所述通孔连接到集成在所述中间芯片ICH至少一个表面的端接点。所述中间芯片ICH还可包括位于两侧,即下表面BF和上表面TF,的端接点。
两个其他微电子芯片,称为上和下芯片TCH,BCH,通过倒装晶片接合连接到所述中间芯片ICH的上表面TF和下表面BF。所述上和下芯片TCH和BCH因此通过电连接,如连接领域都已知道的倒装晶片接合,连接到所述中间芯片ICH。
倒装晶片接合的连接方法提供了较短的信号路径,因此器件之间具有比其他方法,如带自动接合法和传统的引线接合法,更快速的连通。此外,接合的端接点不限于芯片的周边。端接点可位于进行连接的多个位置。例如,芯片的端接点可电镀多层金属形成凸部,用于倒装晶片接合法的连接。电镀沉积之后,加热芯片使金属重熔,沉积物产生表面张力形成半球型钎焊点。然后可从芯片所在的晶片切割出上和下芯片,并倒转,与端接点和/或所述中间芯片ICH的通孔VH对准,这些凸点因此接触所述中间芯片ICH的端接点和/或通孔VH,同时均匀加热,在中间芯片的端接点与对准的上和下芯片的端接点之间形成连接。下面介绍使用倒装晶片接合方法的不同步骤。任何其他的在两个芯片之间实现倒装晶片接合的技术都可使用。例如,实现电连接的包括导电材料微球的粘接层也可以使用,以便无需凸部实现粘接和连接。这些技术和其他的方式在微电子领域都是已知的。
倒装晶片接合的主要优点是连接是直接的,避免了使用引线。根据本发明,所述通孔VH直接接触所述上和下芯片的端接点,以便直接在所述上和下芯片之间和在中间芯片和上或下芯片之间实现电连接。
由三个芯片构成的组件然后设置在连接机构CDV上,连接机构可以是基底或引线框。所述基底或引线框与组件之间连接的实现通过采用倒装晶片接合来连接所述中间芯片ICH到所述连接机构CDV。连接机构CDV可与外部电路的连接。连接机构CDV为组装领域的技术人员所公知。
在优选实施例中,连接机构包括热汇,用于接触下芯片BCH。这使得本发明的组件累积的能量发散。由于本发明具有非常紧凑的系统,这个特征是很重要的,因为累积的能量可造成系统损坏。
根据本发明,集成于不同芯片的不同器件可通过中间芯片进行连接,中间芯片设置了必要的周边机构,可使不同的器件集成于上和下芯片。
图2显示了本发明系统的应用的实施例。该系统具有电子功能,因此必要的器件可分别置于三个芯片。在这种情况下,本发明可使得性能和成本得到优化。
因此,当要求采用不同制造方法的不同种类的器件需要置于一个系统时,本发明有很大优越性。例如,系统可由功率器件和连接到所述功率器件的无源器件构成。信号处理装置也可以成为系统的一部分。所有这些不同的器件要求不同的集成方式。本发明可使得形成紧凑的系统,其包括所有这些器件,同时保持非常简单的制造过程。实际上,包括不同种类器件的不同芯片单独形成,其后用本发明的方法互相连接。
图2显示了本发明的实施例,其包括集成的高频收发器TSC和数字基带器BB。所述高频收发器TSC要求无源器件MD,其至少包括电感器和去耦电容器以及高频匹配器件。本发明允许将这三个不同器件分置于三个不同芯片。在本发明的优选实施例中,所述高功率和高频器件可具优越性地集成到下芯片以接近热汇。因此,无源器件MD可集成到中间芯片ICH,以便与下芯片上形成的高功率和高频率器件有较短的连接。这样通过与所述连接机构相连的所述中间晶片ICH还为高频器件提供了良好接地。实际上,收发器的RF前端部分要求高质量的接地连接。本发明还有经济上的优点,因匹配器件如电感器设置在中间芯片,中间芯片是用便宜的高电阻基片制造。
在根据本发明的系统中,不必要整个基片都为高电阻,只需一定区域是高电阻,而其他区域可以是低电阻。RF部分的电感器最好位于低电阻区。
此外,集成无源器件要求使用比集成数字器件少的屏蔽。这导致中间芯片便宜。数字基带和程序化的电路可在上芯片TCH实现。这些器件即使在质量低的接地连接情况下也可正常工作。此外,这些器件一般不发热。
图中显示了从下芯片到上芯片的特定次序,在这个示例中,中间芯片一表面集成了无源元件,可用于下芯片形成的高频和功率器件。通过所述穿过中间芯片的通孔建立与上芯片的连接。本发明还包括在中间芯片的两侧形成器件的情况。在这种情况下,与上芯片形成的器件互相作用的器件集成到中间芯片的另一(上)侧。
根据本发明的一个完整组装系统包括数字低功率器件,高功率器件,存储器,模拟器件,高频小信号器件,高功率模拟器件,高频器件。这个列表不是详尽的。可应用本发明到该系统的任何种类的器件,优选实施例的从下到上的特定次序是性能波动器件到低性能波动度器件,如高频器件到低功率消耗的数字器件。
根据这个特定次序,包括高功率消耗的数字器件的功率器件在下芯片形成,直接接触热汇。包括无线频率器件的高频率器件也直接接触热汇。高性能模拟器件也在下芯片形成,可形成良好的能量发散和低阻抗接地连接,这是高频器件所必要的。不同种类的器件可集成到单个下芯片或多个下芯片。因此,任何性能波动器件最好在所述下芯片上实现。
根据这个特定次序,应用的下芯片上形成的器件最好集成在所述中间芯片ICH的下表面BF。这些器件包括上面显示示例中的匹配器件。如果所述器件集成在上表面TF。与集成在所述下芯片的器件的连接可通过穿过中间芯片的通孔来实现。但是,与所述下芯片的连接的质量低于所述器件在下表面上实现的质量,因为包括通孔长度的话,这些连接的长度很长。
根据这个特定次序,该上芯片或多个上芯片包括低功率器件,低频率模拟器件,低功率数字器件和存储器。这个列表不是穷尽的。任何低性能波动度器件最好集成到所述上芯片,其可通过倒装晶片接合连接到所述中间芯片。与中间和下芯片上集成器件的连接可通过通孔来实现。
中间芯片的上表面TF最好包括必要的器件,以便使集成到上芯片的器件工作正常。还注意到,当上芯片直接连接到中间芯片,其通过连接机构接地连接,可使接地连接具有很好的质量。
因此,本发明提出了一种优化的多用途组件,可实现组装结构中微型和便宜系统的系统性能优化。通过扩展,可叠置多个夹持的芯片以便适应多种应用。在这种扩展中,需要多个中间芯片。尽管存在这个从下到上的次序,要求低阻抗连接到低功率低频率应用器件的高频应用器件需要防止高能量消耗。例如,优选的从下到上的次序是从高功率到低功率器件,从高频率到低频率器件。优选次序的总特征是从高性能波动度器件到低性能波动度器件。
不使用接合引线可实现优良性能。已知道引线可限制电系统的高频性能,引线可产生干扰,损害信号的完整性。
图3示意性地显示了根据本发明的实施例的微电子芯片组件。在这个实施例中,显示出上和下芯片31,32的周边器件的示例设置在中间芯片30的相对表面。其中下芯片接近与外电路相连的连接机构。因此,高性能波动度芯片最好集成到下芯片32。下芯片32可以是高频率高功率芯片,并通过倒装晶片接合连接到地线GND和连接到中间芯片,倒装晶片接合用位于电路连接片之间的球形表示。下芯片使用设置在中间芯片30下表面的线圈33。上芯片31可以是数字IC,通过倒装晶片接合连接到中间芯片,上芯片使用设置在中间芯片30上表面的电源电压退耦电容器34。垂直影线表示电路连接片。倾斜影线代表带有有源器件的数字器件。通孔用穿过中间芯片30的垂直粗线表示。
还可以使用位于中间芯片的外围器件排列,这使得整个组件更小和更便宜。这种外围元件的示例是电阻,不同尺寸的电容(垂直沟槽电容,薄膜金属-绝缘器-金属电容,感应器等)。
图4a到图4f介绍了本发明的用于制造微型化组装系统的方法的主要步骤,其包括根据本发明的至少一个微电子组件。
图4a显示了晶片WAF,其上形成中间芯片ICH。图4a只显示了一个中间芯片ICH。其他的芯片集成在其旁边,位于虚线表示的晶片。所述中间芯片包括位于至少一个表面的集成器件和通孔VH,其穿过所述芯片并填充有导电材料。所述通孔VH根据公知的微电子技术形成。
下芯片单独实现。其包括位于一个表面的集成器件。然后至少一个下芯片通过倒装晶片接合连接到所述第一晶片,使得所述下芯片的端接点与所述中间芯片的通孔相连的端接点对准。这在图4b中显示。下芯片连接到所述中间芯片ICH的下表面BF。在图4中的“下”相对于最终的组件,不相对于中间芯片和其他芯片在实施本发明期间可能处于的不同位置。
其后对所述下芯片倒装接合的所述晶片进行切割。得到图4c所显示的微电子中间组件。
带有倒装下芯片的所述中间芯片然后通过倒装晶片接合连接到连接机构CDV。所述下芯片因此叠置在所述中间芯片和所述连接机构CDV之间。所述下芯片最好与上面介绍过的热汇接触。所述热汇是所述连接机构的一部分。所述下芯片叠置在所述中间芯片和所述热汇之间,如图4d所示。
第三芯片称作上芯片,其通过倒装晶片接合和使所述通孔对准所述上芯片的端接点,连接到所述中间芯片的上表面TF。图4e显示得到的组件。
最后,根据组装技术,组件通过模制部件MC进行模制。得到如图4f所示的组装系统。
附图显示了本发明的说明性特定实施例,其不是限制性的。对于所属领域的技术人员,很明显对于上面列出的本发明的示例性实施例可进行许多改进和变化,这基本未脱离本发明的原理,所有这些改进和变化都包括其中。
Claims (9)
1.一种微电子芯片组件,包括至少三个叠置到一起的微电子芯片,至少一个芯片,即中间芯片,包括穿过其中的通孔,孔中充填导电材料,其特征在于,所述中间芯片由高电阻基片形成,芯片上形成至少两个其他微电子芯片,称作上芯片和下芯片,使用的器件,所述上和下芯片设置在所述中间芯片的至少一个表面上,所述上和下芯片通过倒装晶片接合分别连接到所述中间芯片上表面和下表面,所述通孔可实现所述上和下芯片焊点之间的电连接。
2.根据权利要求1所述的组件,其特征在于,所述中间芯片可与外电路连接,所述中间芯片通过倒装晶片接合连接到外连接机构。
3.根据权利要求2所述的组件,其特征在于,高和低性能波动度器件集成到所述下、中间和上芯片,所述器件按特定次序相对所述连接机构叠置,所述特定次序是高性能波动度器件集成到下芯片,低性能波动度器件集成到上芯片。
4.根据权利要求2或3所述的组件,其特征在于,所述连接机构包括热汇,可实现与所述下芯片的接触。
5.根据权利要求4所述的组件,其特征在于,至少发热器件集成到所述下芯片,所述下芯片与所述热汇接触。
6.根据权利要求4所述的组件,其特征在于,至少高频器件集成到所述下芯片,所述下芯片与所述热汇接触。
7.根据权利要求1或2所述的组件,其特征在于,所述中间芯片包括两侧的集成器件。
8.一种组装系统,包括至少三个集成到各自单独芯片的器件,其特征在于,所述芯片设置成权利要求1到7中任一项所述的组件。
9.一种制造微型化组装系统的方法,所述组装系统包括至少一个微电子组件,其特征在于,所述方法包括步骤:
用高电阻基片得到至少一个芯片,称为中间芯片,其包括位于至少一个表面的集成器件,和穿过所述芯片并充填有导电材料的通孔;
所述中间芯片通过倒装晶片接合连接至少一个芯片,称为下芯片,其包括位于一个表面的集成器件,使所述通孔连接所述下芯片的端接点;
所述中间芯片通过倒装晶片接合连接到连接机构,使所述下芯片叠置到所述中间芯片和所述连接机构之间;
所述中间芯片通过倒装晶片接合连接到第三芯片,第三芯片称为上芯片,其包括位于一个表面的集成器件,使所述通孔连接到所述上芯片的端接点;
所述组件通过模制部件进行模制。
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DE1514818A1 (de) * | 1951-01-28 | 1969-05-08 | Telefunken Patent | Festkoerperschaltung,bestehend aus einem Halbleiterkoerper mit eingebrachten aktiven Bauelementen und einer Isolierschicht mit aufgebrachten passiven Bauelementen und Leitungsbahnen |
US6593645B2 (en) * | 1999-09-24 | 2003-07-15 | United Microelectronics Corp. | Three-dimensional system-on-chip structure |
US6559499B1 (en) * | 2000-01-04 | 2003-05-06 | Agere Systems Inc. | Process for fabricating an integrated circuit device having capacitors with a multilevel metallization |
US6384468B1 (en) * | 2000-02-07 | 2002-05-07 | International Business Machines Corporation | Capacitor and method for forming same |
JP3854054B2 (ja) * | 2000-10-10 | 2006-12-06 | 株式会社東芝 | 半導体装置 |
ITTO20010050A1 (it) * | 2001-01-23 | 2002-07-23 | St Microelectronics Srl | Dispositivo integrato a semiconduttori includente interconnessioni adalta tensione attraversanti regioni a bassa tensione. |
US6633005B2 (en) * | 2001-10-22 | 2003-10-14 | Micro Mobio Corporation | Multilayer RF amplifier module |
TW533561B (en) * | 2002-02-26 | 2003-05-21 | Orient Semiconductor Elect Ltd | Opening-type multi-chip stacking package |
-
2004
- 2004-06-11 CN CNB2004800170897A patent/CN100365798C/zh not_active Expired - Lifetime
- 2004-06-16 EP EP04736936A patent/EP1639643A1/en not_active Withdrawn
- 2004-06-16 WO PCT/IB2004/002022 patent/WO2004114407A1/en not_active Application Discontinuation
- 2004-06-16 US US10/562,295 patent/US20070018298A1/en not_active Abandoned
- 2004-06-16 KR KR1020057024491A patent/KR20060026434A/ko not_active Application Discontinuation
- 2004-06-16 CN CNA2004800173518A patent/CN1809925A/zh active Pending
- 2004-06-16 JP JP2006516563A patent/JP2007516588A/ja not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
CN1809919A (zh) | 2006-07-26 |
KR20060026434A (ko) | 2006-03-23 |
EP1639643A1 (en) | 2006-03-29 |
JP2007516588A (ja) | 2007-06-21 |
US20070018298A1 (en) | 2007-01-25 |
WO2004114407A1 (en) | 2004-12-29 |
CN100365798C (zh) | 2008-01-30 |
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