JP4866625B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4866625B2 JP4866625B2 JP2006037931A JP2006037931A JP4866625B2 JP 4866625 B2 JP4866625 B2 JP 4866625B2 JP 2006037931 A JP2006037931 A JP 2006037931A JP 2006037931 A JP2006037931 A JP 2006037931A JP 4866625 B2 JP4866625 B2 JP 4866625B2
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- Prior art keywords
- semiconductor chip
- pad
- input
- signal
- amplifying unit
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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Description
図1は、例えばデジタル携帯電話機における信号送受信部のブロック図を示したものである。図1において、携帯電話機における信号送受信部は、デジタル信号処理部1、IF(Intermediate Frequency)部2、変調信号源3、ミキサ4、RFモジュール5、アンテナスイッチ6、アンテナ7、低雑音増幅器8を有している。
次に、本実施の形態2について説明する。前記実施の形態1では、増幅回路を形成している半導体チップ28としてGaAs基板に形成されているHBTを例にして説明した。本実施の形態2では、増幅回路が形成されている半導体チップも制御回路が形成されている半導体チップ27と同様にシリコンを主成分とし、HBTの代わりにLDMOSFET(Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor)が形成されている例について説明する。
sを主成分とする半導体チップに形成されたHBTから構成する場合にも適用できる。
前記実施の形態1では、配線基板26にキャビティと呼ばれる溝を形成せずに半導体チップ27を搭載する例について説明したが、本実施の形態3では、配線基板26にキャビティ96を形成し、このキャビティ96内に半導体チップ27を配置する例について説明する。
前記実施の形態1では、増幅回路が形成されている半導体チップ28で異なる周波数の信号を増幅できるように構成されていた。つまり、GSM方式の信号とDCS方式の信号を1つの半導体チップ28内に形成されたそれぞれの増幅回路で増幅できるように構成されていた(デュアルバンド方式)。本実施の形態4では、GSM方式の信号を増幅する増幅回路とDCS方式の信号を増幅する増幅回路が異なる半導体チップに形成されている例について説明する。
2 IF部
3 変調信号源
4 ミキサ
5 RFモジュール
6 アンテナスイッチ
7 アンテナ
8 低雑音増幅器
10 制御回路
11a〜11c 増幅部
12a〜12c 増幅部
13 入力端子
14 整合回路
15 HBT
16 整合回路
17 出力端子
18 電流源
19 バイアス抵抗
20 高周波閉塞用インダクタ
21 出力制御端子
22 電源電圧検出回路
23 電源電圧端子
25 RFモジュール
26 配線基板
27 半導体チップ(第2半導体チップ)
28 半導体チップ(第1半導体チップ)
29 受動部品
30 ボンディングパッド
31 ボンディングパッド
32 ワイヤ
32a ボール
32b ワイヤ
33a、33b 導電性接着材料
34a、34b ビア
35a、35b 配線
36 RFモジュール
37 中継パッド
38 ボンディングパッド
39a ワイヤ
39b ワイヤ
40a、40b 入力パッド
41a、41b 初段出力パッド
42a、42b 中段入力パッド
43a、43b 中段出力パッド
44a、44b 終段入力パッド
45a、45b 出力パッド
46a、46b 第1増幅部
47a、47b 第2増幅部
48a、48b 第3増幅部
50 HBT
51 サブコレクタ層
52 コレクタメサ
52a コレクタ電極
53 ベースメサ
54 エミッタ層
55 エミッタ電極
56 ベース電極
57 接続孔
58 エミッタ配線
58a 金配線
58b 金配線
59 ベース配線
60 コレクタ配線
61 GaAs基板
62 裏面電極
63 絶縁膜
64 表面保護膜
65 ポリイミド樹脂膜
66 キャピラリ
67 破線
68 表面保護膜
71 半導体基板
72 エピタキシャル層
73 溝
74 p型打ち抜き層
75 p型ウェル
76 ゲート絶縁膜
77 ゲート電極
78 キャップ絶縁膜
79 n−型オフセットドレイン領域
80 n−型ソース領域
81 p型ハロー領域
82 サイドウォール
83 n型オフセットドレイン領域
84 n+型ドレイン領域
85 n+型ソース領域
86 p+型半導体領域
87 窒化シリコン膜
88 酸化シリコン膜
89 コンタクトホール
90 プラグ
91 第1層配線
92 酸化シリコン膜
93 接続孔
94 プラグ
95 第2層配線
96 キャビティ
97 半導体チップ
98 半導体チップ
99a ボンディングパッド
99b ボンディングパッド
100 GSM用第1増幅部
101 DCS用第1増幅部
Claims (11)
- (a)入力信号を増幅して出力信号を生成する増幅回路が形成された第1半導体チップと、
(b)前記増幅回路を制御する制御回路が形成された第2半導体チップと、
(c)前記第1半導体チップと前記第2半導体チップとを隣接して配置する配線基板とを備え、
前記第1半導体チップと前記第2半導体チップとはワイヤを用いて電気的に接続されており、前記ワイヤは、中継パッドを介さずに前記第1半導体チップと前記第2半導体チップとを直接接続しており、
前記第1半導体チップに形成されている複数のパッドのうち前記第2半導体チップと接続する制御用パッドは、前記第1半導体チップの1辺に沿って配列され、
前記第1半導体チップに形成されている複数のパッドのうち前記入力信号を入力する入力パッドは、前記制御用パッドが形成されている辺と交差する辺に形成されていることを特徴とする半導体装置。 - (a)入力信号を増幅して出力信号を生成する増幅回路が形成された第1半導体チップと、
(b)前記増幅回路を制御する制御回路が形成された第2半導体チップと、
(c)前記第1半導体チップと前記第2半導体チップとを隣接して配置する配線基板とを備え、
前記第1半導体チップと前記第2半導体チップとはワイヤを用いて電気的に接続されており、前記ワイヤは、中継パッドを介さずに前記第1半導体チップと前記第2半導体チップとを直接接続しており、
前記第1半導体チップに形成されている複数のパッドのうち前記第2半導体チップと接続する制御用パッドは、前記第1半導体チップの1辺に沿って配列され、
前記第1半導体チップに形成されている複数のパッドのうち前記出力信号を出力する出力パッドは、前記制御用パッドが形成されている辺と対向する辺に形成されていることを特徴とする半導体装置。 - (a)入力信号を増幅して出力信号を生成する増幅回路が形成された第1半導体チップと、
(b)前記増幅回路を制御する制御回路が形成された第2半導体チップと、
(c)前記第1半導体チップと前記第2半導体チップとを隣接して配置する配線基板とを備え、
前記第1半導体チップと前記第2半導体チップとはワイヤを用いて電気的に接続されており、前記ワイヤは、中継パッドを介さずに前記第1半導体チップと前記第2半導体チップとを直接接続しており、
前記第1半導体チップに形成されている複数のパッドのうち前記第2半導体チップと接続する制御用パッドは、前記第1半導体チップの1辺に沿って配列され、
前記制御用パッドは、矩形形状をしていることを特徴とする半導体装置。 - 前記増幅回路は、前記入力信号を増幅する第1増幅部と、前記第1増幅部で増幅された信号を増幅する第2増幅部と、前記第2増幅部で増幅された信号を増幅して前記出力信号を生成する第3増幅部とを有することを特徴とする請求項1記載の半導体装置。
- 前記第3増幅部は、前記第1増幅部および前記第2増幅部よりも前記第1半導体チップの中央側に配置され、前記第1増幅部および前記第2増幅部は、前記第3増幅部よりも前記入力パッドに近い位置へ配置されていることを特徴とする請求項4記載の半導体装置。
- 前記第1半導体チップは、前記入力パッドと、前記入力パッドから入力した前記入力信号を前記第1増幅部で増幅して出力する初段出力パッドと、前記初段出力パッドから出力した信号を前記第2増幅部へ入力する中段入力パッドと、前記中段入力パッドから入力した信号を前記第2増幅部で増幅して出力する中段出力パッドと、前記中段出力パッドから出力した信号を前記第3増幅部へ入力する終段入力パッドと、前記終段入力パッドから入力した信号を前記第3増幅部で増幅して前記出力信号を出力する出力パッドとを有し、
前記入力パッド、前記初段出力パッド、前記中段入力パッド、前記中段出力パッドおよび前記終段入力パッドは、この順番で、前記制御用パッドが形成されている辺と交差する辺に配列されていることを特徴とする請求項4記載の半導体装置。 - 前記出力パッドは、前記制御用パッドが形成されている辺と対向する辺に配列されていることを特徴とする請求項6記載の半導体装置。
- 前記増幅回路は、周波数帯の異なる複数の入力信号をそれぞれ増幅することを特徴とする請求項1記載の半導体装置。
- 前記第1半導体チップは、化合物半導体を主成分とし、前記第2半導体チップは、シリコンを主成分とすることを特徴とする請求項1記載の半導体装置。
- 前記増幅回路は、前記入力信号を増幅する第1増幅部と、前記第1増幅部で増幅された信号を増幅する第2増幅部と、前記第2増幅部で増幅された信号を増幅して前記出力信号を生成する第3増幅部とを有することを特徴とする請求項2記載の半導体装置。
- 前記増幅回路は、周波数帯の異なる複数の入力信号をそれぞれ増幅することを特徴とする請求項2記載の半導体装置。
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