JPS5854646A - 混成集積回路装置 - Google Patents

混成集積回路装置

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Publication number
JPS5854646A
JPS5854646A JP56154356A JP15435681A JPS5854646A JP S5854646 A JPS5854646 A JP S5854646A JP 56154356 A JP56154356 A JP 56154356A JP 15435681 A JP15435681 A JP 15435681A JP S5854646 A JPS5854646 A JP S5854646A
Authority
JP
Japan
Prior art keywords
semiconductor chip
integrated circuit
circuit device
hybrid integrated
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56154356A
Other languages
English (en)
Inventor
Naoharu Senba
仙波　直治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56154356A priority Critical patent/JPS5854646A/ja
Publication of JPS5854646A publication Critical patent/JPS5854646A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は複数の半導体チップを搭載する混成集積回路装
置に関し、特にそれら半導体チップ間の接続構造に関す
るものである。
従来のかかる混成集積回路装置は、第１図にその断面図
に示すように、基板４に回路を構成する導体５を設け、
その上に半導体チップ１およびｚを接着し、半導体チッ
プ１＃２の間にこれらの接続の九めの接続用中継導体６
ｔ−設け、そして接続用細線３を用いてワイヤーボンデ
ィング法等により接続した構造となっている。
しかしながら、この様な構造では、高集積化および極小
化が要求されている現代、これに対応する手段として多
層化があるが半導体チップ１−２間に接続用の中継導体
６は必要であり、この中継点に賛する面積空間Ａは減少
し１い、従って、高集積化および極小化も限界がある。
そこで、半導体チップ１および２ｔ−直接ワイヤポンデ
ィンダすれば、面積空間Ａはより縮小され得る。しかし
ながら、例えばまずチップｌにボンディング線の接着し
、次にチップ２に接着した場合、チップ２上のポンディ
ングパッドに近接する配線導体や半導体チップ２の基板
エッヂ部にボンディング線が接融してしまうことがある
。このように、従来構造では、短線接触なしに高集積化
、極小化は困難である。
、本発明の目的は、従来構造の無駄な面積五を小さくシ
、且つワイヤー接続点数を半減させることにより、更に
高集積化、小屋化を可能にした混成集積回路装置を提供
することにある。
すなわち、本発明はチップ間のボンディング線による直
接接続を可能にし友もので、以下、図面に基づき詳細に
゛説明する。
第２図は本発明による混成集積回路装置の一実施例を示
す図であり、半導体チップ１と半導体チ、プ２’を直接
ワイヤーボンディング法により接続するため、半導体チ
ップ２上のポンディングパッド電極７を拡大している。
従って、ワイヤーボンディングにより直接接続しても、
近接する配線との短絡や基板エッヂ部との接触は防止さ
れる。
また、短絡接触防止は、第３図のように、チップ２上の
ポンディングパッドの近傍にスタートパッド（即ち、チ
ップ１）方向に導電性あるいは絶縁性のバンブ８を設け
ることによって、前述したように近接するボンディング
ワイヤーによる不具合を防止し、直接ワイヤーボンディ
ング法を可能にできる。
さらに、第４図のように、半導体チップ１と牛導体チ、
プ２間に少くとも半導体チップよりも高さの高い絶縁性
の土手９を設けても直接ワイヤーボンディング法が可能
となる。
第５図は半導体チップ１−２間に於いて、少くともセカ
ンドポンド側の半導体チップ２がスタートパッド儒の半
導体チップｌよりも高さＩＨだけ低くなっている。この
几め、前述したように近接するボンディングワイヤーに
よる不具合を防止し、直接ワイヤーボンディングが可能
になる。
本発明は以上説明したように、半導体チップ−半導体チ
ップ間の直接ワイヤーボンディング法および、これ管可
能にするための構造を提供することにより、混成集積回
路装置の高集積化、小型化が進むなかで非常に効果があ
る。
【図面の簡単な説明】
第１図は従来の混成集積回路装置を示す断面図である。 第２図〜第５図はそれぞれ本発明の実施例管示す断面図
である。 １・・・・・・半導体チップ、２・・・・・・半導体チ
ップ、３・・・・・・接続用細線、４・・・・・・基板
、５・・・・・・回路構成導体、６・・・・・・接続用
中継導体、７・・・・・・ボンディングバット電極、８
・・・・・・導電性、絶縁性バンプ、９・・・・・・絶
縁性の土手、入・・・・・・半導体チップ〜半導体チッ
プ間隔１Ｈ・・・・・・チップ高さ。

Claims (5)

    【特許請求の範囲】
  1. （１）少なくとも二つの半導体チップカニ搭載された混
    成集積回路装置において、それら半導体チ。 プ間が金属細線により直接接続されていることｔ−特徴
    とする混成集積回路装置。
  2. （２）上記金属細線は、一方の半導体チップ上の電極か
    ら他方の半導体チップ上の電極へ接続されており、前記
    他方の半導体チップ上の電極は前記一方の半導体チップ
    上の電極より大きくなされていることを特徴とする特許
    請求の範囲第１項記載の混成集積回路装置。
  3. （３）上記金属細線は、一方の半導体チップから他方の
    半導体チップへ他方の半導体チップ上に設けられた導電
    性又は絶縁性ノ（ンプ上を経て接続されていること′を
    特徴とする特許請求の範囲第１項記載の混成集積回路装
    置。
  4. （４）　　上記金属細線は、一方の半導体チップから他
    方の半導体チップへそれら二つの半導体チップよりも高
    い絶縁性の土手上を経て接続されていることｔ−特徴と
    する特許請求の範囲第１項記載の混成集積回路装置。
  5. （５）　　上記金属細線は、一方の半導体チップからそ
    の半導体チップよりも一段下がった他方の半導体チップ
    へ接続されていることを特徴とする特許請求の範囲路１
    項記載の混成集積回路装置。
JP56154356A 1981-09-29 1981-09-29 混成集積回路装置 Pending JPS5854646A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56154356A JPS5854646A (ja) 1981-09-29 1981-09-29 混成集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56154356A JPS5854646A (ja) 1981-09-29 1981-09-29 混成集積回路装置

Publications (1)

Publication Number Publication Date
JPS5854646A true JPS5854646A (ja) 1983-03-31

Family

ID=15582363

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56154356A Pending JPS5854646A (ja) 1981-09-29 1981-09-29 混成集積回路装置

Country Status (1)

Country Link
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6230343A (ja) * 1985-07-31 1987-02-09 Nec Corp 半導体装置
US6208018B1 (en) 1997-05-29 2001-03-27 Micron Technology, Inc. Piggyback multiple dice assembly
US6682954B1 (en) * 1996-05-29 2004-01-27 Micron Technology, Inc. Method for employing piggyback multiple die #3
JP2007220790A (ja) * 2006-02-15 2007-08-30 Renesas Technology Corp 半導体装置およびその製造方法
WO2014166547A1 (en) * 2013-04-12 2014-10-16 Osram Opto Semiconductors Gmbh Electronic device and method for producing an electronic device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5011655A (ja) * 1973-06-01 1975-02-06
JPS5310268B2 (ja) * 1974-09-20 1978-04-12
JPS5461471A (en) * 1977-10-25 1979-05-17 Nec Corp Semiconductor device
JPS54112167A (en) * 1978-02-22 1979-09-01 Nec Corp Manufacture of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5011655A (ja) * 1973-06-01 1975-02-06
JPS5310268B2 (ja) * 1974-09-20 1978-04-12
JPS5461471A (en) * 1977-10-25 1979-05-17 Nec Corp Semiconductor device
JPS54112167A (en) * 1978-02-22 1979-09-01 Nec Corp Manufacture of semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6230343A (ja) * 1985-07-31 1987-02-09 Nec Corp 半導体装置
US6682954B1 (en) * 1996-05-29 2004-01-27 Micron Technology, Inc. Method for employing piggyback multiple die #3
US6208018B1 (en) 1997-05-29 2001-03-27 Micron Technology, Inc. Piggyback multiple dice assembly
JP2007220790A (ja) * 2006-02-15 2007-08-30 Renesas Technology Corp 半導体装置およびその製造方法
WO2014166547A1 (en) * 2013-04-12 2014-10-16 Osram Opto Semiconductors Gmbh Electronic device and method for producing an electronic device

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