JPS54112167A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS54112167A
JPS54112167A JP2008678A JP2008678A JPS54112167A JP S54112167 A JPS54112167 A JP S54112167A JP 2008678 A JP2008678 A JP 2008678A JP 2008678 A JP2008678 A JP 2008678A JP S54112167 A JPS54112167 A JP S54112167A
Authority
JP
Japan
Prior art keywords
chip
insulator
flank
circumferential
fixed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008678A
Other languages
Japanese (ja)
Inventor
Jiro Suma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2008678A priority Critical patent/JPS54112167A/en
Publication of JPS54112167A publication Critical patent/JPS54112167A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To prevent a short from occurring owing to the contact between a chip and a bonding wire by covering the circumferential prat and flank of a chip fixed to a holder with an insulator when bonding a metal wire to a semiconductor chip.
CONSTITUTION: Semiconductor chip 13 is fixed to island part 11 of a base ribbon and the circumferential part and flank of chip 13 are coated with insulator 15 of epoxy resin or polyamide. Then, lead 12 and chip 13 positioned near island part 11 are connected together via bonding wire 14. To form the insulator on the chip, chip 23 with bonding pad 26 formed is fixed onto island part 21 of the base ribbon with lead 22 and square case 25 made of resin such as epoxy is arranged surrounding a heat treatment, thereby producing insulator layers at the circumferential part and chip 23. Square case 25 is softened and made diquid through flank of chip 23.
COPYRIGHT: (C)1979,JPO&Japio
JP2008678A 1978-02-22 1978-02-22 Manufacture of semiconductor device Pending JPS54112167A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008678A JPS54112167A (en) 1978-02-22 1978-02-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008678A JPS54112167A (en) 1978-02-22 1978-02-22 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS54112167A true JPS54112167A (en) 1979-09-01

Family

ID=12017285

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008678A Pending JPS54112167A (en) 1978-02-22 1978-02-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS54112167A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57196537A (en) * 1981-05-28 1982-12-02 Nec Home Electronics Ltd Manufacture of semiconductor device
JPS5854646A (en) * 1981-09-29 1983-03-31 Nec Corp Hybrid integrated circuit device
JPH022835U (en) * 1988-06-20 1990-01-10

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57196537A (en) * 1981-05-28 1982-12-02 Nec Home Electronics Ltd Manufacture of semiconductor device
JPS5854646A (en) * 1981-09-29 1983-03-31 Nec Corp Hybrid integrated circuit device
JPH022835U (en) * 1988-06-20 1990-01-10

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