JPS6231132A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6231132A
JPS6231132A JP60170712A JP17071285A JPS6231132A JP S6231132 A JPS6231132 A JP S6231132A JP 60170712 A JP60170712 A JP 60170712A JP 17071285 A JP17071285 A JP 17071285A JP S6231132 A JPS6231132 A JP S6231132A
Authority
JP
Japan
Prior art keywords
reference potential
pad
metal wire
semiconductor chip
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60170712A
Other languages
English (en)
Inventor
Shigeru Kagiyama
鍵山　滋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60170712A priority Critical patent/JPS6231132A/ja
Publication of JPS6231132A publication Critical patent/JPS6231132A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関する。
〔従来の技術〕
通常、半導体装置は回路素子を形成した半導体チップと
それを搭載するパッケージとからなる。
第３図は従来の半導体装置の一例の平面図、第４図は第
３図に示す半導体装置の部分断面図であるＯ このパッケージは外部リードが一層であシ、このリード
とつながる半導体チップ上の引出し電極パッドとがＡＩ
！、Ａｕ等の金塊線でボンディングされている。前記半
導体チップの電源、接地につながる導体層は電源電流値
に応じて幅広くなっていることもある。
〔発明が解決しようとする問題点〕
半導体装置１個に要求される機能が増せば増すほど、そ
れに応じて半導体チップの大きさも大きくなるがその際
、回路の安定した動作をする上で重要視されているのが
電源系の配線である。例えば、ゲートアレイと呼ばれる
半導体装置では、ユーザ自身が回路を設計し、コンピュ
ータ処理でチップ上での論理ブロック配置を決定するた
め、論理動作上基準電位のマージンが十分とれないブロ
ックが基準電位引出しパッドから遠い位置に配置される
ことがあシ、チップ内基準電位抵抗が大きくなり、パッ
ド電位基準が変動し、論理回路の電圧マージンが小さく
なシ、誤動作をするという場合がある。
又、ＴＴＬ（Ｔｒａｎｓｉｓｔｏｒ　Ｔｒａｎａｉａｔ
ｏｒしたときに接地レベルが上昇して、その分だけ論理
動作の入力、電源電圧のマージンが少なくなシ所定の動
作を果さないことがあシ、基準電位となるパッド電位を
一定にするために基準電位点接続パッドを多く出すこと
が必要になってくる。
ゲートアレイの場合、１つのチップで複数のパッケージ
に対応できるよう、予めパッドは多めに設けられている
ので余剰のパッドを基準電位点接続パッドとして使用す
ることは可能である。しかし、従来のパッケージにおい
ては外部リードとつながる導体リード数は限られている
から入出力信号系を有効に使っても、基準電位点引出し
用には必要最小限しか割当てられない。そのため、チッ
プ側で基準電位点引出しパッドを増してもそれを生かし
きれず、結果として前述のような不具合を生じる欠点が
あった。
本発明の目的は半導体チップの基準電位パッドと導体リ
ードを最短距離で結び、基準電位電圧が変動することな
く、回路が安定に働く半導体装置を提供することにある
。
〔問題点を解決するための手段〕
本発明の半導体装置は、外部リードとつながる導体層が
複数層でかつ絶縁体層で互いに絶縁された多層構造であ
るパッケージと、前記パッケージ内に搭載されボンディ
ングパッドが金属線で前記半導体層に接続される半導体
チップと葡有する半導体装置において、前記複数層の導
を体層のうちの少なくとも一層が前記半導体チップを囲
んで形成されかつ基準電位リードに接続されて構成され
るＯ 〔実施例〕 次に、本発明の実施例について図面を用いて説明する。
第１図は本発明の一実施例の平面図、第２図は第１図に
示す実施例の部分断面図である。
パッケージ３は外部リード４とつながる複数の導体層５
，７が絶縁体層９で互いに絶縁された構造になっていて
、導体層のうち少なくとも一層、この実施例では導体層
７が半導体チップ２のマウント用アイランドを囲んで設
けられている。導体層７が外部リード４のうちの基準電
位リードに接続され、このパッケージに搭載された半導
体チップの基準電位パッド６から最短距離で導体層７に
金属線でボンディングされている。信号線は半導体チッ
プのパッド２から導体層５へ金属線でボンディングされ
ている。
このような構造にすると、基準電位パッド６から導体層
７へ最短距離で接続されるから金属線８の抵抗値を小さ
くすることができ、従って、金属線８による電位降下も
小さくなシ、基準電位パッド６の電位が安定する。これ
によシ入力電源電圧の電圧マージンも確保され、誤動作
がなくなる。
また、半導体チップｌＫ設けられる基準電位引出し用の
パッドの数を増すことができ、半導体チップｌ内での電
位降下も低減することができる。
〔発明の効果〕
以上説明したように、本発明によれば、半導体チップの
基準電位点接続用の金属線を短くでき、インピーダンス
が減り、基準電位パッドの電位が安定する半導体装置が
得られるという効果が得られる。
【図面の簡単な説明】
第１図は本発明の一実施例の平面図、第２図は第１図に
示す実施例の部分断面図、第３図は従来の半導体装置の
一例の平面図、第４図は第３図に示す半導体装置の部分
断面図である。 ｌ・・・・・・半導体チップ、２・・・・・・パッド、
３・・・・・・パッケージ、４・・・・・・外部リード
、５・・・・・・導体層、６・・・・・・基準を位パッ
ド、７・・・・・・導体層、８・・・・・・金属線、９
・・・・・・絶縁体。 、／−’　−８ 代理人　弁理士　　内　原　　　晋１′’　　　、＋、
）第２　図 第４　＠

Claims (1)

    【特許請求の範囲】
  1. 外部リードとつながる導体層が複数層でかつ絶縁体層で
    互いに絶縁された多層構造であるパッケージと、前記パ
    ッケージ内に搭載されボンディングパッドが金属線で前
    記導体層に接続される半導体チップとを有する半導体装
    置において、前記複数層の導電体層のうちの少なくとも
    一層が前記半導体チップを囲んで形成されかつ基準電位
    リードに接続されていることを特徴とする半導体装置。
JP60170712A 1985-08-02 1985-08-02 半導体装置 Pending JPS6231132A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60170712A JPS6231132A (ja) 1985-08-02 1985-08-02 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60170712A JPS6231132A (ja) 1985-08-02 1985-08-02 半導体装置

Publications (1)

Publication Number Publication Date
JPS6231132A true JPS6231132A (ja) 1987-02-10

Family

ID=15909999

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60170712A Pending JPS6231132A (ja) 1985-08-02 1985-08-02 半導体装置

Country Status (1)

Country Link
JP (1) JPS6231132A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63197350A (ja) * 1987-02-12 1988-08-16 Nec Ic Microcomput Syst Ltd 半導体集積回路装置
JPH01111342A (ja) * 1987-10-26 1989-04-28 Nec Corp 集積回路用パッケージ
US5818102A (en) * 1995-12-29 1998-10-06 Lsi Logic Corporation System having integrated circuit package with lead frame having internal power and ground busses

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63197350A (ja) * 1987-02-12 1988-08-16 Nec Ic Microcomput Syst Ltd 半導体集積回路装置
JPH01111342A (ja) * 1987-10-26 1989-04-28 Nec Corp 集積回路用パッケージ
US5818102A (en) * 1995-12-29 1998-10-06 Lsi Logic Corporation System having integrated circuit package with lead frame having internal power and ground busses

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