CN102822965B - 具有内嵌式裸片的集成电路封装中的热通孔 - Google Patents

具有内嵌式裸片的集成电路封装中的热通孔 Download PDF

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CN102822965B
CN102822965B CN201180014511.3A CN201180014511A CN102822965B CN 102822965 B CN102822965 B CN 102822965B CN 201180014511 A CN201180014511 A CN 201180014511A CN 102822965 B CN102822965 B CN 102822965B
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nude film
hole
package
heat
substrate
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CN102822965A (zh
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菲芬·斯威尼
米林德·P·沙阿
马里奥·弗朗西斯科·韦莱兹
达米翁·B·加斯特卢姆
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Qualcomm Inc
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Abstract

在具有封装衬底和封装触点的多模块集成电路封装中，将裸片内嵌在所述封装衬底中，其中热通孔将所述经内嵌裸片上的热点耦合到所述封装触点中的一些封装触点。

Description

具有内嵌式裸片的集成电路封装中的热通孔
技术领域
本发明涉及集成电路封装，且更特定来说涉及从集成电路封装移除热量。
背景技术
在电子系统级封装(或封装中封装)技术中，单一封装包括一个或一个以上裸片，其中这些裸片中的一者或一者以上处于其自身的个别封装中。图1中提供一实例。图1是倒装芯片堆叠模块封装的简化平面图(未按比例绘制的)图示。裸片102经倒装，其有源侧面对着封装衬底104。在倒装芯片工艺(也正式称为受控塌陷芯片连接(C4)蒸发凸块工艺)中，导电凸块(106)经形成且焊接到裸片102的有源侧上的衬垫。焊料凸起裸片102接着面朝下放置到封装衬底104上的匹配接合衬垫上，所述封装衬底104可为多层有机衬底。组合件经回流使得导电凸块106焊接到封装衬底104上的衬垫以便提供裸片102的有源侧与封装衬底104之间的电连接。导电凸块106还提供裸片102与封装衬底104之间的负载承载链路。通常，导电凸块包括焊料。封装衬底104包含电互连件，使得导电凸块106电连接到多个封装触点108中的至少一些。
封装110附接到裸片102的背侧。其为线接合封装，其中裸片102附接到封装衬底114，且借助从裸片112的有源侧到封装衬底114上的衬垫的线接合来提供电连接。作为一实例，展示一个此类线接合，标记为116。来自衬底封装114的外侧上的衬垫的线接合提供了到封装衬底104的电连接。举例来说，展示一个此类线接合，标记为118。裸片120附接到封装110，所述裸片120线接合到封装衬底104。举例来说，展示一个此类线接合，标记为122。
通常应用环氧树脂(有时称为底部填料)来帮助补偿裸片102与封装衬底104之间的热膨胀系数(CTE)的差异，且防止湿气破坏。组合件还可用液态环氧树脂封端以进行进一步保护，从而产生最终的系统级封装124。
对于一些应用，裸片102可包括数字逻辑电路，封装110可为存储器模块，且裸片120可包括模拟电路。
随着系统级封装技术领域中发生越来越多的集成，热管理可能提出一个挑战。常规热管理包含封装衬底104中的热通孔，以及散热器的使用。然而，为使热量从裸片120逸出到封装触点108，热量从裸片120流动经过封装110中的各种材料、倒装裸片102、底部填料和封装衬底104，且经过封装触点108，之后逸出系统级封装124。将需要提供具有供热量逸出的有效热路径的系统级封装技术。
发明内容
在一实施例中，将裸片内嵌在封装衬底中。封装衬底具有封装触点。封装衬底中的热通孔将裸片耦合到封装触点中的至少一些。热通孔中的至少一者具有与至少两个重叠圆形的联合大体类似的横截面形状。
在另一实施例中，孔形成在封装衬底芯中，其中封装衬底芯具有拥有第一金属层的第一侧和拥有第二金属层的第二侧。将胶带放置在封装衬底芯的第二侧上。接着将裸片放置到孔中，所述裸片具有第一侧和与胶带邻近的第二侧。衬底形成在裸片的第一侧、第一金属层和封装衬底芯的第一侧上。热通孔形成在衬底中以在裸片的热点处耦合到裸片的第一侧。
在另一实施例中，孔形成在封装衬底芯中，其中封装衬底芯具有拥有第一金属层的第一侧和拥有第二金属层的第二侧。将胶带放置在封装衬底芯的第二侧上。将裸片放置到孔中，其中所述裸片具有第一侧和与胶带邻近的第二侧。第一衬底形成在裸片的第一侧、第一金属层和封装衬底芯的第一侧上。移除胶带。第二衬底形成在裸片的第二侧、第二金属层和封装衬底芯的第二侧上。热通孔形成在第二衬底中以在裸片的热点处耦合到裸片的第二侧。
附图说明
图1是常规多模块集成电路封装的平面图。
图2A和2B说明具有内嵌式裸片和热通孔的集成电路封装。
图3是具有内嵌式裸片和热通孔的集成电路封装的一部分的平面图。
图4是说明用于将裸片内嵌在具有热通孔的集成电路封装衬底中的程序的平面图。
图5说明覆盖热点的热通孔的横截面平面图。
具体实施方式
在以下描述中，术语“一些实施例”的范围不应限于表示一个以上实施例，而是所述范围可包含一个实施例、一个以上实施例，或可能所有实施例。
图2A说明系统级封装200的简化平面图(未按比例绘制)，其中裸片202内嵌在封装衬底208内。如图1中，系统级封装200包括倒装裸片102，以及处于其自身封装110中的裸片112。在图2A的特定实施例中，裸片202的有源侧背对封装衬底208的连接到封装触点108的一侧。图2A中展示裸片202的有源侧上的镀铜(或触点)，其中镀铜的一个此类实例标记为204。尽管未明确展示，但镀铜204电连接到封装衬底208中的迹线以便电连接到封装触点108中的至少一些。
在图2A的图示中，封装衬底208中的热通孔耦合到裸片202的背侧且耦合到封装触点108中的至少一些，使得有效热路径可提供在裸片202与封装触点108中的一些之间。一个此类热通孔标记为206。热通孔可包括例如铜，使得其也可为导电的。
对于并非定位在封装触点的正上方的热通孔，迹线可形成在封装衬底内以使得到封装触点中的一者的热路径得以继续。此在图2B中说明，其中迹线210提供从热通孔206到封装触点108的传导热路径，其中假定不存在定位在热通孔206正下方的封装触点。图2B中说明的视图的定向垂直于图2A中说明的视图，其中图2B说明沿着裸片202的平行于封装衬底208的面的实施例的切片。为便于说明，图2B未按比例绘制，且未遵循图2A的图示的比例。在图2B中，虚线202表示图2A中的裸片202的轮廓，且虚线208表示图2A中的封装衬底208的轮廓。这些轮廓用虚线表示以指示其位于提供图2B的视图的穿过裸片202的切片的上方和下方。
对于一些实施例，裸片202可内嵌在封装衬底208中以使得其有源侧面对着封装衬底208的附接到封装触点108的一侧。对于此类实施例，热通孔中的一些除了提供热路径外还可对裸片202的有源侧上的有源组件中的一些提供到封装触点108中的一者或一者以上的电连接。
图3是具有内嵌式裸片202的封装衬底208的一部分的平面图(未按比例绘制)，但比图2A的图示更详细。图3的封装衬底经展示为多层，包括金属层302、衬底304、金属层306、芯308、金属层310、衬底312和金属层314。所述金属层可包括铜。各种材料和层压物可用于衬底和芯。芯308可包括与用于衬底的材料相同的材料。对于一些实施例，FR-4(阻燃剂4)可用于芯308或衬底，或者可使用例如聚酰亚胺。
图3中说明的平面图是简化的，因为其不展示金属层中的开口(到裸片202的开口除外)。即，所述图示在金属层的平面图(其是垂直于图示中的视图的方向的方向上的实施例的切片)将金属层展示为矩形的意义上是简化的。实践中，对金属层执行蚀刻以使得可形成到各种组件的电连接。
裸片202的背侧上的镀铜将各个热点以热学方式耦合到热通孔206。镀铜的一个此类实例在图3中标记为316。对于一些实施例，可对裸片202执行热分析以使得镀铜316沉积在热点上，或在热点中的至少一些处。此允许对热管理的精细调谐。
对于一些实施例，裸片202的有源侧可面对金属层306，在此情况下一些镀铜316可提供到有源侧上的各个装置的电连接以及热耦合。对于其中有源侧面对着金属层306的此类实施例，如标记204表示的镀铜可能不是必需的。
图4展示说明用于将裸片202内嵌到芯308中的程序的各个平面图(未按比例绘制)，其中程序次序由字母A到E指示。以处于A的芯308开始，向B中的芯308中钻凿孔。在B中，金属层306和310已沉积在芯308的两侧上，且已对这些金属层执行蚀刻以提供迹线。在C中，胶带402附接到芯308的底部，且在D中，裸片202下落到芯308中钻凿的孔中。裸片202包含镀铜204和316。衬底312(例如，FR-4)层压在组合件的顶部上。此衬底材料由交叉线指示。在E中，胶带402已移除，且衬底304层压在底部上(再次以交叉线表示)。热通孔206形成到衬底304中以形成与镀铜316的接触。
为便于说明，先前图式将热通孔206说明为沿着裸片202的底面均匀地定位，但在实践中，因为热通孔206耦合到裸片202上的热点，所以热通孔206的定位可能不是均匀的。并且，因为热通孔206集中在各个热点周围，所以关于功率或信号通孔的情况，热通孔206中的一些的形状并不预期为大体圆柱形的。热通孔206中的一些可为彼此重叠的两个或两个以上圆柱形的联合。
图5说明包括多个个别通孔的热通孔的横截面平面图(不一定按比例绘制)。所述横截面图是平行于裸片202的底面且大体垂直于热通孔206而截取的切片。热通孔将覆盖的经测量热点的横截面平面图是由具有标记为502的轮廓的不规则形状说明。热通孔的形状是由若干重叠的圆柱形形状的联合形成，所述圆柱形形状在图示中呈现为圆形。这些圆形的联合的外包络说明为具有标记504的实线。并非包络的部分的圆形的部分以虚线说明。
在图5的图示中，热通孔不完全覆盖热点502，但对于一些实施例，热通孔的形状可通过形成较多圆形的联合以便完全覆盖热点来合成。在实践中，不能实现完美的圆形，使得热通孔的横截面形状仅可大体类似于由重叠的圆形的联合形成的几何形状。
可对所描述的实施例作出各种修改而不脱离如所主张的本发明的范围。举例来说，在图4的E中，热通孔可形成在衬底312中而非衬底304中。即，在移除胶带402之前施加的衬底312可含有热通孔。

Claims (17)

1.一种集成电路封装，其包括：
封装衬底，其包括多个封装触点；
裸片，其内嵌在所述封装衬底中；以及
所述封装衬底中的多个热通孔，其在所述裸片的热点处耦合到所述裸片，并将所述裸片的所述热点耦合到所述多个封装触点中的至少一者，其中属于所述多个热通孔的热通孔具有与至少两个重叠圆形的联合类似的横截面形状，以覆盖属于所述裸片上的所述热点的热点。
2.根据权利要求1所述的集成电路封装，所述裸片具有有源侧和背侧，其中所述多个热通孔耦合到所述裸片的所述背侧，并提供所述裸片上的所述热点和所述多个封装触点中的所述至少一者之间的热路径。
3.根据权利要求2所述的集成电路封装，其进一步包括在所述裸片的所述热点处沉积在所述裸片的所述背侧的镀铜，其中所述镀铜将所述裸片上的所述热点热耦合到所述多个热通孔。
4.根据权利要求1所述的集成电路封装，所述封装衬底具有第一面和第二面，其中所述第一面与所述多个封装触点接触，所述集成电路封装进一步包括耦合到所述第二面的倒装裸片。
5.根据权利要求1所述的集成电路封装，所述封装衬底包括第一衬底、芯和第二衬底，其中所述裸片内嵌在所述芯中。
6.根据权利要求5所述的集成电路封装，其中所述多个热通孔仅内嵌在所述第一衬底中。
7.根据权利要求5所述的集成电路封装，所述封装衬底进一步包括与所述多个封装触点和所述第一衬底接触的金属层。
8.根据权利要求7所述的集成电路封装，其中所述多个热通孔与所述金属层的至少一部分接触。
9.根据权利要求8所述的集成电路封装，其进一步包括与所述多个热通孔接触，并在所述裸片上的热点处沉积在所述裸片上的镀铜，其中所述镀铜将所述裸片上的所述热点热耦合到所述多个热通孔，并在所述裸片的有源侧上提供到一个或多个装置的电连接。
10.根据权利要求1所述的集成电路封装，其中所述多个热通孔是导电的。
11.一种用于将裸片嵌入封装衬底的方法，其包括：
在封装衬底芯中形成孔，所述封装衬底芯具有拥有第一金属层的第一侧和拥有第二金属层的第二侧；
将胶带放置在所述封装衬底芯的所述第二侧上；
将裸片放置到所述孔中，所述裸片具有第一侧和与所述胶带邻近的第二侧；
在所述裸片的所述第一侧、所述第一金属层和所述封装衬底芯的所述第一侧上形成第一衬底；以及
在所述第一衬底中形成热通孔以在所述裸片的热点处耦合到所述裸片的所述第一侧，其中所述热通孔具有与至少两个重叠圆形的联合类似的横截面形状，以覆盖属于所述裸片上的所述热点的热点。
12.根据权利要求11所述的方法，其进一步包括：
移除所述胶带；以及
在所述裸片的所述第二侧、所述第二金属层和所述封装衬底芯上形成第二衬底。
13.根据权利要求12所述的方法，所述裸片包括所述裸片的所述第一侧上的镀铜，其中所述热通孔与所述裸片的所述第一侧上的所述镀铜接触。
14.根据权利要求11所述的方法，其中所述裸片的所述第二侧为有源侧。
15.一种用于将裸片嵌入封装衬底的方法，其包括：
在封装衬底芯中形成孔，所述封装衬底芯具有拥有第一金属层的第一侧和拥有第二金属层的第二侧；
将胶带放置在所述封装衬底芯的所述第二侧上；
将裸片放置到所述孔中，所述裸片具有第一侧和与所述胶带邻近的第二侧；
在所述裸片的所述第一侧、所述第一金属层和所述封装衬底芯的所述第一侧上形成第一衬底；
移除所述胶带；
在所述裸片的所述第二侧、所述第二金属层和所述封装衬底芯的所述第二侧上形成第二衬底；以及
在所述第二衬底中形成热通孔以在所述裸片的热点处耦合到所述裸片的所述第二侧，其中所述热通孔具有与至少两个重叠圆形的联合类似的横截面形状，以覆盖属于所述裸片上的所述热点的热点。
16.根据权利要求15所述的方法，所述裸片包括所述裸片的所述第二侧上的镀铜，其中所述热通孔与所述裸片的所述第二侧上的所述镀铜接触。
17.根据权利要求15所述的方法，其中所述裸片的所述第一侧为有源侧。
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CN102822965A (zh) 2012-12-12
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