CN101609830A - 包括嵌入其中的电子部件的印刷电路板及其制造方法 - Google Patents
包括嵌入其中的电子部件的印刷电路板及其制造方法 Download PDFInfo
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Abstract
本发明涉及一种包括嵌入其中的电子部件的印刷电路板及其制造方法,本发明使用连接部将电子部件的电极端子电连接至内部电路层,从而使电路装配密度分散。
Description
相关申请交叉参考
本申请要求于2008年6月16日提交的题为“PRINTED CIRCUITBOARD WITH ELECTRONIC COMPONENTS EMBEDDED THEREINAND METHOD FOR FABRICATING THE SAME”的第10-2008-0056487号韩国专利申请的权益,其全部内容通过引用结合于此。
技术领域
本发明主要涉及一种包括嵌入其中的电子部件的印刷电路板及其制造方法,,并且,更具体地,本发明涉及一种包括嵌入其中的电子部件的印刷电路板及其制造方法,其将电子部件的电极端子电连接至内部电路层,从而使电路装配密度分散。
背景技术
目前,随着电子产品的小型化以及功能增加,包括嵌入其中的电子部件的印刷电路板得到了更多的关注。
为了实现包括嵌入其中的电子部件的印刷电路板,存在很多种用于将诸如集成电路(IC)芯片的半导体器件安装在印刷电路板上的表面安装技术。表面安装技术可以包括引线接合(wire bonding)技术和倒装(flip chip)技术。
在这些技术之中,使用引线接合技术的表面安装工艺以这种方式进行配置:使用粘合剂将电子部件(其上印刷有经过设计的电路)接合在印刷电路板上,将电子部件的端子(即,焊盘)经由金属引线连接至印刷电路板的引线框以在电子部件和印刷电路板之间传送信息,以及使用热固性树脂或热塑性树脂来对电子部件和引线进行成型工艺。
同时,不同于使用引线接合技术的工艺,使用倒装技术的表面安装工艺以这种方式配置:使用诸如金、焊料和其他金属的连接材料在电子部件上形成具有尺寸范围在几μm至几百μm的外部连接端子(即,凸块),包括形成在其上的凸块的电子部件被倒装以使该元件的表面面向印刷电路板,以及在倒装方向上将电子部件安装在印刷电路板上。
由于以将电子部件安装在印刷电路板表面上的普通方式进行表面安装工艺,所以在安装工艺之后所得到的产品的总厚度不会小于印刷电路板和电子部件的厚度的总和,从而难以制造高密度产品。另外,由于使用连接终端(焊盘或凸块)实现了电子部件和印刷电路板之间的电连接,故电连接可能由于连接端子的破损或侵蚀而损坏或发生故障,从而使产品的可靠性劣化。
为此,为了克服这些问题,将电子部件嵌入印刷电路内部而不是外部,并且形成积层(build-up layer)以进行电连接,从而实现紧凑且高密度的产品、使高频率(100MHz以上)处的引线距离最小化、以及在使用引线接合技术或倒装技术的表面安装工艺中避免在将元件彼此连接的步骤中出现可靠性的劣化。
图1至图7是示出了制造包括嵌入其中的电子部件的印刷电路板的传统工艺的截面图。
参考附图,现在将描述传统工艺。
首先,如图1所示,配备芯基板(core substrate)10,其由覆铜箔层压板和形成在覆铜箔层压板上的内部电路层11组成,其中用于将电子部件容纳在其中的空腔12形成在覆铜箔层压板中。
如图2所示,将用于支持电子部件的胶带(tape)13附着至芯基板10的一面。
如图3所示,将其上具有电极端子15的电子部件14插入空腔12中,然后将其沿面朝上(face-up)的方向附着至胶带13。
如图4所示,此后,第一绝缘层16形成在其上未附着有胶带13的芯基板10的另一侧上,并且还形成在电子部件14和空腔12的内壁之间的空隙中。
如图5所示,将胶带13从芯基板10的一侧去除。
如图6所示,第二绝缘层17形成在从中去除了胶带13的芯基板10的另一侧上。
如图7所示,最终,外部电路层18形成在第一绝缘层16和第二绝缘层17上,所述外部电路层具有连接至内部电路层11或电子部件14电极端子15的过孔19。
然而,在包括嵌入其中的电子部件的传统印刷电路板(其通过上述工艺制造)中,电子部件14的端子15仅通过过孔19连接至外部电路层18,而不连接至内部电路层11。换言之,电路集中在外部电路层18上,并且在电子部件14具有大量电极端子15的情况下,单独的外部电路层18不足以容纳如此多的电极端子15。因此,可能存在对能够嵌入印刷电路板中的电子部件14数量的不利限制。
图8示出了根据传统工艺在电子部件的电极端子和内部电路层之间的连接结构。从附图中可以了解,电子部件14的电极端子15和内部电路层11未彼此电连接。即,可以了解,电子部件14的电极端子15均未连接至内部电路层11。
发明内容
因此,考虑到在现有技术中出现的上述问题而提出了本发明,本发明提供了一种包括嵌入其中的电子部件的印刷电路板以及该印刷电路板的制造方法,其将电子部件的电极端子电连接至内部电路层,从而使电路装配密度分散。
在一个方面,本发明提供了一种包括嵌入其中的电子部件的印刷电路板,包括:芯基板,其具有形成在所述芯基板中的空腔并包括形成在所述芯基板两侧上的内部电路层;电子部件,容纳在空腔中;连接部,用于将电子部件的电极端子电连接至内部电路层;以及绝缘层,形成在芯基板的两侧上以覆盖电子部件。
印刷电路板还可以包括形成在绝缘层上的外部电路层。
外部电路层可以通过过孔连接至电极端子或内部电路层。
连接部可以将电极端子沿水平方向连接至内部电路层。
在另一方面,本发明提供了一种用于制造包括嵌入其中的电子部件的印刷电路板的方法,包括:配备芯基板,其具有形成在所述芯基板中的空腔并包括形成在所述芯基板上的内部电路层;将胶带附着至芯基板的一侧;将电子部件附着在胶带上以使空腔将电子部件容纳在其中;在芯基板的另一侧上形成第一绝缘层,以使第一绝缘层渗入空腔;去除附着至芯基板的一侧的胶带,并形成连接部,用于将电子部件的电极端子电连接至形成在芯基板的一侧上的内部电路层;以及在从中去除了胶带的芯基板的一侧上形成第二绝缘层。
胶带可以包括硅橡胶板或聚酰亚胺粘合带。
在将电子部件附着在胶带上的过程中,可以沿面朝下(face-down)的方向安装电子部件,以使电子部件的电极端子附着至胶带。
在去除胶带以及形成连接部的过程中,可以使用喷墨印刷工艺或丝网印刷工艺形成该连接部。
可以形成连接部,以在水平方向上将电极端子连接至内部电路层。
该方法还可以包括:在形成第二绝缘层之后,在第一绝缘层和第二绝缘层上形成包含过孔的外部电路层。
在形成外部电路层的过程中,可以形成过孔以将外部电路层连接至内部电路层或电极端子。
可以使用机械打孔、CO2激光打孔、Nd-Yag激光打孔以及湿法蚀刻中的任意一种来形成过孔。
附图说明
从结合附图所得到的以下详细描述中,将更加清楚地理解本发明的以上及其他目的、特征、和其他优点,其中:
图1至图7是示出了制造包括嵌入其中的电子部件的印刷电路板的传统工艺的截面图;
图8是示出了根据传统工艺的在电子部件和内部电路层之间的连接结构的示图;
图9是根据本发明实施例的包括嵌入其中的电子部件的印刷电路板的截面图;
图10至图17是根据本发明实施例的制造包括嵌入其中的电子部件的印刷电路板的工艺的截面图;以及
图18是示出了根据本发明实施例的在电子部件和内部电路层之间的连接结构的示图。
具体实施方式
参考附图,从以下实施例的描述中,本发明的各种目的、优点和特征将显而易见。在指定参考标号时,应该注意,在所有不同的附图中使用相同的参考标号来标明相同或相似的元件。同样,在本发明的说明书中,当考虑到现有技术的详细描述可能使本发明的要点难以理解时,会省略这样的详细描述。
在下文中,将参考附图更详细地描述本发明的实施例。
图9是根据本发明实施例的包括嵌入其中的电子部件的印刷电路板的截面图,图10至图17是顺序地示出了根据本发明实施例的制造包括嵌入其中的电子部件的印刷电路板的工艺的截面图,以及图18是示出了根据传统工艺的在电子部件的电极端子和内部电路层之间的连接结构的示图。
参考图9,根据本发明实施例的包括嵌入其中的电子部件的印刷电路板100包括芯基板105、电子部件107、连接部110和绝缘层109、111。
芯基板105包括:空腔103,用于使电子部件107能够安装在其中;内部电路层102,形成在该空腔的两侧上并且每个内部电路层均包括电路图案和焊接区(land);以及通孔104,用于在内部电路层102之间进行层间连接。
电子部件(可以为半导体器件)包括连接至电路层的电极端子108。
连接部110旨在用于在内部电路层102和电子部件107的一些电极端子108之间进行连接,并且可以在期望的范围内设置多个所述连接部。
形成连接部110以使内部电路层102通过该连接部水平地连接至电子部件107的电极端子108。
绝缘层109、111形成在芯基板105的两侧上以支持电子部件107。
绝缘层109、111其上设置有外部电路层113,且其中还设置有过孔112,用于将内部电路层102或电极端子108连接至外部电路层113。
图10至图17是顺序地示出了根据本发明实施例的制造包括嵌入其中的电子部件的印刷电路板的工艺的截面图。在下文中,将参考附图描述制造该印刷电路板的工艺。
如图10所示,首先配备双面覆铜箔层压板101,其包括构成芯基板的树脂层、和形成在树脂层的两侧上的铜层。
如图11所示,内部电路层102和空腔103形成在双面覆铜箔层压板101上及其中,从而配备了芯基板105。
此后,在芯基板105中形成通孔104,用于在形成在双面覆铜箔层压板的两侧上的内部电路层102之间进行连接。使用机械打孔或激光打孔(CO2激光打孔或Nd-Yag激光打孔)打通通孔104。
根据制造工艺,可以使用减成工艺、加成工艺、或改进的半加成工艺(MSAP)形成内部电路层102。在该实施例中,虽然为了便于说明而将内部电路层102描述为使用减成工艺而形成的,但是不应将根据本发明的制造工艺解释成仅限于减成工艺。
更具体地,内部电路层102按照这种方式形成:在铜层上涂覆光敏光刻胶,使光掩模与光刻胶紧密接触,使用紫外线和显影(development)来通过曝光使光刻胶图样化,并通过将图样化后的光刻胶用作抗蚀剂来对铜层的不必要区域进行化学蚀刻。
在这点上,在形成内部电路层102之后,可以与形成通孔104的打孔操作同时地形成用于容纳电子部件的空腔103,或者可以使用机械打孔、CO2激光打孔或Nd-Yag激光打孔来独立地形成空腔103。
随后,如图12所示,适于支持电子部件的胶带106附着至芯基板105的一侧。
这里,可以将硅橡胶板或聚酰亚胺(PI)粘合带用作胶带106。因此,通过使用具有粘附力的硅橡胶板或聚酰亚胺粘合带,电子部件能够处于期望的位置。此外,在随后的印刷以及固化填料或者在将电子部件安装在印刷电路板上之后形成用于保护电极元件的绝缘层的工艺中,粘合胶带106可能具有热阻以致即使通过加热或按压也不会使其变形。
如图13所示,将电子部件107附着至粘附于芯基板105一侧的胶带106上,以使电子部件107容纳在空腔103中。
此时,电子部件107附着在预定位置处,并且沿面朝下的方向安装,从而使用于与电路层电连接的电子部件107的电极端子108附着至胶带106。
参考图13,虽然电子部件107被示出作为沿面朝下的方向安装,但也可以沿面朝上的方向安装电子部件,这应被理解成落入本发明的范围内。
如图14所示,在芯基板105的另一侧上形成第一绝缘层109(其上未附着胶带),以使通孔104和在电子部件与空腔103的内壁之间的空隙填充有第一绝缘层109。
参考图14,进行第一绝缘层109的形成。然而,在形成第一绝缘层之前,可以首先进行封装工艺,以保持电子部件107附着在胶带106上。以填充填料的方式进行封装工艺,即,将填料压进空腔103的内壁和电子部件107之间的空隙中,以将电子部件107保持在预定位置而不用移位(displacement)。可以使用丝网印刷、掩模印刷、滴涂(dispensing)等进行填充,并且填料可以是热固性树脂、热塑性树脂或者两者的结合。
随后,如图15所示,在翻转包括形成在其上的第一绝缘层109的芯基板105之后,去除胶带106,然后形成连接部110以将电路层102与电子部件107的一些电极端子电连接。
此时,可以使用喷墨印刷工艺或丝网印刷工艺来形成连接部110。
按照这种方式进行喷墨印刷工艺:在内部电路层102和电子部件107的电极端子108之上放置喷墨头(header),从喷墨头喷射油墨以形成用于在内部电路层102和电子部件107的电极端子108之间进行电连接的连接部110。油墨由金属(例如,银)和溶剂组成,因而具有导电性。
同时,按照这种方式进行丝网印刷工艺:在期望位置处具有开口的丝网印刷掩模上放置用于构成连接部的导电糊剂,并且按压导电糊剂并使用从丝网印刷掩模的一个侧边移向另一侧边的压头(squeeze)来将其在与丝网印刷掩模接触的状态下挤压进开口中。在此操作期间,掩模中的开口填充有导电糊剂,使得连接部110形成在内部电路层102和电子部件107的电极端子108上,开口位于该电极端子之上。此后,去除丝网印刷掩模。
由于使用这种工艺使内部电路层102和电子部件107的电极端子108彼此电连接,所以可以解决传统的由于外部电路层和电子部件通过过孔连接而使外部电路层的电路密度增大的问题,且不会受电子部件的高密度端子的影响。即,由于电子部件107的电极端子108电连接至内部电路层102,故分散了电路装配密度。
尽管链接部110被示出作为形成在内部电路层102和电极端子108上,但是用于将内部电路层102连接至电极端子108的任何结构(例如,在内部电路层102和电极端子108彼此连接而没有第一绝缘层109置于其间的结构)应被理解为落入本发明的范围内。
形成连接部110以将内部电路层102沿水平方向连接至电极端子108。参考图15,连接部110被示出作为置于内部电路层102和电极端子108上,以使内部电路层102和电极端子108彼此水平连接。
此后,如图16所示,第二绝缘层111形成在芯基板105上,所述芯基板上形成有连接部110。在这点上,由于按照与第一绝缘层109相同的方式形成第二绝缘层111,所以省略对其详细描述。
通过上述工艺,制造了包括嵌入其中的电子部件的印刷电路板100。
此外,根据包括嵌入其中的电子部件的印刷电路板的制造工艺,如图17所示,在第一绝缘层109和第二绝缘层111上形成包括过孔112的外部电路层113。
在这点上,按照这种方式形成过孔112:将过孔112连接至电极端子108,所述电极端子不连接至内部电路层102或者用于将内部电路层102连接至外部电路层113。使用机械打孔、激光打孔(CO2激光打孔或Nd-Yag激光打孔)以及湿法蚀刻中的任意一种来形成过孔112。
尽管附图中未示出,但显而易见,可以通过进一步在芯基板105的两侧上设置过孔或凸块来制造多层的印刷电路板(包括嵌入其中的电子部件107)。
图18示出了根据本发明实施例的在内部电路层102和电子部件107的电极端子108之间的电连接结构。再次如图8所示,在传统的印刷电路板中,内部电路层102未连接至电子部件102的任意一个电极端子108,而是简单地用作接地。与此相反,应了解,根据本发明实施例的印刷电路板被配置成内部电路层102电连接至电子部件107的电极端子108,从而使电流装配密度分散。具体地,应了解,形成在电子部件107上的12个电子端子108中的八个电极端子108通过连接部件110连接至内部电路层102。尽管图中未示出,但剩余的电极端子108将通过过孔112连接至外部电路层113。
如上所述,根据本发明,由于电子部件的一些电极端子首先通过连接部连接至内部电路层,并且剩余的电极端子再通过过孔连接至外部电路层,所以使电路装配密度分散,因此,即使当需要大量电极端子时,根据本发明的印刷电路板仍能够容纳电极端子。
此外,由于本发明用于将电子部件的电极端子电连接至内部电路层,使电路装配密度分散,从而减小整个印刷电路板的尺寸。
尽管为了说明目的而公开了本发明的优选实施例,但本领域的技术人员应了解,在不背离附图所披露的本发明的范围和精神的情况下,可以进行各种修改、添加和替代。因此,应理解,这种修改、添加和替代落入本发明的范围内。
Claims (12)
1.一种包括嵌入其中的电子部件的印刷电路板,包括:
芯基板,具有形成在所述芯基板中的空腔,并包括形成在所述芯基板的两侧上的内部电路层;
电子部件,容纳在所述空腔中;
连接部,用于将所述电子部件的电极端子电连接至所述内部电路层;以及
绝缘层,形成在所述芯基板的两侧上以覆盖所述电子部件。
2.根据权利要求1所述的印刷电路板,还包括形成在所述绝缘层上的外部电路层。
3.根据权利要求2所述的印刷电路板,其中,所述外部电路层通过过孔连接至所述电极端子或所述内部电路层。
4.根据权利要求1所述的印刷电路板,其中,所述连接部沿水平方向将所述电极端子连接至所述内部电路层。
5.一种用于制造包括嵌入其中的电子部件的印刷电路板的方法,包括:
制备芯基板,所述芯基板具有形成在所述芯基板中的空腔,并包括形成在所述芯基板上的内部电路层;
将胶带附着至所述芯基板的一侧;
将所述电子部件附着在所述胶带上,使得所述空腔将所述电子部件容纳在其中;
在所述芯基板的另一侧上形成第一绝缘层,使得所述第一绝缘层渗入所述空腔;
去除附着至所述芯基板的所述一侧的胶带,并形成连接部,用于将所述电子部件的电极端子电连接至形成在所述芯基板的所述一侧上的内部电路层;以及
在所述芯基板的去除了所述胶带的所述一侧上形成第二绝缘层。
6.根据权利要求5所述的方法,其中,所述胶带包括硅橡胶板或聚酰亚胺粘合带。
7.根据权利要求5所述的方法,其中,在所述的将所述电子部件附着在所述胶带上的过程中,沿面朝下的方向安装所述电子部件,使得所述电子部件的电极端子附着至所述胶带。
8.根据权利要求5所述的方法,其中,在所述的去除所述胶带以及形成所述连接部的过程中,使用喷墨印刷工艺或丝网印刷工艺形成所述连接部。
9.根据权利要求5所述的方法,其中,形成所述连接部,以沿水平方向将所述电极端子连接至所述内部电路层。
10.根据权利要求5所述的方法,还包括:在所述的形成所述第二绝缘层之后,在所述第一绝缘层和所述第二绝缘层上形成包含过孔的外部电路层。
11.根据权利要求10所述的方法,其中,在形成所述外部电路层的过程中,形成所述过孔以将所述外部电路层连接至所述内部电路层或所述电极端子。
12.根据权利要求10所述的方法,其中,使用机械打孔、CO2激光打孔、Nd-Yag激光打孔以及湿法蚀刻中的任意一种来形成所述过孔。
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- 2008-08-28 CN CN2008102139102A patent/CN101609830B/zh not_active Expired - Fee Related
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2011
- 2011-08-31 US US13/137,655 patent/US20110314667A1/en not_active Abandoned
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US20090310323A1 (en) | 2009-12-17 |
CN101609830B (zh) | 2011-07-27 |
US20110314667A1 (en) | 2011-12-29 |
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