CN105720036A - 封装结构及其制法 - Google Patents

封装结构及其制法 Download PDF

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Publication number
CN105720036A
CN105720036A CN201410727443.0A CN201410727443A CN105720036A CN 105720036 A CN105720036 A CN 105720036A CN 201410727443 A CN201410727443 A CN 201410727443A CN 105720036 A CN105720036 A CN 105720036A
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Prior art keywords
insulating barrier
line layer
encapsulating structure
electronic component
conductive pole
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CN201410727443.0A
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许诗滨
吴唐仪
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Persistent Strength Or Power Science And Technology Co Ltd
Phoenix Pioneer Technology Co Ltd
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Persistent Strength Or Power Science And Technology Co Ltd
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Priority to CN201410727443.0A priority Critical patent/CN105720036A/zh
Priority to US14/801,099 priority patent/US20160163629A1/en
Publication of CN105720036A publication Critical patent/CN105720036A/zh
Pending legal-status Critical Current

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Abstract

一种封装结构及其制法，先形成多个导电柱于一导体层上，再形成一绝缘层于该导体层与所述多个导电柱上，接着，移除该导体层的部分材质，使该导体层作为线路层，之后于该线路层上设置一电子元件，最后形成一包覆层以包覆该电子元件，所以通过单一线路层的设计，使该线路层结合电子元件，而该导电柱能结合焊球，以缩短信号传递路径。

Description

封装结构及其制法
技术领域
本发明涉及一种封装结构，特别涉及一种单层线路层的封装结构及其制法。
背景技术
随着半导体封装技术的演进，于智能型手机、平板、网络、笔记本计算机等产品中，半导体装置(Semiconductordevice)已开发出不同的封装型态，例如，球栅数组式(Ballgridarray，简称BGA)、四方扁平式半导体封装件(Quad-FlatPackage，简称QFP)或四方扁平无引脚式(QuadFlatNonleadPackage，简称QFN)半导体封装件等。
如第1A图所示，公知QFP封装结构1包括：承载座10、位于该承载座10周围的多个引脚11、黏接至该承载座10上并以多个焊线120电性连接该引脚11的电子元件12、以及包覆该电子元件12、承载座10、焊线120及引脚11的如封装胶体的绝缘层13，且该引脚11凸伸出该绝缘层13。
然而，公知QFP封装结构1的制法中，该承载座10与该些引脚11是来自于导线架，所以无法任意布线，亦即限制线路与接点的设计。例如，公知导线架的一排引脚11的总长约占有400um，该承载座10的总长约占有125um，所以已限制该引脚11的I/O数量与长度(pitch)。
再者，于进行封装时，受限于该导线架的固定尺寸与该焊线120的高度，所以公知QFP封装结构1的整体厚度较厚，且难以薄化。
又，公知QFP封装结构1中，受限于该导线架的设计，导致其引脚11的数量少，亦即接点数量少，因而难以实现高接点数量与薄型化的需求。
如第1B图所示，公知BGA封装结构1’能在相同单位面积的封装基板上容纳更多输入/输出接点(I/Oconnection)以符合高度集积化(Integration)的芯片所需。所述的封装结构1’包括：于上侧10a与下侧10b具有一线路层11a,11b的一承载板10’、设于该承载板10’上侧10a并以多个导电凸块120’电性连接该线路层11a的电子元件12、包覆该些导电凸块120’的如底胶的绝缘层13、以及设于该承载板10’下侧10b的线路层11b上的多个如焊球的导电元件14，且该承载板10’中具有电性连接该线路层11a,11b的导电柱100。因此，该电子元件12是以打线接合(wrebonding)或倒装芯片接合(Flipchip)方式电性连接该承载板10’，再于该承载板10’下侧10b的线路层11b植设导电元件14而进行电性外接，以达到高脚数的目的。
惟，公知BGA封装结构1’中，于更高频使用时或高速操作时，因信号传递路径过长(即导电元件14、线路层11a,11b与导电柱100)而无法提升电性表现，以致于该封装结构1’的效能有所限制。
再者，公知BGA封装结构1’需制作至少两层线路层11a,11b与导电柱100(如钻孔工艺，且于导通孔内镀上铜材，以作为层与层间的连接)，所以整体结构不仅难以符合薄化需求，且因生产工艺复杂、流程长而难以降低制造成本。
又，公知BGA封装结构1’因需制作较多的连接接口(如两线路层11a,11b与导电柱100之间)，且需使用各层材质不相同的复合式承载板10’，所以不仅容易发生分层，且大幅增加制造成本。
另外，因该承载板10’是由多层(多种原材料组成)热膨胀系数(thermalexpansioncoefficient，简称CTE)与电性特质不匹配的复合式材质所构成，特别是材料间的CTE不匹配，所以于工艺中容易发生翘曲。
因此，如何避免公知技术中的种种缺失，实已成为目前亟欲解决的课题。
发明内容
鉴于上述公知技术的种种缺失，本发明提供一种封装结构，包括：一绝缘层，具有相对的第一表面与第二表面；多个导电柱，嵌埋于该绝缘层中且其端面外露于该绝缘层的第一表面；一线路层，嵌设于该绝缘层的第二表面上并电性连接该些导电柱；至少一电子元件，设于该线路层上并电性连接该线路层；以及一包覆层，形成于该线路层与该绝缘层的第二表面上并包覆该电子元件。
在本发明的封装结构的一个实施方式中，该线路层供电性连接该电子元件，且该导电柱的端面定义为外接垫。
在本发明的封装结构的另一个实施方式中，该导电柱的端面齐平该绝缘层的第一表面。
在本发明的封装结构的另一个实施方式中，该电子元件为主动元件、被动元件或其二者组合。
在本发明的封装结构的另一个实施方式中，该电子元件以倒装芯片方式电性连接该线路层。
在本发明的封装结构的另一个实施方式中，所述封装结构还包括多个导电元件，形成于该绝缘层的第一表面上并电性连接所述多个导电柱。
本发明还提供一种封装结构的制法，包括：形成多个导电柱于一导体层上；形成一绝缘层于该导体层与该些导电柱上，其中，该绝缘层具有相对的第一表面与第二表面，且令该些导电柱的端面外露于该绝缘层的第一表面；移除该导体层的部分材质，使该导体层作为线路层；于该线路层上设置至少一电子元件，且该电子元件电性连接该线路层；以及于该线路层与该绝缘层的第二表面上形成一包覆层，使该包覆层包覆该电子元件。
本发明另提供一种封装结构的制法，包括：形成多个导电柱于一导体层上；形成一绝缘层于该导体层与该些导电柱上，并使该绝缘层完全包覆该些导电柱，其中，该绝缘层具有相对的第一表面与第二表面；移除部分的绝缘层，令该些导电柱的端面外露于该绝缘层的第一表面；移除该导体层的部分材质，使该导体层作为线路层；于该线路层上设置至少一电子元件，且该电子元件电性连接该线路层；以及于该线路层与该绝缘层的第二表面上形成一包覆层，使该包覆层包覆该电子元件。
在本发明的封装结构的制法的一个实施方式中，该线路层供电性连接该电子元件，且该导电柱的端面定义为外接垫。
在本发明的封装结构的制法的另一个实施方式中，该导电柱的端面齐平该绝缘层的第一表面。
在本发明的封装结构的制法的另一个实施方式中，该电子元件为主动元件、被动元件或其二者组合。
在本发明的封装结构的制法的另一个实施方式中，该电子元件以倒装芯片方式电性连接该线路层。
在本发明的封装结构的制法的另一个实施方式中，还包括形成多个导电元件于该绝缘层的第一表面上，且所述多个导电元件电性连接所述多个导电柱。
由上可知，本发明封装结构及其制法，通过仅需制作一层线路层，且以该导电柱作外接垫的设计，使该线路层结合电子元件，而导电柱结合焊球，以缩短信号传递路径，因而能减少信号损失，所以能提升电气特性。
再者，本发明封装结构通过将多个导电柱形成于单一线路层上的设计，使该些导电柱的端面作外接垫，因而无需制作另一层线路，所以能省略公知钻孔工艺、填孔工艺、第二线路层的制作等，因而不仅大幅降低封装结构的厚度以符合薄化的需求，且能大幅降低制造成本。
又，本发明封装结构是于单一线路层与该些导电柱间具有连接接口，使其连接接口的数量少于公知技术的连接接口的数量，因而能避免分层问题，且因直接将该导电层图案化制作成该线路层，所以能大幅降低制造成本。
另外，本发明的绝缘层为单一材质，而非公知承载板的复合式材质，所以能避免该绝缘层的应力分布不均而发生翘曲的问题。
附图说明
第1A图为公知QFP封装结构的剖视示意图；
第1B图为公知BGA封装结构的剖视示意图；以及
第2A至2H图为本发明的封装结构的制法的剖视示意图。
其中，附图标记说明如下：
1、1’、2封装结构
10承载座
10’承载板
10a上侧
10b下侧
100导电柱
11引脚
11a、11b、20’线路层
12、22电子元件
120焊线
120’、220导电凸块
13、25绝缘层
14、24导电元件
20导体层
21导电柱
21a端面
23包覆层
25a第一表面
20b第二表面
200凹状
S切割路径。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域普通技术人员可由本说明书所公开的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附附图所绘示的结构、比例、大小等，均仅用以配合说明书所公开的内容，以供本领域普通技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所公开的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等的用语，亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
第2A至2G图为本发明的封装结构2的制法的剖视示意图。
如第2A图所示，提供一导体层20。于本实施例中，该导体层20为金属材，例如铜，但不限于此。
如第2B图所示，形成多个导电柱21于该导体层20上。
如第2C图所示，形成一绝缘层25于该导体层20与该些导电柱21上，并使该绝缘层25完全包覆该些导电柱21，其中，该绝缘层25具有相对的第一表面25a与第二表面25b。
于本实施例中，形成该绝缘层25的材质为底层涂料(Primer)或介电材料。
如第2D图所示，移除该绝缘层25的第一表面25a的部分材质，令该些导电柱21的端面21a外露于该绝缘层25的第一表面25a。
又，于其它实施例中可利用整平工艺(如研磨绝缘层25的方式)，使该些导电柱的端面齐平该绝缘层的第一表面。
如第2E图所示，图案化移除该导体层20的部分材质与该绝缘层25的第二表面25b的部分材质，使该导体层20作为线路层20’，且令该绝缘层25的第二表面25b露出该线路层20’的部分表面。
于本实施例中，该线路层20’电性连接该些导电柱21。
再者，以蚀刻方式进行图案化，所以该线路层20’的第二表面20b会呈现凹状200。
如第2F图所示，于该线路层20’上设置至少一电子元件22，且该电子元件22电性连接该线路层20’。
于本实施例中，该电子元件22为主动元件、被动元件或其二者组合，且该主动元件是例如半导体元件(如芯片)，而该被动元件是例如电阻、电容及电感。
再者，该电子元件22是通过多个导电凸块220以经由该线路层20’电性连接至该些导电柱21。
如第2G图所示，于该线路层20’与该绝缘层25的第二表面25b上形成一包覆层23，使该包覆层23包覆该电子元件22与该些导电凸块220。
于本实施例中，该包覆层23是以铸模方式(molding)、涂布方式或压合方式形成于该承载板20上，且形成该包覆层23的材质为铸模化合物(MoldingCompound)、底层涂料(Primer)、或如环氧树脂(Epoxy)的介电材料。
再者，于另一实施例中，该电子元件22的上表面亦可外露于该包覆层23的上表面。
又，于其它实施例中，亦可先形成底胶(图略)以包覆该些导电凸块220，再形成该包覆层23。
如第2H图所示，形成多个如焊球的导电元件24于该绝缘层25的第一表面25a上，且沿如第2G图所示的切割路径S进行切单工艺，以获得多个封装结构2。
于本实施例中，该些导电元件24是结合并电性连接该些导电柱21的端面21a，以通过该些导电元件24堆栈结合其它电子装置(图略)。
本发明封装结构2的制法中，通过仅需制作一层线路层20’，且以该导电柱21作外接垫，使该线路层20’结合该电子元件22，而该些导电柱21结合该些导电元件24，以缩短信号传递路径，因而能减少信号损失，所以能提升电气特性。
再者，本发明封装结构2通过将多个导电柱21形成于单一线路层20’上的设计，使该些导电柱21的端面21a作外接垫，因而无需制作另一层线路，所以能省略公知钻孔工艺、填孔工艺、第二线路层的制作等，因而不仅大幅降低该封装结构2的整体厚度以符合薄化的需求，且能大幅降低制造成本。
又，本发明封装结构2是于单一线路层20’与该些导电柱21间具有连接接口，使其连接接口的数量少于公知技术的连接接口的数量，因而能降低分层的风险，所以可靠度提高，且因直接将该导体层20图案化制作成该线路层20’，所以能大幅降低制造成本。
另外，本发明的绝缘层25为单一材质，而非公知承载板的复合式材质，所以能避免该绝缘层25的应力分布不均而发生翘曲的问题。
本发明还提供一种封装结构2，包括：一绝缘层25、多个导电柱21、一线路层20’、至少一电子元件22、以及一包覆层23。
所述的绝缘层25具有相对的第一表面25a及第二表面25b。
所述的导电柱21嵌埋于该绝缘层25中且其端面21a外露于该绝缘层25的第一表面25a。
所述的线路层20’嵌设于该绝缘层25的第二表面25b上并电性连接该些导电柱21。
所述的电子元件22设于该线路层20’上并电性连接该线路层20’。例如，该电子元件22为主动元件、被动元件或其二者组合，且该电子元件22以倒装芯片方式电性连接该线路层20’。
所述的包覆层23形成于该线路层20’与该绝缘层25的第二表面25b上并包覆该电子元件22。
于一实施例中，该线路层20’定义供电性连接该电子元件22，且该些导电柱21的端面21a定义为外接垫。
于一实施例中，该导电柱的端面齐平该绝缘层的第一表面(图略)。
于一实施例中，所述的封装结构2还包括多个导电元件24，结合于该绝缘层25的第一表面25a上并电性连接该些导电柱21的端面21a。
上述实施例是用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域普通技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如后述的权利要求所列。

Claims (13)

1.一种封装结构，其特征在于，该封装结构包括：
一绝缘层，具有相对的第一表面与第二表面；
多个导电柱，嵌埋于该绝缘层中且其端面外露于该绝缘层的第一表面；
一线路层，嵌设于该绝缘层的第二表面上并电性连接所述多个导电柱；
至少一电子元件，设于该线路层上并电性连接该线路层；以及
一包覆层，形成于该线路层与该绝缘层的第二表面上并包覆该电子元件。
2.如权利要求1所述的封装结构，其特征在于，该线路层供电性连接该电子元件，且该导电柱的端面定义为外接垫。
3.如权利要求1所述的封装结构，其特征在于，该导电柱的端面齐平该绝缘层的第一表面。
4.如权利要求1所述的封装结构，其特征在于，该电子元件为主动元件、被动元件或其二者组合。
5.如权利要求1所述的封装结构，其特征在于，该电子元件以倒装芯片方式电性连接该线路层。
6.如权利要求1所述的封装结构，其特征在于，所述封装结构还包括多个导电元件，形成于该绝缘层的第一表面上并电性连接所述多个导电柱。
7.一种封装结构的制法，其特征在于，包括：
形成多个导电柱于一导体层上；
形成一绝缘层于该导体层与所述多个导电柱上，其中，该绝缘层具有相对的第一表面与第二表面，且令所述多个导电柱的端面外露于该绝缘层的第一表面；
移除该导体层的部分材质，使该导体层作为线路层；
于该线路层上设置至少一电子元件，且该电子元件电性连接该线路层；以及
于该线路层与该绝缘层的第二表面上形成一包覆层，使该包覆层包覆该电子元件。
8.一种封装结构的制法，其特征在于，包括：
形成多个导电柱于一导体层上；
形成一绝缘层于该导体层与所述多个导电柱上，并使该绝缘层完全包覆所述多个导电柱，其中，该绝缘层具有相对的第一表面与第二表面；
移除部分的绝缘层，令所述多个导电柱的端面外露于该绝缘层的第一表面；
移除该导体层的部分材质，使该导体层作为线路层；
于该线路层上设置至少一电子元件，且该电子元件电性连接该线路层；以及
于该线路层与该绝缘层的第二表面上形成一包覆层，使该包覆层包覆该电子元件。
9.如权利要求7或8所述的封装结构的制法，其特征在于，该线路层供电性连接该电子元件，且该导电柱的端面定义为外接垫。
10.如权利要求7或8所述的封装结构的制法，其特征在于，该导电柱的端面齐平该绝缘层的第一表面。
11.如权利要求7或8所述的封装结构的制法，其特征在于，该电子元件为主动元件、被动元件或其二者组合。
12.如权利要求7或8所述的封装结构的制法，其特征在于，该电子元件以倒装芯片方式电性连接该线路层。
13.如权利要求7或8所述的封装结构的制法，其特征在于，还包括形成多个导电元件于该绝缘层的第一表面上，且所述多个导电元件电性连接所述多个导电柱。
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