TWI462192B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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TWI462192B
TWI462192B TW096120262A TW96120262A TWI462192B TW I462192 B TWI462192 B TW I462192B TW 096120262 A TW096120262 A TW 096120262A TW 96120262 A TW96120262 A TW 96120262A TW I462192 B TWI462192 B TW I462192B
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Taiwan
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metal layer
metal
semiconductor package
layer
encapsulant
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TW096120262A
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TW200849419A (en
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李春源
洪孝仁
林宥緯
張錦煌
賴正淵
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矽品精密工業股份有限公司
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Priority to TW096120262A priority Critical patent/TWI462192B/zh
Priority to US12/156,875 priority patent/US20080303134A1/en
Publication of TW200849419A publication Critical patent/TW200849419A/zh
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Publication of TWI462192B publication Critical patent/TWI462192B/zh

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Description

半導體封裝件及其製法
本發明係有關於一種半導體封裝件及其製法，尤指一種毋需承載件之半導體封裝件及其製法。
傳統以導線架作為晶片承載件之半導體封件之型態及種類繁多，就四邊扁平無導腳(Quad Flat Non－leaded,QFN)半導體封裝件而言，其特徵在於未設置有外導腳，即未形成有如習知四邊形平面(Quad Flat package,QFP)半導體封裝件中用以與外界電性連接之外導腳，如此，將得以縮小半導體封裝件之尺寸。
然而伴隨半導體產品輕薄短小之發展趨勢，傳統導線架之QFN封裝件往往因其封裝膠體厚度之限制，而無法進一步縮小封裝件之整體高度，因此，業界便發展出一種無承載件(carrier)之半導體封裝件，冀藉由減低習用之導線架厚度，以令其整體厚度得以較傳統導線架式封裝件更為輕薄。
請參閱第1圖，係為美國專利第5,830,800號案所揭示之無承載件之半導體封裝件，該半導體封裝件主要先於一銅板(未圖示)上形成多數電鍍銲墊(Pad)12，接著，再於該銅板上設置晶片13並透過銲線14電性連接晶片13及電鍍銲墊12，復進行封裝模壓製程以形成封裝膠體15，然後再蝕刻移除該銅板以使電鍍銲墊12顯露於外界，接著以拒銲層11定義出該電鍍銲墊12位置，以供植設銲球16於該電鍍銲墊12上，藉以完成一無需晶片承載件以供晶片接置使用之封裝件。相關之技術內容亦可參閱美國專利第6,770,959、6,989,294、6,933,594及6,872,661等。
惟前述之無承載件之半導體封裝件中，須先以拒銲層定義出電鍍銲墊位置，方可使銲球植設於該電鍍銲墊上，然而該銅板於蝕刻移除後，若製程採批次方式進行時，整個封裝膠體結構係呈一陣列形狀，因封裝膠體結構產生之翹曲影響，難以有效且精準將拒銲層及拒銲層開口設置於該封裝件上，造成製程之不便；相對地，若製程以單顆封裝件進行時，對應於小面積之拒銲層塗佈及曝光、顯影作業，其生產效率不高，造成製程成本的增加。另外，若不以拒銲層定義出銲墊位置，則於植設時銲球很難定位於該電鍍銲墊上，易造成回銲(reflow)時，銲球於電鍍銲墊發生位移(shift)及銲球脫層問題。
鑒此，請參閱第2A至2D圖，美國專利第6,072,239號遂揭示一種無承載件之半導體封裝件及其製法，主要係提供一銅板20，並於該銅板20上形成阻層21，且令該阻層21定義出欲電鍍開孔210，以於該開孔210中電鍍形成金屬銲墊22(如第2A圖所示)；移除該阻層21，並以該金屬銲墊22作為蝕刻遮罩而半蝕刻該銅板20，以令該銅板20形成有相對高、低表面(如第2B圖所示)；於該銅板20相對較低表面上接置半導體晶片23，並以銲線24電性連接該半導體晶片23及該銅板20上相對較高表面之金屬銲墊22，再於該銅板20上形成覆蓋該半導體晶片23及銲線24之封裝膠體25(如第2C圖所示)；蝕刻移除該銅板20，以令該封裝膠體25表面形成有相對內凹之凹槽250，且該金屬銲墊22即位於該凹槽250底部，亦即使該金屬銲墊22相對內凹於該封裝膠體25中，藉以在相對內凹於該封裝膠體25中之金屬銲墊22上植設銲球26，以有效定位該銲球26(如第2D圖所示)。
惟前述製程中，在進行銅板之半蝕刻製程時，該蝕刻深度不易控制，亦即容易導致內凹於封裝膠體之凹槽深淺不同，造成後續植設於該凹槽底部金屬銲墊上之銲球高度不穩定。再者，該銲球僅在其底部與金屬銲墊形成共金結構，且相對在該凹槽開口角端處因應力集中之效應，易導致銲球發生裂損(crack)C(如第3A圖所示)。此外，由於該金屬銲墊為約0.5至5 μm厚之電鍍層，且其僅在凹槽底部與封裝膠體接觸，彼此附著力明顯有限，易因銲球之應力造成該金屬銲墊與封裝膠體間發生脫層(delamination)D，如第3B圖所示。
因此，如何解決上述問題而能提供一種無承載件之半導體封裝件及其製法，可有效定位銲球，且避免銲球應力集中造成銲球破裂及脫層問題，同時不須使用拒銲層以提升製程效率，改善銲球品質及降低製程成本，實為業界亟待解決之課題。
有鑑於前述及其他問題，本發明之一目的在於提供一種毋需承載件之半導體封裝件及其製法。
本發明之另一目的在於提供一種半導體封裝件及其製法，可有效定義銲墊位置，以供容置銲球。
本發明之另一目的在於提供一種半導體封裝件及其製法，可毋需使用拒銲層定義銲墊位置，藉以簡化製程及降低成本。
本發明之另一目的在於提供一種半導體封裝件及其製法，可避免銲墊與封裝膠體間脫層問題。
本發明之另一目的在於提供一種半導體封裝件及其製法，可避免銲球受應力集中造成銲球破裂問題。
為達成上揭及其他目的，本發明揭露一種半導體封裝件之製法，包括：提供一載板且於該載板上形成有複數金屬塊；於該載板上形成包覆該金屬塊之金屬層；將至少一半導體晶片電性連接至該金屬層；於該載板上形成包覆該半導體晶片之封裝膠體；移除該載板及金屬塊，藉以相對在該封裝膠體表面形成有複數之凹槽，以外露出該凹槽內之金屬層；以及於該凹槽中植設導電元件。
該金屬塊及金屬層之製法係包括：提供一金屬材質之金屬載板，藉以於該金屬載板上覆蓋第一阻層，並令該第一阻層形成有複數第一開口；於該第一開口中電鍍形成金屬塊；移除該第一阻層；於該金屬載板上覆蓋第二阻層，並令該第二阻層形成有第二開口以外露出該金屬塊，其中該第二開口尺寸係大於該第一開口尺寸；於該第二開口中電鍍形成金屬層，以使該金屬層包覆該金屬塊；以及移除該第二阻層。
再者，復可於該凹槽底面、側邊及自底面凸伸形成有金屬層，亦或使該金屬層形成於該封裝膠體表面凹槽之底面與側邊，且該金屬層具有延伸部以形成於該凹槽周圍之封裝膠體表面，藉以增加導電元件與金屬層之接著面積，強化導電元件與金屬層之接合。
透過前述之製法，本發明復揭示一種半導體封裝件，係包括：封裝膠體，且該封裝膠體表面形成有複數凹槽；金屬層，係覆蓋於該凹槽底面及側邊；半導體晶片，係內嵌於該封裝膠體中且電性連接至該金屬層；以及導電元件，係植設於該凹槽中且與該金屬層電性連接。
因此本發明之半導體封裝件及其製法主要係先在載板上形成複數金屬塊，再於該載板上形成包覆該金屬塊之金屬層，以將至少一半導體晶片電性連接至該金屬層，並於該載板上形成包覆該半導體晶片之封裝膠體，接著即移除該載板及金屬塊，藉以相對在該封裝膠體表面形成有複數凹槽，且該凹槽底面及側邊形成有先前覆蓋於該金屬塊之金屬層，之後即可於該凹槽中植設導電元件，以製得本發明之半導體封裝件。如此，本發明中形成於該封裝膠體表面之凹槽深度大小可由金屬塊高度精密定義及控制，避免習知直接半蝕刻銅板時，因蝕刻深度不易控制，導致後續植設銲球高度發生不穩定問題，同時透過該凹槽可有效定位導電元件，避免習知透過拒銲層定位銲球時，所造成製程繁雜及成本增加問題，另外，因本發明中導電元件與金屬層接觸面包含有凹槽之底面及側邊，以產生足夠的共金結構，強化該導電元件和金屬層之接合強度，此外，該金屬層與封裝膠體間亦形成有包含凹槽底面及側邊等接觸面，可供該金屬層有效附著於該封裝膠體而不致發生脫層問題，再者，該封裝膠體於凹槽開口之角緣與導電元件接觸位置，因有金屬層附著，故得減低因應力集中現象而發生導電元件裂損問題。
以下係藉由特定的具體實施例說明本發明之實施方式，熟習此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點與功效。
第一實施例
請參閱第4A至4G圖，係本發明之半導體封裝件及其製法第一實施之剖面示意圖。
如第4A圖所示，首先，製備一金屬材質之載板40(例如銅板(Cu Plate))，並於該金屬載板40之一表面上覆蓋第一阻層41，且令該第一阻層41形成有複數第一開口410，藉以定義出後續供與半導體晶片電性連接之導腳(terminal)位置41a及供接置半導體晶片之晶片座(die pad)位置41b。
如第4B圖所示，進行電鍍製程，以於該第一開口410中電鍍形成金屬塊42，其材質例如為金屬銅。
如第4C圖所示，移除該第一阻層41，並於該金屬載板40上覆蓋第二阻層43，且令該第二阻層43形成有複數第二開口430以外露出該金屬塊42，以再次定義導腳位置41a及晶片座位置41b。該第二開口430尺寸係大於第一開口410尺寸，以使該金屬塊42完整外露出該第二阻層43。
如第4D圖所示，進行電鍍製程，以於該第二開口430中電鍍形成金屬層44，並使該金屬層44包覆該金屬塊42，該金屬層44例如為金(Au)/鈀(Pd)/鎳(Ni)/鈀(Pd)、金(Au)/鎳(Ni)/金(Au)、及金(Au)/銅(Cu)/金(Au)之其中一者。
如第4E圖所示，移除該第二阻層43，並於該對應為晶片座位置41b之金屬層44上接置半導體晶片45，且透過銲線46電性連接該半導體晶片45及對應為導腳位置41a之金屬層44，接著於該金屬載板40上形成包覆該半導體晶片45及銲線46之封裝膠體47。
如第4F圖所示，同時蝕刻移除該金屬載板40及金屬塊42，藉以在該封裝膠體47表面形成先前由金屬塊42所定義之凹槽470，同時令該凹槽470至少於其底面及側邊形成有先前覆蓋在金屬塊42外表面之金屬層44。
如第4G圖所示，於該凹槽470中植設如銲球之導電元件48，並使該導電元件48得以與該凹槽470底面及側邊之金屬層44有效接著與電性連接。
對應接置於該導腳位置41a上之金屬層44的導電元件48係供傳輸半導體晶片訊號，而對應接置於該晶片座位置41b上之金屬層44的導電元件48係供半導體晶片接地或導熱功能。
另外，本發明製程中，該半導體晶片亦可直接置於金屬載板上，而省略晶片座位置上之金屬塊及金屬層之製作，另該半導體晶片復可以覆晶方式電性連接至該金屬層。
透過前述之製法，本發明復揭示一種半導體封裝件，係包括：封裝膠體47，該封裝膠體47表面形成有複數凹槽470；金屬層44，係覆蓋於該凹槽470底面及側邊；半導體晶片45，係內嵌於該封裝膠體47中且電性連接至該金屬層44；以及導電元件48，係植設於該凹槽470中且與該金屬層44電性連接。
因此本發明之半導體封裝件及其製法主要係先在載板上形成複數金屬塊，再於該載板上形成包覆該金屬塊之金屬層，以將至少一半導體晶片電性連接至該金屬層，並於該載板上形成包覆該半導體晶片之封裝膠體，接著即移除該載板及金屬塊，藉以相對在該封裝膠體表面形成有複數凹槽，且該凹槽底面及側邊形成有先前覆蓋於該金屬塊之金屬層，之後即可於該凹槽中植設導電元件，以製得本發明之半導體封裝件。如此，本發明中形成於該封裝膠體表面之凹槽深度大小可由金屬塊高度精密定義及控制，避免習知直接半蝕刻銅板時，因蝕刻深度不易控制，導致後續植設銲球高度發生不穩定問題，同時透過該凹槽可有效定位導電元件，避免習知透過拒銲層定位銲球時，所造成製程繁雜及成本增加問題，另外，因本發明中導電元件與金屬層接觸面包含有凹槽之底面及側邊，以產生足夠的共金結構，強化該導電元件和金屬層之接合強度，此外，該金屬層與封裝膠體間亦形成有包含凹槽底面及側邊等接觸面，可供該金屬層有效附著於該封裝膠體而不致發生脫層問題，再者，該封裝膠體於凹槽開口之角緣與導電元件接觸位置，因有金屬層附著，故得減低因應力集中現象而發生導電元件裂損問題。
第二實施例
請參閱第5A及5G圖，係為本發明之半導體封裝件及其製法第二實施例之示意圖。本實施例之半導體封裝件及其製法與前述實施例大致相同，主要差異係在金屬載板上形成金屬塊時，該金屬塊係呈多重柱狀，並形成有包覆該呈多重柱狀之金屬塊外表面的金屬層，俾於後續移除該金屬載板及金屬塊時，得以在封裝膠體表面形成其中具有凸出金屬層之凹槽，俾增加後續植設於該凹槽中之導電元件與金屬層之接觸面積及接合力。
如第5A圖所示，製備一金屬載板50，並於該金屬載板50之一表面上覆蓋第一阻層51，且令該第一阻層51形成有複數第一開口510，藉以定義出後續供與半導體晶片電性連接之導腳(terminal)位置51a及供接置半導體晶片之晶片座(die pad)位置51b。本實施例中該第一開口510係由複數小尺寸之開孔510’所構成。
如第5B圖所示，進行電鍍製程，以於構成該第一開口510之複數小尺寸開孔510’中形成導電柱520，亦即在該第一開口510中形成由複數導電柱520所構成之金屬塊52。
如第5C圖所示，移除該第一阻層51，並於該金屬載板50上覆蓋第二阻層53，且令該第二阻層53形成有複數第二開口530以完整外露出該由複數導電柱520所構成之金屬塊52。
如第5D圖所示，進行電鍍製程，以於該第二開口530中形成金屬層54，並使該金屬層54包覆該由複數導電柱520所構成之金屬塊52。
如第5E圖所示，移除該第二阻層53，並於該對應為晶片座位置51b之金屬層54上接置半導體晶片55，且透過該銲線56電性連接該半導體晶片55及對應為導腳位置51a之金屬層54，接著於該金屬載板50上形成包覆該半導體晶片55及銲線56之封裝膠體57。
如第5F圖所示，同時蝕刻移除該金屬載板50及由複數導電柱520所構成之金屬塊52，藉以在該封裝膠體57表面形成複數凹槽570，其中該凹槽570底面、側邊及自底面凸伸形成有先前覆蓋在由複數導電柱所構成之金屬塊外表面之金屬層54。
如第5G圖所示，於該凹槽570中植設如銲球之導電元件58，並使該導電元件58得以與該凹槽570底面、側邊及自底面凸伸之金屬層54有效接著與電性連接。
第三實施例
復請參閱第6圖，係為本發明之半導體封裝件第三實施例之示意圖。
本實施例之半導體封裝件與前述實施例大致相同，主要差異係在金屬載板上形成金屬塊後，欲形成包覆該金屬塊之金屬層時，較先前實施例增加第二阻層之第二開口尺寸，藉以在該金屬載板上形成包覆該金屬塊之金屬層64同時形成有延伸部分640，以供後續完成置晶、銲線作業、封裝模壓作業後，移除該金屬載板及金屬塊時，得以使該金屬層64形成於該封裝膠體67表面凹槽670之底面與側邊，同時使該金屬層延伸部640形成於該凹槽670周圍之封裝膠體67表面，藉以增加該金屬層64與導電元件68之接著面積。
上述實施例僅例示性說明本發明之原理及其功效，而非用於限制本發明，任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修飾與改變。因此，本發明之權利保護範圍，應如後述之申請專利範圍所列。
11．．．拒銲層
12．．．電鍍銲墊
13．．．晶片
14．．．銲線
15．．．封裝膠體
16．．．銲球
20．．．銅板
21．．．阻層
210．．．開孔
22．．．金屬銲墊
23．．．半導體晶片
24．．．銲線
25．．．封裝膠體
250．．．凹槽
26．．．銲球
40．．．載板
41．．．第一阻層
410．．．第一開口
41a．．．導腳位置
41b．．．晶片座位置
42．．．金屬塊
43．．．第二阻層
430．．．第二開口
44．．．金屬層
45．．．半導體晶片
46．．．銲線
47．．．封裝膠體
470．．．凹槽
48．．．導電元件
50．．．金屬載板
51．．．第一阻層
510．．．第一開口
51a．．．導腳位置
51b．．．晶片座位置
510’．．．開孔
520．．．導電柱
52．．．金屬塊
53．．．第二阻層
530．．．第二開口
54．．．金屬層
55．．．半導體晶片
56．．．銲線
57．．．封裝膠體
570．．．凹槽
58．．．導電元件
64．．．金屬層
640．．．延伸部分
67．．．封裝膠體
670．．．凹槽
68．．．導電元件
C．．．裂損
D．．．脫層
第1圖係顯示美國專利第5,830,800號之無承載件之半導體封裝件示意圖；第2A至2D圖係顯示美國專利第6,072,239號之無承載件之半導體封裝件製法示意圖；第3A及3B圖係顯示美國專利第6,072,239號之無承載件之半導體封裝件所存在銲球裂損及金屬銲墊脫層之缺失示意圖；第4A至4G圖係顯示本發明之半導體封裝件及其製法第一實施例之示意圖；第5A至5G圖係顯示本發明之半導體封裝件及其製法第二實施例之示意圖；以及第6圖係顯示本發明之半導體封裝件第三實施例之示意圖。
44．．．金屬層
45．．．半導體晶片
46．．．銲線
47．．．封裝膠體
470．．．凹槽
48．．．導電元件

Claims (18)

  1. 一種半導體封裝件之製法，係包括：提供一金屬材質之載板且於該載板上覆蓋第一阻層，並令該第一阻層形成有複數第一開口；進行電鍍製程，於該第一開口中形成有複數金屬塊；移除該第一阻層；於該載板上形成包覆該金屬塊之金屬層；將至少一半導體晶片電性連接至該金屬層；於該載板上形成包覆該半導體晶片之封裝膠體；移除該載板及金屬塊，藉以相對在該封裝膠體表面形成有複數之凹槽，俾外露出該凹槽內之金屬層；以及於該凹槽中植設導電元件。
  2. 如申請專利範圍第1項之半導體封裝件之製法，其中，該金屬層之製法係包括：於該載板上覆蓋第二阻層，並令該第二阻層形成有第二開口以外露出該金屬塊，其中該第二開口尺寸係大於該第一開口尺寸；進行電鍍製程，於該第二開口中形成該金屬層，並使該金屬層包覆該金屬塊；以及移除該第二阻層。
  3. 如申請專利範圍第1項之半導體封裝件之製法，其中，該金屬層定義出後續供與半導體晶片電性連接之導腳(terminal)位置及供接置半導體晶片之晶片座(die pad) 位置。
  4. 如申請專利範圍第3項之半導體封裝件之製法，其中，該對應接置於導腳位置上之金屬層的導電元件係供傳輸半導體晶片訊號，而對應接置於該晶片座位置上之金屬層的導電元件係供半導體晶片接地或導熱功能。
  5. 如申請專利範圍第1項之半導體封裝件之製法，其中，該半導體晶片於製程中係置於該金屬層或載板上。
  6. 如申請專利範圍第1項之半導體封裝件之製法，其中，該金屬層為金(Au)/鈀(Pd)/鎳(Ni)/鈀(Pd)、金(Au)/鎳(Ni)/金(Au)、及金(Au)/銅(Cu)/金(Au)之其中一者。
  7. 如申請專利範圍第1項之半導體封裝件之製法，其中，該金屬塊係呈多重柱狀，並形成有包覆該呈多重柱狀之金屬塊外表面的金屬層。
  8. 如申請專利範圍第7項之半導體封裝件之製法，其中，該金屬塊及金屬層之製法係包括：令該第一開口係由複數小尺寸之開孔所構成；進行電鍍製程，以於構成該第一開口之複數開孔中形成導電柱，藉以在該第一開口中形成由複數導電柱所構成之該金屬塊；移除該第一阻層；於該載板上覆蓋第二阻層，且令該第二阻層形成有複數第二開口以完整外露出該由複數導電柱所構成之金屬塊；進行電鍍製程，以於該第二開口中形成金屬層，並 使該金屬層包覆該由複數導電柱所構成之金屬塊；以及移除該第二阻層。
  9. 如申請專利範圍第8項之半導體封裝件之製法，復包括蝕刻移除該載板及由複數導電柱所構成之金屬塊，藉以在該封裝膠體表面形成複數凹槽，其中該凹槽底面、側邊及自底面凸伸形成有先前覆蓋在由複數導電柱所構成之金屬塊外表面之金屬層。
  10. 如申請專利範圍第1項之半導體封裝件之製法，其中，該金屬層復具有延伸部以覆蓋至該凹槽周圍之封裝膠體表面。
  11. 如申請專利範圍第1項之半導體封裝件之製法，其中，該半導體晶片透過銲線及覆晶之其中一方式而電性連接至該金屬層。
  12. 一種半導體封裝件，係包括：封裝膠體，且該封裝膠體表面形成有複數凹槽；金屬層，係覆蓋於該凹槽底面及側邊並連通該封裝膠體表面；半導體晶片，係內嵌於該封裝膠體中且電性連接至該金屬層；以及導電元件，係植設於該凹槽中且與該金屬層電性連接，其中，該導電元件與該金屬層係為不同材質。
  13. 如申請專利範圍第12項之半導體封裝件，其中，該金屬層定義有供與半導體晶片電性連接之導腳(terminal)部分及供接置半導體晶片之晶片座(die pad)部分。
  14. 如申請專利範圍第13項之半導體封裝件，其中，該對應接置於導腳位置上之金屬層的導電元件係供傳輸半導體晶片訊號，而對應接置於該晶片座位置上之金屬層的導電元件係供半導體晶片接地或導熱功能。
  15. 如申請專利範圍第12項之半導體封裝件，其中，該金屬層為金(Au)/鈀(Pd)/鎳(Ni)/鈀(Pd)、金(Au)/鎳(Ni)/金(Au)、及金(Au)/銅(Cu)/金(Au)之其中一者。
  16. 如申請專利範圍第12項之半導體封裝件，其中，該凹槽底面、側邊及自底面凸伸形成有金屬層。
  17. 如申請專利範圍第12項之半導體封裝件，其中，該金屬層復具有延伸部以形成於該凹槽周圍之封裝膠體表面。
  18. 如申請專利範圍第12項之半導體封裝件，其中，該半導體晶片透過銲線及覆晶之其中一方式而電性連接至該金屬層。
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US9312194B2 (en) 2012-03-20 2016-04-12 Stats Chippac Ltd. Integrated circuit packaging system with terminals and method of manufacture thereof
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