TWI462194B - 半導體封裝結構及其製作方法 - Google Patents
半導體封裝結構及其製作方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 65
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000008393 encapsulating agent Substances 0.000 claims description 90
- 239000002184 metal Substances 0.000 claims description 42
- 229910000679 solder Inorganic materials 0.000 claims description 33
- 229920002120 photoresistant polymer Polymers 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 24
- 239000007769 metal material Substances 0.000 claims description 20
- 238000000059 patterning Methods 0.000 claims description 4
- 239000000084 colloidal system Substances 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 56
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000002679 ablation Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
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Description
本發明是有關於一種半導體元件及其製作方法,且特別是有關於一種半導體封裝結構及其製作方法。
晶片封裝的目的在於保護裸露的晶片、降低晶片接點的密度及提供晶片良好的散熱。當晶片的接點數不斷地增加,而晶片的面積卻越來越小的情況下,勢必難以將晶片所有的接點以面矩陣的方式重新分佈於晶片的表面,即使晶片表面容納得下所有的接點,也將造成接點之間的間距過小,而影響後續銲接銲球時的電性可靠度。
因此,習知技術提出了可先利用封裝膠體封裝晶片來增加晶片的面積,其中晶片的主動表面與封裝膠體的底面暴露於外。之後,再於晶片的主動表面以及封裝膠體的底面上形成重配置線路層,並在重配置線路層的接點上分別形成銲球,來作為晶片與外界接點相電性連接的媒介。也就是說,晶片的主動表面與銲球是位於同一平面上。由於封裝時易產生溢膠的現象,而導致封裝膠體延伸至晶片的部分主動表面上,污染晶片之主動面,因此此方式無法應用於CMOS晶片。
再者,上述之方式亦無法利用垂直堆疊的方式將多個半導體元件(例如是晶片)封裝於同一封裝結構中。由於習知是透過封裝膠體封裝晶片來增加晶片的面積設計,但其重配置線路層僅位於晶片的主動表面及封裝膠體的底面上,因此無法透過堆疊的形式來堆疊晶片。故,如何有效縮小多個堆疊晶片之封裝結構的厚度與尺寸,同時兼顧封裝結構的電性可靠度,已成為亟待解決的課題。
本發明提供一種半導體封裝結構及其製作方法,具有低成本、製程簡單以及適於量產等優勢。
本發明提出一種半導體封裝結構的製作方法,其包括以下步驟。提供一晶片,其中晶片具有彼此相對的一主動表面與一背面。將晶片配置於一承載板上,其中主動表面朝向承載板。於承載板上形成一第一封裝膠體以覆蓋晶片。於第一封裝膠體上設置一金屬層。金屬層具有彼此相對的一上表面與一下表面、多個形成於上表面的凹陷以及多個形成於下表面且對應凹陷設置的突出,其中突出嵌於第一封裝膠體內。圖案化金屬層以於第一封裝膠體的部分區域上形成多個接墊,其中每一凹陷分別位於每一接墊之一頂表面上,而每一突出分別位於每一接墊之一底表面上。令承載板與第一封裝膠體分離。於第一封裝膠體中形成多個將突出暴露之通孔。於第一封裝膠體與晶片之主動表面上形成一重配置線路層,其中部分重配置線路層從第一封裝膠體延伸至晶片之主動表面上以及通孔中,以使晶片透過部分重配置線路層與接墊電性連接。於重配置線路層上形成多個第一銲球,其中部分第一銲球對應於接墊設置。
在本發明之一實施例中,上述形成凹陷與突出的方法包括:提供一金屬材料層;於金屬材料層的一第一表面上形成一第一圖案化光阻層;以第一圖案化光阻層為罩幕,移除部分金屬材料層以於金屬材料層之第一表面上形成凹陷;於金屬材料層的一第二表面上形成一第二圖案化光阻層;以及以第二圖案化光阻層為罩幕,移除部分金屬材料層以於金屬材料層之第二表面上形成突出。
在本發明之一實施例中,上述圖案化金屬層的方法包括:於金屬層的上表面上形成一第三圖案化光阻層;以及以第三圖案化光阻層為罩幕,移除部分金屬層直至部分第一封裝膠體被暴露。
在本發明之一實施例中,上述半導體封裝結構的製作方法,更包括:於每一接墊之頂表面上形成一第二銲球。
在本發明之一實施例中,上述半導體封裝結構的製作方法,更包括:形成一第二封裝膠體於第一封裝膠體上,其中第二封裝膠體覆蓋接墊與第一封裝膠體。
在本發明之一實施例中,上述半導體封裝結構的製作方法,更包括:形成第一銲球之後,進行一單體化程序,以形成多個各自獨立的封裝單元。
在本發明之一實施例中,上述之半導體封裝結構的製作方法,更包括:於第一封裝膠體呈一半固化狀態時,將金屬層設置於第一封裝膠體上,以使突出嵌入於第一封裝膠體內;以及於圖案化金屬層之前,同時對第一封裝膠體與金屬層進行一烘烤步驟,以固化第一封裝膠體。
本發明提出一種半導體封裝結構,其包括一晶片、一第一封裝膠體、一金屬層、一重配置線路層以及多個第一銲球。晶片具有彼此相對的一主動表面與一背面。第一封裝膠體覆蓋晶片且具有多個通孔,其中第一封裝膠體的一底面與晶片的主動表面實質上齊平。金屬層設置於部分第一封裝膠體上,且具有多個凹陷、多個對應凹陷設置的突出以及多個接墊,其中每一凹陷分別位於每一接墊之一頂表面上,而每一突出分別位於每一接墊之一底表面上,且通孔暴露出突出。重配置線路層配置於第一封裝膠體與晶片之主動表面上,其中部分重配置線路層從第一封裝膠體延伸至晶片之主動表面上以及通孔中,以使晶片透過部分重配置線路層與接墊電性連接。多個第一銲球配置於重配置線路層上,其中部分第一銲球對應於接墊設置。
在本發明之一實施例中,上述之半導體封裝結構更包括多個第二銲球,配置於接墊之頂表面上。
在本發明之一實施例中,上述之半導體封裝結構更包括一第二封裝膠體,配置於第一封裝膠體上,其中第二封裝膠體覆蓋接墊與第一封裝膠體。
基於上述,由於本發明是將預先形成之金屬層設置於第一封裝膠體上,因此本發明之半導體封裝結構除了具有較佳的散熱效能外,亦可透過金屬層來增加整體的半導體封裝結構的結構可靠度,以避免整體結構產生撓曲(warpage)的現象。再者,由於金屬層的製作具有製程簡單與適於量產等優勢,因此本發明之半導體封裝結構採用此金屬層亦可有效降低生產成本。
為讓本發明之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
圖1A至圖1G為本發明之一實施例之一種半導體封裝結構的製作方法的剖面示意圖。請先參考圖1A,本實施例的半導體封裝結構的製作方法包括以下步驟。首先,提供一晶片110,其中晶片110具有彼此相對的一主動表面112與一背面114以及位於主動表面112上的多個銲墊116。接著,並將晶片110配置於一承載板10上,其中晶片110的主動表面112朝向承載板10。
接著,請參考圖1B,於承載板10上形成一第一封裝膠體120以覆蓋晶片110與部分承載板10。
之後,請同時參考圖1C與圖1D,提供一金屬材料層130’,並於金屬材料層130’的一第一表面132’及一第二表面134’上全面性的塗佈覆蓋一層光阻層(未繪示),再藉由曝光顯影的方式,於第一圖案化光阻層20上暴露出部分第一表面132’,以及,於第二圖案化光阻層30上暴露出部分第二表面134’。接著,以第一圖案化光阻層20為罩幕,移除部分金屬材料層130’,以於金屬材料層130’之第一表面132’上形成多個凹陷136。再以第二圖案化光阻30層為罩幕,移除部分金屬材料層130’,以於金屬材料層130’之第二表面134’上形成多個突出138。之後,再移除第一圖案化光阻層20與第二圖案化光阻層30,藉以完成一金屬層130的製作。簡言之,本實施例之金屬層130具有彼此相對的一上表面132與一下表面134、多個形成於上表面132的凹陷136以及多個形成於下表面134且對應凹陷136設置的突出138。
接著,請參考圖1E,於第一封裝膠體120上設置金屬層130,其中金屬層130的突出138嵌於第一封裝膠體120內。於此必須說明的是,本實施例是於第一封裝膠體120呈現一半固化狀態時,將金屬層130設置於第一封裝膠體120上,如此一來,該突出138可輕易地嵌入於第一封裝膠體120內。接著,在同時對第一封裝膠體120與金屬層130進行一烘烤步驟,以進一步固化呈現半固化狀態之第一封裝膠體120。並於金屬層130的上表面132上形成一第三圖案化光阻層40,以圖案化金屬層130,其中第三圖案化光阻層40暴露出部分上表面132。
接著,請同時參考圖1E與圖1F,以第三圖案化光阻層40為罩幕,移除部分金屬層130,直至部分第一封裝膠體120被暴露,而於第一封裝膠體120的部分區域上形成多個接墊130a。其中,每一凹陷136分別位於每一接墊130a之一頂表面132a上,而每一突出138分別位於每一接墊130a之一底表面134a上。
之後,請參考圖1G,令承載板10與第一封裝膠體120分離,且於第一封裝膠體120中形成多個將突出138暴露之通孔122,其中形成通孔122的方法例如是以雷射燒蝕的方式移除部分第一封裝膠體120。接著,於第一封裝膠體120與晶片110之主動表面112上形成一重配置線路層140,其中部分重配置線路層140從第一封裝膠體120延伸至晶片110之主動表面112上以及通孔122中,以使晶片110上之銲墊116透過部分重配置線路層140與接墊130a電性連接。最後,於重配置線路層140上形成多個第一銲球150,其中部分第一銲球150對應於接墊130a設置。至此,已完成半導體封裝結構100的製作。
在結構上,請再參考圖1G,本發明之半導體封裝結構100包括晶片110、第一封裝膠體120、金屬層130、重配置線路層140以及多個第一銲球150。晶片110具有彼此相對的主動表面112與背面114。第一封裝膠體120覆蓋晶片110且具有通孔122,其中第一封裝膠體120的一底面124與晶片130的主動表面112實質上齊平。金屬層130設置於部分第一封裝膠體120上,且具有多個凹陷136、多個對應凹陷136設置的突出138以及多個接墊130a,其中每一凹陷136分別位於每一接墊130a之頂表面132a上,而每一突出138分別位於每一接墊130a之一底表面134a上,且通孔122暴露出突出138。重配置線路層140配置於第一封裝膠體120與晶片110之主動表面112上,其中部分重配置線路層140從晶片110之主動表面112上延伸至第一封裝膠體120以及通孔122中,以使晶片110的銲墊116透過部分重配置線路層140與接墊130a電性連接。第一銲球150配置於重配置線路層140上,其中部分第一銲球150對應於接墊130a設置。
圖1H繪示為本發明之一實施例之一種半導體封裝結構的剖面示意圖。請參考圖1H,本實施例之半導體封裝結構100a相似於圖1G之半導體封裝結構100,差異之處僅在於:本實施例之半導體封裝結構100a更包括於每一接墊130a之頂表面132a上形成一第二銲球160,其中第二銲球160嵌入於凹陷136中,且與第一銲球150對應設置。
圖2繪示為本發明之一實施例之一種堆疊多個半導體封裝結構的剖面示意圖。請參考圖2,本實施例是將多個半導體封裝結構100’、100、100b垂直疊置,其中半導體封裝結構100’與圖1G之半導體封裝結構100相似,而半導體封裝結構100與圖1G之半導體封裝結構100相同。半導體封裝結構100b與圖1G之半導體封裝結構100相似,其兩者差異之處在於:半導體封裝結構100b更包括一第二封裝膠體170於第一封裝膠體120上,其中第二封裝膠體170覆蓋接墊130a與第一封裝膠體120。再者,半導體封裝結構100’與圖1G之半導體封裝結構100相似,差異之處在於:半導體封裝結構100’為並未進行單體化程序之晶圓級的封裝結構,而半導體封裝結構100、100b則為晶片級的封裝結構。
如圖2所示,半導體封裝結構100、100b疊置於半導體封裝結構100’上,其中半導體封裝結構100的第一銲球150對應配置於半導體封裝結構100’的接墊130a上,而半導體封裝結構100b的第一銲球150對應配置於半導體封裝結構100的接墊130a上,如此一來,可有效減少整體的封裝厚度。再者,於疊置半導體封裝結構100、100b於半導體封裝結構100’上之後,亦可沿著切割線L對半導體封裝結構100’進行一單體化切割製程,以使半導體封裝結構100’形成多個各自獨立的封裝單元(未繪示)。
綜上所述,由於本發明是將事先已做好之金屬層設置於第一封裝膠體上,因此本發明之半導體封裝結構除了具有較佳的散熱效能外,亦可透過金屬層來增加整體的半導體封裝結構的結構可靠度,以避免整體結構產生撓曲(warpage)的現象。再者,由於金屬層的製作具有製程簡單與適於量產等優勢,因此本發明之半導體封裝結構採用此金屬層亦可有效降低生產成本。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10...承載板
20...第一圖案化光阻層
30...第二圖案化光阻層
40...第三圖案化光阻層
100、100’、100a、100b...半導體封裝結構
110...晶片
112...主動表面
114...背面
116...銲墊
120...第一封裝膠體
122...通孔
124...底面
130...金屬層
130’...金屬材料層
132...上表面
132’...第一表面
134’...第二表面
134...下表面
136...凹陷
138...突出
130a...接墊
132a...頂表面
134a...底表面
140...重配置線路層
150...第一銲球
160...第二銲球
170...第二封裝膠體
L...切割線
圖1A至圖1G為本發明之一實施例之一種半導體封裝結構的製作方法的剖面示意圖。
圖1H繪示為本發明之一實施例之一種半導體封裝結構的剖面示意圖。
圖2繪示為本發明之一實施例之一種堆疊多個半導體封裝結構的剖面示意圖。
100...半導體封裝結構
110...晶片
112...主動表面
114...背面
116...銲墊
120...第一封裝膠體
122...通孔
124...底面
130...金屬層
130a...接墊
132...上表面
132a...頂表面
134...下表面
134a...底表面
136...凹陷
138...突出
140...重配置線路層
150...第一銲球
Claims (10)
- 一種半導體封裝結構的製作方法,包括:提供一晶片,具有彼此相對的一主動表面與一背面;將該晶片配置於一承載板上,其中該主動表面朝向該承載板;於該承載板上形成一第一封裝膠體以覆蓋該晶片;於該第一封裝膠體上設置一金屬層,該金屬層具有彼此相對的一上表面與一下表面、多個形成於該上表面的凹陷以及多個形成於該下表面且對應該些凹陷設置的突出,其中該些突出嵌於該第一封裝膠體內;圖案化該金屬層以於該第一封裝膠體的部分區域上形成多個接墊,其中各該凹陷分別位於各該接墊之一頂表面上,而各該突出分別位於各該接墊之一底表面上;令該承載板與該第一封裝膠體分離;於該第一封裝膠體中形成多個將該些突出暴露之通孔;於該第一封裝膠體與該晶片之該主動表面上形成一重配置線路層,其中部分該重配置線路層從該第一封裝膠體延伸至該晶片之該主動表面上以及該些通孔中,以使該晶片透過部分該重配置線路層與該些接墊電性連接;以及於該重配置線路層上形成多個第一銲球,其中部分該些第一銲球對應於該些接墊設置。
- 如申請專利範圍第1項所述之半導體封裝結構的製作方法,其中形成該些凹陷與該些突出的方法包括:提供一金屬材料層;於該金屬材料層的一第一表面上形成一第一圖案化光阻層;以該第一圖案化光阻層為罩幕,移除部分該金屬材料層以於該金屬材料層之該第一表面上形成該些凹陷;於該金屬材料層的一第二表面上形成一第二圖案化光阻層;以及以該第二圖案化光阻層為罩幕,移除部分該金屬材料層以於該金屬材料層之該第二表面上形成該些突出。
- 如申請專利範圍第1項所述之半導體封裝結構的製作方法,其中圖案化該金屬層的方法包括:於該金屬層的該上表面上形成一第三圖案化光阻層;以及以該第三圖案化光阻層為罩幕,移除部分該金屬層直至部分該第一封裝膠體被暴露。
- 如申請專利範圍第1項所述之半導體封裝結構的製作方法,更包括:於各該接墊之該頂表面上形成一第二銲球。
- 如申請專利範圍第1項所述之半導體封裝結構的製作方法,更包括:形成一第二封裝膠體於該第一封裝膠體上,其中該第二封裝膠體覆蓋該些接墊與該第一封裝膠體。
- 如申請專利範圍第1項所述之半導體封裝結構的製作方法,更包括:形成該些第一銲球之後,進行一單體化程序,以形成多個各自獨立的封裝單元。
- 如申請專利範圍第1項所述之半導體封裝結構的製作方法,更包括:於該第一封裝膠體呈一半固化狀態時,將該金屬層設置於該第一封裝膠體上,以使該些突出嵌入於該第一封裝膠體內;以及於圖案化該金屬層之前,同時對該第一封裝膠體與該金屬層進行一烘烤步驟,以固化該第一封裝膠體。
- 一種半導體封裝結構,包括:一晶片,具有彼此相對的一主動表面與一背面;一第一封裝膠體,覆蓋該晶片且具有多個通孔,其中該第一封裝膠體的一底面與該晶片的該主動表面實質上齊平;一金屬層,設置於部分該第一封裝膠體上,且具有多個凹陷、多個對應該些凹陷設置的突出以及多個接墊,其中各該凹陷分別位於各該接墊之一頂表面上,而各該突出分別位於各該接墊之一底表面上,且該些通孔暴露出該些突出;一重配置線路層,配置於該第一封裝膠體與該晶片之該主動表面上,其中部分該重配置線路層從該第一封裝膠體延伸至該晶片之該主動表面上以及該些通孔中,以使該晶片透過部分該重配置線路層與該些接墊電性連接;以及多個第一銲球,配置於該重配置線路層上,其中部分該些第一銲球對應於該些接墊設置。
- 如申請專利範圍第8項所述之半導體封裝結構,更包括多個第二銲球,配置於該些接墊之該些頂表面上。
- 如申請專利範圍第8項所述之半導體封裝結構,更包括一第二封裝膠體,配置於該第一封裝膠體上,其中該第二封裝膠體覆蓋該些接墊與該第一封裝膠體。
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US20080157358A1 (en) * | 2007-01-03 | 2008-07-03 | Advanced Chip Engineering Technology Inc. | Wafer level package with die receiving through-hole and method of the same |
TWI387074B (zh) * | 2008-06-05 | 2013-02-21 | Chipmos Technologies Inc | 晶粒堆疊結構及其形成方法 |
CN101615583B (zh) * | 2008-06-25 | 2011-05-18 | 南茂科技股份有限公司 | 芯片堆栈结构的形成方法 |
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Also Published As
Publication number | Publication date |
---|---|
US20130049198A1 (en) | 2013-02-28 |
CN102956511A (zh) | 2013-03-06 |
CN102956511B (zh) | 2015-08-19 |
TW201310554A (zh) | 2013-03-01 |
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