JP2009026805A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP2009026805A JP2009026805A JP2007185710A JP2007185710A JP2009026805A JP 2009026805 A JP2009026805 A JP 2009026805A JP 2007185710 A JP2007185710 A JP 2007185710A JP 2007185710 A JP2007185710 A JP 2007185710A JP 2009026805 A JP2009026805 A JP 2009026805A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- package
- resin layer
- pad
- sealing resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 87
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 136
- 238000007789 sealing Methods 0.000 claims abstract description 90
- 229920005989 resin Polymers 0.000 claims abstract description 85
- 239000011347 resin Substances 0.000 claims abstract description 85
- 239000004020 conductor Substances 0.000 claims abstract description 26
- 238000000465 moulding Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 23
- 239000002184 metal Substances 0.000 abstract description 16
- 229910052751 metal Inorganic materials 0.000 abstract description 16
- 238000012545 processing Methods 0.000 abstract description 9
- 239000011162 core material Substances 0.000 description 19
- 229910000679 solder Inorganic materials 0.000 description 13
- 239000002082 metal nanoparticle Substances 0.000 description 6
- 239000012212 insulator Substances 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 4
- 230000035515 penetration Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- YZCKVEUIGOORGS-UHFFFAOYSA-N Hydrogen atom Chemical compound [H] YZCKVEUIGOORGS-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
- H01L21/481—Insulating layers on insulating parts, with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
【解決手段】半導体チップ44とバンプ68とは、封止樹脂層50により封止されている。封止樹脂層50は、半導体チップ44の周囲を覆うと共に、封止樹脂層50を貫通し配線20に到達する複数の貫通孔32を備えるように、モールド成形(金型成形)により形成されている。各々の貫通孔32内には、導電性材料34が充填されて、貫通電極36とされている。貫通電極36の一端は端面36Aとして封止樹脂層50の表面に露出し、貫通電極36の他端は配線20に電気的に接続されている。
【選択図】図1
Description
図1(A)は本発明の実施の形態に係る両面電極パッケージの構成を示す概略断面図である。図1(B)は同じ両面電極パッケージを表面側から見た平面図である。図1(A)は図1(B)のA−A断面図である。
次に、上述した両面電極パッケージ10を製造する製造方法について説明する。図3〜図11は本実施の形態に係る両面電極パッケージ10の製造工程を示す図である。この製造工程では、複数のパッケージ基板12が形成された単一の基板フレーム60が用いられる。この基板フレーム60上には、パッケージ基板毎に、両面電極パッケージの構造が形成される。最後に、基板フレーム60をスクライビングすることにより、個々の両面電極パッケージに分割される。以下、両面電極パッケージ10の製造工程を、順を追って説明する。
まず、複数のパッケージ基板が形成された単一の基板フレームを用意する。
図3(A)及び(B)は基板フレームの準備工程を示す図である。図3(A)は基板フレームの部分断面図であり、図3(B)は基板フレームを表面側から見た平面図である。
次に、個々のパッケージ基板12のチップ配置領域14に、半導体チップ44を配置する。図4(A)及び(B)は半導体チップの配置工程を示す図である。図4(A)は基板フレームの部分断面図であり、図4(B)は基板フレームを表面側から見た平面図である。ICチップやLSIチップなどの半導体チップ44は、同じ回路を複数形成した半導体ウェーハを、個々の回路に分割(ダイシング)して作製されている。半導体チップ44の表面には、図示はしてないが、複数の電極が設けられている。
次に、半導体チップ44を封止樹脂により封止する。
図5〜図7は半導体チップの封止工程を示す図である。図5は金型にセットされた状態での基板フレームの部分断面図であり、図6(A)及び(B)は金型の部分断面図である。図7(A)は樹脂封止後の基板フレームの部分断面図であり、図7(B)は基板フレームを表面側から見た平面図である。図7(B)からは、1組(9個)のパッケージ基板12を備えた基板フレーム60の一部を図示する。
次に、貫通孔32に導電性材料34を充填して貫通電極36を形成する。
図8及び図9は貫通電極の形成工程を示す図である。図8(A)はメタルマスク取り付け後の基板フレームの部分断面図であり、図8(B)は基板フレームを表面側から見た平面図である。また、図9(A)は貫通電極が形成された基板フレームの部分断面図であり、図9(B)は基板フレームを表面側から見た平面図である。
次に、封止樹脂層50の表面50M上で再配線を行う。
図10(A)及び(B)は再配線工程を示す図である。図10(A)は再配線後の基板フレームの部分断面図であり、図10(B)は基板フレームを表面側から見た平面図である。
最後に、基板フレーム60をスクライビングして各パッケージを個片化する。
図11(A)及び(B)はスクライビング工程を示す図である。図11(A)はスクライビング前の基板フレームの部分断面図であり、図11(B)は基板フレームを表面側から見た平面図である。
以下、変形例について説明する。
12 パッケージ基板
14 チップ配置領域
16 コア材
20 配線
24 ビア
26 導電性材料
28 貫通電極
30 接続パッド
32 貫通孔
34 導電性材料
36 貫通電極
36A 端面
42 ソルダレジスト
44 半導体チップ
50M 表面
50 封止樹脂層
52 再配線パッド
54 配線
60 基板フレーム
62 領域
64 パッケージ構造
64 両面電極パッケージ構造
66 通過領域
68 バンプ
70 モールド金型
72 平板部
74 外枠部
76 突起部
80 メタルマスク
82 開口部
Claims (7)
- 表面に半導体チップの電極と電気的に接続される電極パッドが形成されると共に、裏面に前記電極パッドと電気的に接続された外部接続パッドが形成されたパッケージ基板と、
前記パッケージ基板の表面に載置され、前記電極が前記電極パッドに電気的に接続された半導体チップと、
前記電極パッドに到達する複数の貫通孔を備えるように金型成形され、前記半導体チップを封止樹脂で封止する封止樹脂層と、
前記封止樹脂層に形成された貫通孔を導電性材料で埋めて形成され、一端が前記電極パッドと電気的に接続されると共に、他端が前記封止樹脂層の表面に露出した貫通電極と、
を含むことを特徴とする半導体装置。 - 前記封止樹脂層の表面に形成された再配線パッドと、
前記封止樹脂層の表面に形成され、前記貫通電極の他端と前記再配線パッドとを電気的に接続する接続配線と、
を更に含むことを特徴とする請求項1に記載の半導体装置。 - 複数のパッケージ基板に分割されるフレーム基板に、パッケージ毎に、パッケージ基板の表面に半導体チップの電極と電気的に接続される電極パッドを形成すると共に、パッケージ基板の裏面に前記電極パッドと電気的に接続された外部接続パッドを形成する工程と、
パッケージ毎に、前記パッケージ基板の表面に前記半導体チップを載置し、前記電極を前記電極パッドに電気的に接続する工程と、
パッケージ毎に前記電極パッドに到達する複数の貫通孔が形成されるように、金型内側に前記電極パッドに圧接される柱状突起が形成された金型を用い、該金型を前記フレーム基板の表面に密着させて封止樹脂を注入成形し、前記半導体チップを封止する工程と、
前記半導体チップを封止する封止樹脂層に形成された複数の貫通孔の各々に導電性材料を充填して、一端が前記電極パッドと電気的に接続されると共に、他端が前記封止樹脂層の表面に露出した貫通電極を形成する工程と、
前記半導体チップの各々がパッケージ毎に収納されると共に、前記電極パッド、前記外部接続パッド、前記貫通電極、及び前記封止樹脂層の各々がパッケージ毎に形成された前記フレーム基板をスクライビングして、個々のパッケージに分割する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 請求項2に記載の半導体装置を製造する半導体装置の製造方法であって、
複数のパッケージ基板に分割されるフレーム基板に、パッケージ毎に、パッケージ基板の表面に半導体チップの電極と電気的に接続される電極パッドを形成すると共に、パッケージ基板の裏面に前記電極パッドと電気的に接続された外部接続パッドを形成する工程と、
パッケージ毎に、前記パッケージ基板の表面に前記半導体チップを載置し、前記電極を前記電極パッドに電気的に接続する工程と、
パッケージ毎に前記電極パッドに到達する複数の貫通孔が形成されるように、金型内側に前記電極パッドに圧接される柱状突起が形成された金型を用い、該金型を前記フレーム基板の表面に密着させて封止樹脂を注入成形し、前記半導体チップを封止する工程と、
前記半導体チップを封止する封止樹脂層に形成された複数の貫通孔の各々に導電性材料を充填して、一端が前記電極パッドと電気的に接続されると共に、他端が前記封止樹脂層の表面に露出した貫通電極を形成する工程と、
前記封止樹脂層の表面に、パッケージ毎に、再配線パッドを形成すると共に、前記貫通電極の他端と前記再配線パッドとを電気的に接続する接続配線を形成する工程と、
前記半導体チップの各々がパッケージ毎に収納されると共に、前記電極パッド、前記外部接続パッド、前記貫通電極、前記封止樹脂層、前記再配線パッド、及び前記接続配線の各々がパッケージ毎に形成された前記フレーム基板をスクライビングして、個々のパッケージに分割する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記複数の貫通孔は前記半導体チップを取り囲むように形成されていることを特徴とする請求項3又は4に記載の半導体装置の製造方法。
- 前記金型内側の前記柱状突起は、前記金型と一体に形成されたことを特徴とする請求項3から5までのいずれか1項に記載の半導体装置の製造方法。
- 前記金型内側の前記柱状突起は、前記金型にピンを差し込んで形成されたことを特徴とする請求項3から5までのいずれか1項に記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007185710A JP5215605B2 (ja) | 2007-07-17 | 2007-07-17 | 半導体装置の製造方法 |
US12/219,181 US8053275B2 (en) | 2007-07-17 | 2008-07-17 | Semiconductor device having double side electrode structure and method of producing the same |
US13/176,256 US8643161B2 (en) | 2007-07-17 | 2011-07-05 | Semiconductor device having double side electrode structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007185710A JP5215605B2 (ja) | 2007-07-17 | 2007-07-17 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009026805A true JP2009026805A (ja) | 2009-02-05 |
JP5215605B2 JP5215605B2 (ja) | 2013-06-19 |
Family
ID=40264179
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007185710A Active JP5215605B2 (ja) | 2007-07-17 | 2007-07-17 | 半導体装置の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (2) | US8053275B2 (ja) |
JP (1) | JP5215605B2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20160010305A (ko) | 2014-07-18 | 2016-01-27 | 토와 가부시기가이샤 | 전자 부품 패키지의 제조 방법 |
US9397057B2 (en) | 2014-06-02 | 2016-07-19 | Kabushiki Kaisha Toshiba | Plurality of semiconductor devices in resin with a via |
Families Citing this family (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3942190B1 (ja) * | 2006-04-25 | 2007-07-11 | 国立大学法人九州工業大学 | 両面電極構造の半導体装置及びその製造方法 |
JP5215587B2 (ja) * | 2007-04-27 | 2013-06-19 | ラピスセミコンダクタ株式会社 | 半導体装置 |
US8106496B2 (en) * | 2007-06-04 | 2012-01-31 | Stats Chippac, Inc. | Semiconductor packaging system with stacking and method of manufacturing thereof |
JP2010212575A (ja) * | 2009-03-12 | 2010-09-24 | Casio Computer Co Ltd | 半導体装置の製造方法 |
US8264091B2 (en) * | 2009-09-21 | 2012-09-11 | Stats Chippac Ltd. | Integrated circuit packaging system with encapsulated via and method of manufacture thereof |
CN102575084B (zh) * | 2009-09-29 | 2017-03-29 | 日立化成工业株式会社 | 多层树脂片及其制造方法、多层树脂片固化物的制造方法、以及高热传导树脂片层叠体及其制造方法 |
TWI469289B (zh) * | 2009-12-31 | 2015-01-11 | 矽品精密工業股份有限公司 | 半導體封裝結構及其製法 |
US8716873B2 (en) * | 2010-07-01 | 2014-05-06 | United Test And Assembly Center Ltd. | Semiconductor packages and methods of packaging semiconductor devices |
JP5826532B2 (ja) * | 2010-07-15 | 2015-12-02 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
JP2012114173A (ja) * | 2010-11-23 | 2012-06-14 | Shinko Electric Ind Co Ltd | 半導体装置の製造方法及び半導体装置 |
US9269685B2 (en) | 2011-05-09 | 2016-02-23 | Infineon Technologies Ag | Integrated circuit package and packaging methods |
US9425116B2 (en) * | 2011-05-09 | 2016-08-23 | Infineon Technologies Ag | Integrated circuit package and a method for manufacturing an integrated circuit package |
US8530277B2 (en) * | 2011-06-16 | 2013-09-10 | Stats Chippac Ltd. | Integrated circuit packaging system with package on package support and method of manufacture thereof |
JP5588409B2 (ja) * | 2011-09-05 | 2014-09-10 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP5917899B2 (ja) * | 2011-11-29 | 2016-05-18 | 日産自動車株式会社 | 薄型電池及び薄型電池の製造方法 |
US9576873B2 (en) * | 2011-12-14 | 2017-02-21 | STATS ChipPAC Pte. Ltd. | Integrated circuit packaging system with routable trace and method of manufacture thereof |
US8623711B2 (en) * | 2011-12-15 | 2014-01-07 | Stats Chippac Ltd. | Integrated circuit packaging system with package-on-package and method of manufacture thereof |
US8629567B2 (en) | 2011-12-15 | 2014-01-14 | Stats Chippac Ltd. | Integrated circuit packaging system with contacts and method of manufacture thereof |
US9219029B2 (en) | 2011-12-15 | 2015-12-22 | Stats Chippac Ltd. | Integrated circuit packaging system with terminals and method of manufacture thereof |
KR101867955B1 (ko) | 2012-04-13 | 2018-06-15 | 삼성전자주식회사 | 패키지 온 패키지 장치 및 이의 제조 방법 |
US9331007B2 (en) * | 2012-10-16 | 2016-05-03 | Stats Chippac, Ltd. | Semiconductor device and method of forming conductive ink layer as interconnect structure between semiconductor packages |
KR102067155B1 (ko) * | 2013-06-03 | 2020-01-16 | 삼성전자주식회사 | 연결단자를 갖는 반도체 장치 및 그의 제조방법 |
US9406533B2 (en) | 2013-06-27 | 2016-08-02 | STATS ChipPAC Pte. Ltd. | Methods of forming conductive and insulating layers |
WO2015099684A1 (en) * | 2013-12-23 | 2015-07-02 | Intel Corporation | Package on package architecture and method for making |
US9202742B1 (en) | 2014-01-15 | 2015-12-01 | Stats Chippac Ltd. | Integrated circuit packaging system with pattern-through-mold and method of manufacture thereof |
US9761919B2 (en) * | 2014-02-25 | 2017-09-12 | Tesla, Inc. | Energy storage system with heat pipe thermal management |
CN104078432A (zh) * | 2014-07-15 | 2014-10-01 | 南通富士通微电子股份有限公司 | Pop封装结构 |
US20170178990A1 (en) | 2015-12-17 | 2017-06-22 | Intel Corporation | Through-mold structures |
US9490192B1 (en) * | 2015-12-30 | 2016-11-08 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method thereof |
US9991206B1 (en) * | 2017-04-05 | 2018-06-05 | Powertech Technology Inc. | Package method including forming electrical paths through a mold layer |
WO2020188806A1 (ja) * | 2019-03-20 | 2020-09-24 | 三菱電機株式会社 | 半導体装置 |
CN110444526A (zh) * | 2019-07-23 | 2019-11-12 | 中国科学技术大学 | 一种量子处理器芯片结构及其封装结构和制作方法 |
US11515174B2 (en) * | 2019-11-12 | 2022-11-29 | Micron Technology, Inc. | Semiconductor devices with package-level compartmental shielding and associated systems and methods |
JP2021125643A (ja) * | 2020-02-07 | 2021-08-30 | キオクシア株式会社 | 半導体装置およびその製造方法 |
CN111834329B (zh) * | 2020-06-30 | 2021-12-24 | 江苏长电科技股份有限公司 | 一种半导体封装结构及其制造方法 |
US11562936B2 (en) | 2020-08-31 | 2023-01-24 | Amkor Technology Singapore Holding Pte. Ltd. | Electrionic devices with interposer and redistribution layer |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1167975A (ja) * | 1997-08-15 | 1999-03-09 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2002158312A (ja) * | 2000-11-17 | 2002-05-31 | Oki Electric Ind Co Ltd | 3次元実装用半導体パッケージ、その製造方法、および半導体装置 |
JP2003174122A (ja) * | 2001-12-04 | 2003-06-20 | Toshiba Corp | 半導体装置 |
JP2004119863A (ja) * | 2002-09-27 | 2004-04-15 | Sanyo Electric Co Ltd | 回路装置およびその製造方法 |
JP2006253281A (ja) * | 2005-03-09 | 2006-09-21 | Matsushita Electric Ind Co Ltd | 樹脂パッケージの製造方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001339011A (ja) * | 2000-03-24 | 2001-12-07 | Shinko Electric Ind Co Ltd | 半導体装置およびその製造方法 |
TW511405B (en) * | 2000-12-27 | 2002-11-21 | Matsushita Electric Ind Co Ltd | Device built-in module and manufacturing method thereof |
US6856007B2 (en) * | 2001-08-28 | 2005-02-15 | Tessera, Inc. | High-frequency chip packages |
WO2003049184A1 (en) * | 2001-12-07 | 2003-06-12 | Fujitsu Limited | Semiconductor device and method for manufacturing the same |
US8148803B2 (en) * | 2002-02-15 | 2012-04-03 | Micron Technology, Inc. | Molded stiffener for thin substrates |
JP2003249604A (ja) | 2002-02-25 | 2003-09-05 | Kato Denki Seisakusho:Kk | 樹脂封止半導体装置およびその製造方法、樹脂封止半導体装置に使用されるリードフレーム、ならびに半導体モジュール装置 |
US7394663B2 (en) * | 2003-02-18 | 2008-07-01 | Matsushita Electric Industrial Co., Ltd. | Electronic component built-in module and method of manufacturing the same |
US7141884B2 (en) * | 2003-07-03 | 2006-11-28 | Matsushita Electric Industrial Co., Ltd. | Module with a built-in semiconductor and method for producing the same |
JP4403821B2 (ja) | 2004-02-17 | 2010-01-27 | ソニー株式会社 | パッケージ基板とその製造方法、及び半導体装置とその製造方法、ならびに積層構造体 |
TWI256092B (en) * | 2004-12-02 | 2006-06-01 | Siliconware Precision Industries Co Ltd | Semiconductor package and fabrication method thereof |
TWI245388B (en) * | 2005-01-06 | 2005-12-11 | Phoenix Prec Technology Corp | Three dimensional package structure of semiconductor chip embedded in substrate and method for fabricating the same |
US7640655B2 (en) * | 2005-09-13 | 2010-01-05 | Shinko Electric Industries Co., Ltd. | Electronic component embedded board and its manufacturing method |
SG135074A1 (en) * | 2006-02-28 | 2007-09-28 | Micron Technology Inc | Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices |
US20080136004A1 (en) * | 2006-12-08 | 2008-06-12 | Advanced Chip Engineering Technology Inc. | Multi-chip package structure and method of forming the same |
JP5215587B2 (ja) * | 2007-04-27 | 2013-06-19 | ラピスセミコンダクタ株式会社 | 半導体装置 |
JP5179787B2 (ja) * | 2007-06-22 | 2013-04-10 | ラピスセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
-
2007
- 2007-07-17 JP JP2007185710A patent/JP5215605B2/ja active Active
-
2008
- 2008-07-17 US US12/219,181 patent/US8053275B2/en not_active Expired - Fee Related
-
2011
- 2011-07-05 US US13/176,256 patent/US8643161B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1167975A (ja) * | 1997-08-15 | 1999-03-09 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2002158312A (ja) * | 2000-11-17 | 2002-05-31 | Oki Electric Ind Co Ltd | 3次元実装用半導体パッケージ、その製造方法、および半導体装置 |
JP2003174122A (ja) * | 2001-12-04 | 2003-06-20 | Toshiba Corp | 半導体装置 |
JP2004119863A (ja) * | 2002-09-27 | 2004-04-15 | Sanyo Electric Co Ltd | 回路装置およびその製造方法 |
JP2006253281A (ja) * | 2005-03-09 | 2006-09-21 | Matsushita Electric Ind Co Ltd | 樹脂パッケージの製造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9397057B2 (en) | 2014-06-02 | 2016-07-19 | Kabushiki Kaisha Toshiba | Plurality of semiconductor devices in resin with a via |
KR20160010305A (ko) | 2014-07-18 | 2016-01-27 | 토와 가부시기가이샤 | 전자 부품 패키지의 제조 방법 |
KR20170040150A (ko) | 2014-07-18 | 2017-04-12 | 토와 가부시기가이샤 | 전자 부품 패키지의 제조 방법 |
Also Published As
Publication number | Publication date |
---|---|
US8053275B2 (en) | 2011-11-08 |
US8643161B2 (en) | 2014-02-04 |
US20090020882A1 (en) | 2009-01-22 |
US20110260334A1 (en) | 2011-10-27 |
JP5215605B2 (ja) | 2013-06-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5215605B2 (ja) | 半導体装置の製造方法 | |
JP5280014B2 (ja) | 半導体装置及びその製造方法 | |
JP5215587B2 (ja) | 半導体装置 | |
JP5179787B2 (ja) | 半導体装置及びその製造方法 | |
JP5043743B2 (ja) | 半導体装置の製造方法 | |
US9165878B2 (en) | Semiconductor packages and methods of packaging semiconductor devices | |
JP5579402B2 (ja) | 半導体装置及びその製造方法並びに電子装置 | |
TWI614848B (zh) | 電子封裝結構及其製法 | |
KR20080053241A (ko) | 멀티―칩 패키지 구조 및 그 제조 방법 | |
US20210125965A1 (en) | Semiconductor device package and method of manufacturing the same | |
JP2004214543A (ja) | 半導体装置及びその製造方法 | |
KR20240017393A (ko) | 반도체 장치 및 이의 제조 방법 | |
TWI736859B (zh) | 電子封裝件及其製法 | |
CN213782012U (zh) | 半导体封装结构 | |
JP2006228897A (ja) | 半導体装置 | |
JP2004165190A (ja) | 半導体装置及びその製造方法 | |
JP2020129637A (ja) | 電子装置及び電子装置の製造方法 | |
JP2012134572A (ja) | 半導体装置 | |
TWI607530B (zh) | 封裝裝置與其製作方法 | |
CN116072634A (zh) | 电子封装件及其制法 | |
JP2011029370A (ja) | 積層型半導体装置及びその製造方法 | |
JP2016219535A (ja) | 電子回路装置 | |
WO2014171403A1 (ja) | 半導体装置 | |
CN113990759A (zh) | 半导体封装方法及半导体封装结构 | |
TW202036796A (zh) | 無基板半導體封裝結構及其製法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20081224 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20090209 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100517 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100901 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120522 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120723 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20121002 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121129 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130226 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130301 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5215605 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160308 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160308 Year of fee payment: 3 |